History log of /linux-master/arch/arm/mach-rockchip/pm.h
Revision Date Author Comments
# 2025cf9e 29-May-2019 Thomas Gleixner <tglx@linutronix.de>

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation this program
is distributed in the hope it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 263 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>


# 9bb91ae9 22-Jul-2015 Heiko Stuebner <heiko@sntech.de>

ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend

PMU_GPIOINT_WAKEUP_EN seems needed when entering the shallow suspend
(with logic staying on) but does not seem to be needed for the deep
suspend for unknown reasons.
Testing revealed that this setting really is necessary to reliably
resume the veyron devices from suspend.

Reported-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>


# d1d3a1a1 22-Jul-2015 Heiko Stuebner <heiko@sntech.de>

ARM: rockchip: set correct stabilization thresholds in suspend

Currently the stabilization thresholds for the oscillator and external pmu
are statically set to 30ms based on a 32kHz clock rate. This leaves out the
case when we don't switch to the 32kHz clock when only entering the shallow
suspend mode where the logic keeps running.

So, set the correct threshold after we have determined if we switch to the
32kHz clock or stay with the 24MHz one. Also set the oscillator-
stabilization to 0 if it is kept running during suspend, as it of course
does not need to stabilize then.

Reported-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>


# e6ef15e4 23-Jun-2015 Chris Zhong <zyw@rock-chips.com>

ARM: rockchip: remove some useless macro in pm.h

These are actually not used in the pm code, as we moved suspend handling
to the clock driver, remove them here.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>


# 3f937cf3 13-May-2015 Heiko Stuebner <heiko@sntech.de>

Revert "ARM: rockchip: fix undefined instruction of reset_ctrl_regs"

This reverts commit b403125d3bbf8046c1186e1a49cb17bb5551db14.

As reported by Chris, both commits
b403125 "ARM: rockchip: fix undefined instruction of reset_ctrl_regs"
0ea001d "ARM: rockchip: disable dapswjdp during suspend"
actually fix the same issue and b403125 is the older one, which got
superseded by 0ea001d. Therefore revert the obsolete one again.

Reported-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>


# b403125d 21-Mar-2015 Chris Zhong <zyw@rock-chips.com>

ARM: rockchip: fix undefined instruction of reset_ctrl_regs

Sometimes the debug module may not work well after resume, since it has
not been correctly reset when wakeup from suspend. That cause system
crash during reusme, and a 'undefined instruction' is displayed on the
console. Set the GRF_FORCE_JTAG bit of RK3288_GRF_SOC_CON0 can ensure
that debug modul is reset. And we can change the value of
RK3288_GRF_SOC_CON0 back when system resume.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>

According to discussions, there does not seem a better solution available.
Please also see the potential security implication described in the
comment inline in the code.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>


# 0ea001d3 14-Apr-2015 Chris Zhong <zyw@rock-chips.com>

ARM: rockchip: disable dapswjdp during suspend

Reset dapswjdp is controlled by JTAG_TRSTN, if the iomux of this pin is
not "jtag_trstn". the AP would think this pin is always high, so it can
not reset before resume. When system resume, but the dapswjdp is not in
a default state, it may Access some illegal address, it cause system
crash during resume.
Let's disable this jtag function by clear the dapdeviceen bit, it
prohibit the dapswjdp to access memory and registers. This bit would
be enable in MASKROM, so we need clear it in suspend everytime.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>


# a0307d18 09-Feb-2015 Chris Zhong <zyw@rock-chips.com>

ARM: rockchip: disable watchdog during suspend

The watchdog clock should be disable in dw_wdt_suspend, but we set a
dummy clock to watchdog for rk3288. So the watchdog will continue to
work during suspend. And we switch the system clock to 32khz from 24Mhz,
during suspend, so the watchdog timer over count will increase to
755 times, about 12.5 hours, the original value is 60 seconds. So
watchdog will reset the system over a night, but voltage are all
incorrect, then it hang on reset.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>


# aefc7c75 09-Feb-2015 Chris Zhong <zyw@rock-chips.com>

ARM: rockchip: decrease the wait time for resume

The register-default delay time for wait the 24MHz OSC stabilization as well
as PMU stabilization is 750ms, let's decrease them to a still safe 30ms.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>


# c8823e7a 27-Jan-2015 Arnd Bergmann <arnd@arndb.de>

ARM: rockchip: make rockchip_suspend_init conditional

If CONFIG_PM_SLEEP is disabled, we get a build error for rockchips:

arch/arm/mach-rockchip/built-in.o: In function `rockchip_dt_init':
:(.init.text+0x1c): undefined reference to `rockchip_suspend_init'

This adds an inline alternative for that case.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org


# 9c1ec8e1 01-Dec-2014 Chris Zhong <zyw@rock-chips.com>

ARM: rockchip: add suspend and resume for RK3288

It's a basic version of suspend and resume for rockchip,
it only support RK3288 now.

Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>