1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * DRA7xx CM1 instance offset macros
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Generated by code originally written by:
8 * Paul Walmsley (paul@pwsan.com)
9 * Rajendra Nayak (rnayak@ti.com)
10 * Benoit Cousson (b-cousson@ti.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
20#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
21
22/* CM1 base address */
23#define DRA7XX_CM_CORE_AON_BASE		0x4a005000
24
25#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg)				\
26	OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
27
28/* CM_CORE_AON instances */
29#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST	0x0000
30#define DRA7XX_CM_CORE_AON_CKGEN_INST		0x0100
31#define DRA7XX_CM_CORE_AON_MPU_INST		0x0300
32#define DRA7XX_CM_CORE_AON_DSP1_INST		0x0400
33#define DRA7XX_CM_CORE_AON_IPU_INST		0x0500
34#define DRA7XX_CM_CORE_AON_DSP2_INST		0x0600
35#define DRA7XX_CM_CORE_AON_EVE1_INST		0x0640
36#define DRA7XX_CM_CORE_AON_EVE2_INST		0x0680
37#define DRA7XX_CM_CORE_AON_EVE3_INST		0x06c0
38#define DRA7XX_CM_CORE_AON_EVE4_INST		0x0700
39#define DRA7XX_CM_CORE_AON_RTC_INST		0x0740
40#define DRA7XX_CM_CORE_AON_VPE_INST		0x0760
41
42/* CM_CORE_AON clockdomain register offsets (from instance start) */
43#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS	0x0000
44#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS	0x0000
45#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS	0x0000
46#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS	0x0040
47#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS	0x0000
48#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS	0x0000
49#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS	0x0000
50#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS	0x0000
51#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS	0x0000
52#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS	0x0000
53#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS	0x0000
54
55#endif
56