1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * DRA7xx Clock domains framework 4 * 5 * Copyright (C) 2009-2013 Texas Instruments, Inc. 6 * Copyright (C) 2009-2011 Nokia Corporation 7 * 8 * Generated by code originally written by: 9 * Abhijit Pagare (abhijitpagare@ti.com) 10 * Benoit Cousson (b-cousson@ti.com) 11 * Paul Walmsley (paul@pwsan.com) 12 * 13 * This file is automatically generated from the OMAP hardware databases. 14 * We respectfully ask that any modifications to this file be coordinated 15 * with the public linux-omap@vger.kernel.org mailing list and the 16 * authors above to ensure that the autogeneration scripts are kept 17 * up-to-date with the file contents. 18 */ 19 20#include <linux/kernel.h> 21#include <linux/io.h> 22 23#include "clockdomain.h" 24#include "cm1_7xx.h" 25#include "cm2_7xx.h" 26 27#include "cm-regbits-7xx.h" 28#include "prm7xx.h" 29#include "prcm44xx.h" 30#include "prcm_mpu7xx.h" 31 32/* Static Dependencies for DRA7xx Clock Domains */ 33 34static struct clkdm_dep cam_wkup_sleep_deps[] = { 35 { .clkdm_name = "emif_clkdm" }, 36 { NULL }, 37}; 38 39static struct clkdm_dep dma_wkup_sleep_deps[] = { 40 { .clkdm_name = "dss_clkdm" }, 41 { .clkdm_name = "emif_clkdm" }, 42 { .clkdm_name = "ipu_clkdm" }, 43 { .clkdm_name = "ipu1_clkdm" }, 44 { .clkdm_name = "ipu2_clkdm" }, 45 { .clkdm_name = "iva_clkdm" }, 46 { .clkdm_name = "l3init_clkdm" }, 47 { .clkdm_name = "l4cfg_clkdm" }, 48 { .clkdm_name = "l4per_clkdm" }, 49 { .clkdm_name = "l4per2_clkdm" }, 50 { .clkdm_name = "l4per3_clkdm" }, 51 { .clkdm_name = "l4sec_clkdm" }, 52 { .clkdm_name = "pcie_clkdm" }, 53 { .clkdm_name = "wkupaon_clkdm" }, 54 { NULL }, 55}; 56 57static struct clkdm_dep dsp1_wkup_sleep_deps[] = { 58 { .clkdm_name = "atl_clkdm" }, 59 { .clkdm_name = "cam_clkdm" }, 60 { .clkdm_name = "dsp2_clkdm" }, 61 { .clkdm_name = "dss_clkdm" }, 62 { .clkdm_name = "emif_clkdm" }, 63 { .clkdm_name = "eve1_clkdm" }, 64 { .clkdm_name = "eve2_clkdm" }, 65 { .clkdm_name = "eve3_clkdm" }, 66 { .clkdm_name = "eve4_clkdm" }, 67 { .clkdm_name = "gmac_clkdm" }, 68 { .clkdm_name = "gpu_clkdm" }, 69 { .clkdm_name = "ipu_clkdm" }, 70 { .clkdm_name = "ipu1_clkdm" }, 71 { .clkdm_name = "ipu2_clkdm" }, 72 { .clkdm_name = "iva_clkdm" }, 73 { .clkdm_name = "l3init_clkdm" }, 74 { .clkdm_name = "l4per_clkdm" }, 75 { .clkdm_name = "l4per2_clkdm" }, 76 { .clkdm_name = "l4per3_clkdm" }, 77 { .clkdm_name = "l4sec_clkdm" }, 78 { .clkdm_name = "pcie_clkdm" }, 79 { .clkdm_name = "vpe_clkdm" }, 80 { .clkdm_name = "wkupaon_clkdm" }, 81 { NULL }, 82}; 83 84static struct clkdm_dep dsp2_wkup_sleep_deps[] = { 85 { .clkdm_name = "atl_clkdm" }, 86 { .clkdm_name = "cam_clkdm" }, 87 { .clkdm_name = "dsp1_clkdm" }, 88 { .clkdm_name = "dss_clkdm" }, 89 { .clkdm_name = "emif_clkdm" }, 90 { .clkdm_name = "eve1_clkdm" }, 91 { .clkdm_name = "eve2_clkdm" }, 92 { .clkdm_name = "eve3_clkdm" }, 93 { .clkdm_name = "eve4_clkdm" }, 94 { .clkdm_name = "gmac_clkdm" }, 95 { .clkdm_name = "gpu_clkdm" }, 96 { .clkdm_name = "ipu_clkdm" }, 97 { .clkdm_name = "ipu1_clkdm" }, 98 { .clkdm_name = "ipu2_clkdm" }, 99 { .clkdm_name = "iva_clkdm" }, 100 { .clkdm_name = "l3init_clkdm" }, 101 { .clkdm_name = "l4per_clkdm" }, 102 { .clkdm_name = "l4per2_clkdm" }, 103 { .clkdm_name = "l4per3_clkdm" }, 104 { .clkdm_name = "l4sec_clkdm" }, 105 { .clkdm_name = "pcie_clkdm" }, 106 { .clkdm_name = "vpe_clkdm" }, 107 { .clkdm_name = "wkupaon_clkdm" }, 108 { NULL }, 109}; 110 111static struct clkdm_dep dss_wkup_sleep_deps[] = { 112 { .clkdm_name = "emif_clkdm" }, 113 { .clkdm_name = "iva_clkdm" }, 114 { NULL }, 115}; 116 117static struct clkdm_dep eve1_wkup_sleep_deps[] = { 118 { .clkdm_name = "emif_clkdm" }, 119 { .clkdm_name = "eve2_clkdm" }, 120 { .clkdm_name = "eve3_clkdm" }, 121 { .clkdm_name = "eve4_clkdm" }, 122 { .clkdm_name = "iva_clkdm" }, 123 { NULL }, 124}; 125 126static struct clkdm_dep eve2_wkup_sleep_deps[] = { 127 { .clkdm_name = "emif_clkdm" }, 128 { .clkdm_name = "eve1_clkdm" }, 129 { .clkdm_name = "eve3_clkdm" }, 130 { .clkdm_name = "eve4_clkdm" }, 131 { .clkdm_name = "iva_clkdm" }, 132 { NULL }, 133}; 134 135static struct clkdm_dep eve3_wkup_sleep_deps[] = { 136 { .clkdm_name = "emif_clkdm" }, 137 { .clkdm_name = "eve1_clkdm" }, 138 { .clkdm_name = "eve2_clkdm" }, 139 { .clkdm_name = "eve4_clkdm" }, 140 { .clkdm_name = "iva_clkdm" }, 141 { NULL }, 142}; 143 144static struct clkdm_dep eve4_wkup_sleep_deps[] = { 145 { .clkdm_name = "emif_clkdm" }, 146 { .clkdm_name = "eve1_clkdm" }, 147 { .clkdm_name = "eve2_clkdm" }, 148 { .clkdm_name = "eve3_clkdm" }, 149 { .clkdm_name = "iva_clkdm" }, 150 { NULL }, 151}; 152 153static struct clkdm_dep gmac_wkup_sleep_deps[] = { 154 { .clkdm_name = "emif_clkdm" }, 155 { .clkdm_name = "l4per2_clkdm" }, 156 { NULL }, 157}; 158 159static struct clkdm_dep gpu_wkup_sleep_deps[] = { 160 { .clkdm_name = "emif_clkdm" }, 161 { .clkdm_name = "iva_clkdm" }, 162 { NULL }, 163}; 164 165static struct clkdm_dep ipu1_wkup_sleep_deps[] = { 166 { .clkdm_name = "atl_clkdm" }, 167 { .clkdm_name = "dsp1_clkdm" }, 168 { .clkdm_name = "dsp2_clkdm" }, 169 { .clkdm_name = "dss_clkdm" }, 170 { .clkdm_name = "emif_clkdm" }, 171 { .clkdm_name = "eve1_clkdm" }, 172 { .clkdm_name = "eve2_clkdm" }, 173 { .clkdm_name = "eve3_clkdm" }, 174 { .clkdm_name = "eve4_clkdm" }, 175 { .clkdm_name = "gmac_clkdm" }, 176 { .clkdm_name = "gpu_clkdm" }, 177 { .clkdm_name = "ipu_clkdm" }, 178 { .clkdm_name = "ipu2_clkdm" }, 179 { .clkdm_name = "iva_clkdm" }, 180 { .clkdm_name = "l3init_clkdm" }, 181 { .clkdm_name = "l3main1_clkdm" }, 182 { .clkdm_name = "l4cfg_clkdm" }, 183 { .clkdm_name = "l4per_clkdm" }, 184 { .clkdm_name = "l4per2_clkdm" }, 185 { .clkdm_name = "l4per3_clkdm" }, 186 { .clkdm_name = "l4sec_clkdm" }, 187 { .clkdm_name = "pcie_clkdm" }, 188 { .clkdm_name = "vpe_clkdm" }, 189 { .clkdm_name = "wkupaon_clkdm" }, 190 { NULL }, 191}; 192 193static struct clkdm_dep ipu2_wkup_sleep_deps[] = { 194 { .clkdm_name = "atl_clkdm" }, 195 { .clkdm_name = "dsp1_clkdm" }, 196 { .clkdm_name = "dsp2_clkdm" }, 197 { .clkdm_name = "dss_clkdm" }, 198 { .clkdm_name = "emif_clkdm" }, 199 { .clkdm_name = "eve1_clkdm" }, 200 { .clkdm_name = "eve2_clkdm" }, 201 { .clkdm_name = "eve3_clkdm" }, 202 { .clkdm_name = "eve4_clkdm" }, 203 { .clkdm_name = "gmac_clkdm" }, 204 { .clkdm_name = "gpu_clkdm" }, 205 { .clkdm_name = "ipu_clkdm" }, 206 { .clkdm_name = "ipu1_clkdm" }, 207 { .clkdm_name = "iva_clkdm" }, 208 { .clkdm_name = "l3init_clkdm" }, 209 { .clkdm_name = "l3main1_clkdm" }, 210 { .clkdm_name = "l4cfg_clkdm" }, 211 { .clkdm_name = "l4per_clkdm" }, 212 { .clkdm_name = "l4per2_clkdm" }, 213 { .clkdm_name = "l4per3_clkdm" }, 214 { .clkdm_name = "l4sec_clkdm" }, 215 { .clkdm_name = "pcie_clkdm" }, 216 { .clkdm_name = "vpe_clkdm" }, 217 { .clkdm_name = "wkupaon_clkdm" }, 218 { NULL }, 219}; 220 221static struct clkdm_dep iva_wkup_sleep_deps[] = { 222 { .clkdm_name = "emif_clkdm" }, 223 { NULL }, 224}; 225 226static struct clkdm_dep l3init_wkup_sleep_deps[] = { 227 { .clkdm_name = "emif_clkdm" }, 228 { .clkdm_name = "iva_clkdm" }, 229 { .clkdm_name = "l4cfg_clkdm" }, 230 { .clkdm_name = "l4per_clkdm" }, 231 { .clkdm_name = "l4per3_clkdm" }, 232 { .clkdm_name = "l4sec_clkdm" }, 233 { .clkdm_name = "wkupaon_clkdm" }, 234 { NULL }, 235}; 236 237static struct clkdm_dep l4per2_wkup_sleep_deps[] = { 238 { .clkdm_name = "dsp1_clkdm" }, 239 { .clkdm_name = "dsp2_clkdm" }, 240 { .clkdm_name = "ipu1_clkdm" }, 241 { .clkdm_name = "ipu2_clkdm" }, 242 { NULL }, 243}; 244 245static struct clkdm_dep l4sec_wkup_sleep_deps[] = { 246 { .clkdm_name = "emif_clkdm" }, 247 { .clkdm_name = "l4per_clkdm" }, 248 { NULL }, 249}; 250 251static struct clkdm_dep mpu_wkup_sleep_deps[] = { 252 { .clkdm_name = "cam_clkdm" }, 253 { .clkdm_name = "dsp1_clkdm" }, 254 { .clkdm_name = "dsp2_clkdm" }, 255 { .clkdm_name = "dss_clkdm" }, 256 { .clkdm_name = "emif_clkdm" }, 257 { .clkdm_name = "eve1_clkdm" }, 258 { .clkdm_name = "eve2_clkdm" }, 259 { .clkdm_name = "eve3_clkdm" }, 260 { .clkdm_name = "eve4_clkdm" }, 261 { .clkdm_name = "gmac_clkdm" }, 262 { .clkdm_name = "gpu_clkdm" }, 263 { .clkdm_name = "ipu_clkdm" }, 264 { .clkdm_name = "ipu1_clkdm" }, 265 { .clkdm_name = "ipu2_clkdm" }, 266 { .clkdm_name = "iva_clkdm" }, 267 { .clkdm_name = "l3init_clkdm" }, 268 { .clkdm_name = "l3main1_clkdm" }, 269 { .clkdm_name = "l4cfg_clkdm" }, 270 { .clkdm_name = "l4per_clkdm" }, 271 { .clkdm_name = "l4per2_clkdm" }, 272 { .clkdm_name = "l4per3_clkdm" }, 273 { .clkdm_name = "l4sec_clkdm" }, 274 { .clkdm_name = "pcie_clkdm" }, 275 { .clkdm_name = "vpe_clkdm" }, 276 { .clkdm_name = "wkupaon_clkdm" }, 277 { NULL }, 278}; 279 280static struct clkdm_dep pcie_wkup_sleep_deps[] = { 281 { .clkdm_name = "atl_clkdm" }, 282 { .clkdm_name = "cam_clkdm" }, 283 { .clkdm_name = "dsp1_clkdm" }, 284 { .clkdm_name = "dsp2_clkdm" }, 285 { .clkdm_name = "dss_clkdm" }, 286 { .clkdm_name = "emif_clkdm" }, 287 { .clkdm_name = "eve1_clkdm" }, 288 { .clkdm_name = "eve2_clkdm" }, 289 { .clkdm_name = "eve3_clkdm" }, 290 { .clkdm_name = "eve4_clkdm" }, 291 { .clkdm_name = "gmac_clkdm" }, 292 { .clkdm_name = "gpu_clkdm" }, 293 { .clkdm_name = "ipu_clkdm" }, 294 { .clkdm_name = "ipu1_clkdm" }, 295 { .clkdm_name = "iva_clkdm" }, 296 { .clkdm_name = "l3init_clkdm" }, 297 { .clkdm_name = "l4cfg_clkdm" }, 298 { .clkdm_name = "l4per_clkdm" }, 299 { .clkdm_name = "l4per2_clkdm" }, 300 { .clkdm_name = "l4per3_clkdm" }, 301 { .clkdm_name = "l4sec_clkdm" }, 302 { .clkdm_name = "vpe_clkdm" }, 303 { NULL }, 304}; 305 306static struct clkdm_dep vpe_wkup_sleep_deps[] = { 307 { .clkdm_name = "emif_clkdm" }, 308 { .clkdm_name = "l4per3_clkdm" }, 309 { NULL }, 310}; 311 312static struct clockdomain l4per3_7xx_clkdm = { 313 .name = "l4per3_clkdm", 314 .pwrdm = { .name = "l4per_pwrdm" }, 315 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 316 .cm_inst = DRA7XX_CM_CORE_L4PER_INST, 317 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS, 318 .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT, 319 .flags = CLKDM_CAN_HWSUP_SWSUP, 320}; 321 322static struct clockdomain l4per2_7xx_clkdm = { 323 .name = "l4per2_clkdm", 324 .pwrdm = { .name = "l4per_pwrdm" }, 325 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 326 .cm_inst = DRA7XX_CM_CORE_L4PER_INST, 327 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS, 328 .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT, 329 .wkdep_srcs = l4per2_wkup_sleep_deps, 330 .sleepdep_srcs = l4per2_wkup_sleep_deps, 331 .flags = CLKDM_CAN_SWSUP, 332}; 333 334static struct clockdomain mpu0_7xx_clkdm = { 335 .name = "mpu0_clkdm", 336 .pwrdm = { .name = "cpu0_pwrdm" }, 337 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 338 .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST, 339 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS, 340 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 341}; 342 343static struct clockdomain iva_7xx_clkdm = { 344 .name = "iva_clkdm", 345 .pwrdm = { .name = "iva_pwrdm" }, 346 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 347 .cm_inst = DRA7XX_CM_CORE_IVA_INST, 348 .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS, 349 .dep_bit = DRA7XX_IVA_STATDEP_SHIFT, 350 .wkdep_srcs = iva_wkup_sleep_deps, 351 .sleepdep_srcs = iva_wkup_sleep_deps, 352 .flags = CLKDM_CAN_HWSUP_SWSUP, 353}; 354 355static struct clockdomain coreaon_7xx_clkdm = { 356 .name = "coreaon_clkdm", 357 .pwrdm = { .name = "coreaon_pwrdm" }, 358 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 359 .cm_inst = DRA7XX_CM_CORE_COREAON_INST, 360 .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS, 361 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 362}; 363 364static struct clockdomain ipu1_7xx_clkdm = { 365 .name = "ipu1_clkdm", 366 .pwrdm = { .name = "ipu_pwrdm" }, 367 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 368 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST, 369 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS, 370 .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT, 371 .wkdep_srcs = ipu1_wkup_sleep_deps, 372 .sleepdep_srcs = ipu1_wkup_sleep_deps, 373 .flags = CLKDM_CAN_HWSUP_SWSUP, 374}; 375 376static struct clockdomain ipu2_7xx_clkdm = { 377 .name = "ipu2_clkdm", 378 .pwrdm = { .name = "core_pwrdm" }, 379 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 380 .cm_inst = DRA7XX_CM_CORE_CORE_INST, 381 .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS, 382 .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT, 383 .wkdep_srcs = ipu2_wkup_sleep_deps, 384 .sleepdep_srcs = ipu2_wkup_sleep_deps, 385 .flags = CLKDM_CAN_HWSUP_SWSUP, 386}; 387 388static struct clockdomain l3init_7xx_clkdm = { 389 .name = "l3init_clkdm", 390 .pwrdm = { .name = "l3init_pwrdm" }, 391 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 392 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST, 393 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS, 394 .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT, 395 .wkdep_srcs = l3init_wkup_sleep_deps, 396 .sleepdep_srcs = l3init_wkup_sleep_deps, 397 .flags = CLKDM_CAN_HWSUP_SWSUP, 398}; 399 400static struct clockdomain l4sec_7xx_clkdm = { 401 .name = "l4sec_clkdm", 402 .pwrdm = { .name = "l4per_pwrdm" }, 403 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 404 .cm_inst = DRA7XX_CM_CORE_L4PER_INST, 405 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS, 406 .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT, 407 .wkdep_srcs = l4sec_wkup_sleep_deps, 408 .sleepdep_srcs = l4sec_wkup_sleep_deps, 409 .flags = CLKDM_CAN_SWSUP, 410}; 411 412static struct clockdomain l3main1_7xx_clkdm = { 413 .name = "l3main1_clkdm", 414 .pwrdm = { .name = "core_pwrdm" }, 415 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 416 .cm_inst = DRA7XX_CM_CORE_CORE_INST, 417 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS, 418 .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT, 419 .flags = CLKDM_CAN_HWSUP, 420}; 421 422static struct clockdomain vpe_7xx_clkdm = { 423 .name = "vpe_clkdm", 424 .pwrdm = { .name = "vpe_pwrdm" }, 425 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 426 .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST, 427 .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS, 428 .dep_bit = DRA7XX_VPE_STATDEP_SHIFT, 429 .wkdep_srcs = vpe_wkup_sleep_deps, 430 .sleepdep_srcs = vpe_wkup_sleep_deps, 431 .flags = CLKDM_CAN_HWSUP_SWSUP, 432}; 433 434static struct clockdomain mpu_7xx_clkdm = { 435 .name = "mpu_clkdm", 436 .pwrdm = { .name = "mpu_pwrdm" }, 437 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 438 .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST, 439 .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS, 440 .wkdep_srcs = mpu_wkup_sleep_deps, 441 .sleepdep_srcs = mpu_wkup_sleep_deps, 442 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 443}; 444 445static struct clockdomain custefuse_7xx_clkdm = { 446 .name = "custefuse_clkdm", 447 .pwrdm = { .name = "custefuse_pwrdm" }, 448 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 449 .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST, 450 .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS, 451 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 452}; 453 454static struct clockdomain ipu_7xx_clkdm = { 455 .name = "ipu_clkdm", 456 .pwrdm = { .name = "ipu_pwrdm" }, 457 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 458 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST, 459 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS, 460 .dep_bit = DRA7XX_IPU_STATDEP_SHIFT, 461 .flags = CLKDM_CAN_SWSUP, 462}; 463 464static struct clockdomain mpu1_7xx_clkdm = { 465 .name = "mpu1_clkdm", 466 .pwrdm = { .name = "cpu1_pwrdm" }, 467 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, 468 .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST, 469 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS, 470 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 471}; 472 473static struct clockdomain gmac_7xx_clkdm = { 474 .name = "gmac_clkdm", 475 .pwrdm = { .name = "l3init_pwrdm" }, 476 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 477 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST, 478 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS, 479 .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT, 480 .wkdep_srcs = gmac_wkup_sleep_deps, 481 .sleepdep_srcs = gmac_wkup_sleep_deps, 482 .flags = CLKDM_CAN_HWSUP_SWSUP, 483}; 484 485static struct clockdomain l4cfg_7xx_clkdm = { 486 .name = "l4cfg_clkdm", 487 .pwrdm = { .name = "core_pwrdm" }, 488 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 489 .cm_inst = DRA7XX_CM_CORE_CORE_INST, 490 .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS, 491 .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT, 492 .flags = CLKDM_CAN_HWSUP, 493}; 494 495static struct clockdomain dma_7xx_clkdm = { 496 .name = "dma_clkdm", 497 .pwrdm = { .name = "core_pwrdm" }, 498 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 499 .cm_inst = DRA7XX_CM_CORE_CORE_INST, 500 .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS, 501 .wkdep_srcs = dma_wkup_sleep_deps, 502 .sleepdep_srcs = dma_wkup_sleep_deps, 503 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 504}; 505 506static struct clockdomain rtc_7xx_clkdm = { 507 .name = "rtc_clkdm", 508 .pwrdm = { .name = "rtc_pwrdm" }, 509 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 510 .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST, 511 .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS, 512 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 513}; 514 515static struct clockdomain pcie_7xx_clkdm = { 516 .name = "pcie_clkdm", 517 .pwrdm = { .name = "l3init_pwrdm" }, 518 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 519 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST, 520 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS, 521 .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT, 522 .wkdep_srcs = pcie_wkup_sleep_deps, 523 .sleepdep_srcs = pcie_wkup_sleep_deps, 524 .flags = CLKDM_CAN_SWSUP, 525}; 526 527static struct clockdomain atl_7xx_clkdm = { 528 .name = "atl_clkdm", 529 .pwrdm = { .name = "core_pwrdm" }, 530 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 531 .cm_inst = DRA7XX_CM_CORE_CORE_INST, 532 .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS, 533 .dep_bit = DRA7XX_ATL_STATDEP_SHIFT, 534 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 535}; 536 537static struct clockdomain l3instr_7xx_clkdm = { 538 .name = "l3instr_clkdm", 539 .pwrdm = { .name = "core_pwrdm" }, 540 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 541 .cm_inst = DRA7XX_CM_CORE_CORE_INST, 542 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS, 543}; 544 545static struct clockdomain dss_7xx_clkdm = { 546 .name = "dss_clkdm", 547 .pwrdm = { .name = "dss_pwrdm" }, 548 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 549 .cm_inst = DRA7XX_CM_CORE_DSS_INST, 550 .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS, 551 .dep_bit = DRA7XX_DSS_STATDEP_SHIFT, 552 .wkdep_srcs = dss_wkup_sleep_deps, 553 .sleepdep_srcs = dss_wkup_sleep_deps, 554 .flags = CLKDM_CAN_HWSUP_SWSUP, 555}; 556 557static struct clockdomain emif_7xx_clkdm = { 558 .name = "emif_clkdm", 559 .pwrdm = { .name = "core_pwrdm" }, 560 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 561 .cm_inst = DRA7XX_CM_CORE_CORE_INST, 562 .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS, 563 .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT, 564 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 565}; 566 567static struct clockdomain emu_7xx_clkdm = { 568 .name = "emu_clkdm", 569 .pwrdm = { .name = "emu_pwrdm" }, 570 .prcm_partition = DRA7XX_PRM_PARTITION, 571 .cm_inst = DRA7XX_PRM_EMU_CM_INST, 572 .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS, 573 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 574}; 575 576static struct clockdomain dsp2_7xx_clkdm = { 577 .name = "dsp2_clkdm", 578 .pwrdm = { .name = "dsp2_pwrdm" }, 579 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 580 .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST, 581 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS, 582 .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT, 583 .wkdep_srcs = dsp2_wkup_sleep_deps, 584 .sleepdep_srcs = dsp2_wkup_sleep_deps, 585 .flags = CLKDM_CAN_HWSUP_SWSUP, 586}; 587 588static struct clockdomain dsp1_7xx_clkdm = { 589 .name = "dsp1_clkdm", 590 .pwrdm = { .name = "dsp1_pwrdm" }, 591 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 592 .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST, 593 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS, 594 .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT, 595 .wkdep_srcs = dsp1_wkup_sleep_deps, 596 .sleepdep_srcs = dsp1_wkup_sleep_deps, 597 .flags = CLKDM_CAN_HWSUP_SWSUP, 598}; 599 600static struct clockdomain cam_7xx_clkdm = { 601 .name = "cam_clkdm", 602 .pwrdm = { .name = "cam_pwrdm" }, 603 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 604 .cm_inst = DRA7XX_CM_CORE_CAM_INST, 605 .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS, 606 .dep_bit = DRA7XX_CAM_STATDEP_SHIFT, 607 .wkdep_srcs = cam_wkup_sleep_deps, 608 .sleepdep_srcs = cam_wkup_sleep_deps, 609 .flags = CLKDM_CAN_SWSUP, 610}; 611 612static struct clockdomain l4per_7xx_clkdm = { 613 .name = "l4per_clkdm", 614 .pwrdm = { .name = "l4per_pwrdm" }, 615 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 616 .cm_inst = DRA7XX_CM_CORE_L4PER_INST, 617 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS, 618 .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT, 619 .flags = CLKDM_CAN_HWSUP_SWSUP, 620}; 621 622static struct clockdomain gpu_7xx_clkdm = { 623 .name = "gpu_clkdm", 624 .pwrdm = { .name = "gpu_pwrdm" }, 625 .prcm_partition = DRA7XX_CM_CORE_PARTITION, 626 .cm_inst = DRA7XX_CM_CORE_GPU_INST, 627 .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS, 628 .dep_bit = DRA7XX_GPU_STATDEP_SHIFT, 629 .wkdep_srcs = gpu_wkup_sleep_deps, 630 .sleepdep_srcs = gpu_wkup_sleep_deps, 631 .flags = CLKDM_CAN_HWSUP_SWSUP, 632}; 633 634static struct clockdomain eve4_7xx_clkdm = { 635 .name = "eve4_clkdm", 636 .pwrdm = { .name = "eve4_pwrdm" }, 637 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 638 .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST, 639 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS, 640 .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT, 641 .wkdep_srcs = eve4_wkup_sleep_deps, 642 .sleepdep_srcs = eve4_wkup_sleep_deps, 643 .flags = CLKDM_CAN_HWSUP_SWSUP, 644}; 645 646static struct clockdomain eve2_7xx_clkdm = { 647 .name = "eve2_clkdm", 648 .pwrdm = { .name = "eve2_pwrdm" }, 649 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 650 .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST, 651 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS, 652 .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT, 653 .wkdep_srcs = eve2_wkup_sleep_deps, 654 .sleepdep_srcs = eve2_wkup_sleep_deps, 655 .flags = CLKDM_CAN_HWSUP_SWSUP, 656}; 657 658static struct clockdomain eve3_7xx_clkdm = { 659 .name = "eve3_clkdm", 660 .pwrdm = { .name = "eve3_pwrdm" }, 661 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 662 .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST, 663 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS, 664 .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT, 665 .wkdep_srcs = eve3_wkup_sleep_deps, 666 .sleepdep_srcs = eve3_wkup_sleep_deps, 667 .flags = CLKDM_CAN_HWSUP_SWSUP, 668}; 669 670static struct clockdomain wkupaon_7xx_clkdm = { 671 .name = "wkupaon_clkdm", 672 .pwrdm = { .name = "wkupaon_pwrdm" }, 673 .prcm_partition = DRA7XX_PRM_PARTITION, 674 .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST, 675 .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS, 676 .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT, 677 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 678}; 679 680static struct clockdomain eve1_7xx_clkdm = { 681 .name = "eve1_clkdm", 682 .pwrdm = { .name = "eve1_pwrdm" }, 683 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, 684 .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST, 685 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS, 686 .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT, 687 .wkdep_srcs = eve1_wkup_sleep_deps, 688 .sleepdep_srcs = eve1_wkup_sleep_deps, 689 .flags = CLKDM_CAN_HWSUP_SWSUP, 690}; 691 692/* As clockdomains are added or removed above, this list must also be changed */ 693static struct clockdomain *clockdomains_dra7xx[] __initdata = { 694 &l4per3_7xx_clkdm, 695 &l4per2_7xx_clkdm, 696 &mpu0_7xx_clkdm, 697 &iva_7xx_clkdm, 698 &coreaon_7xx_clkdm, 699 &ipu1_7xx_clkdm, 700 &ipu2_7xx_clkdm, 701 &l3init_7xx_clkdm, 702 &l4sec_7xx_clkdm, 703 &l3main1_7xx_clkdm, 704 &vpe_7xx_clkdm, 705 &mpu_7xx_clkdm, 706 &custefuse_7xx_clkdm, 707 &ipu_7xx_clkdm, 708 &mpu1_7xx_clkdm, 709 &gmac_7xx_clkdm, 710 &l4cfg_7xx_clkdm, 711 &dma_7xx_clkdm, 712 &rtc_7xx_clkdm, 713 &pcie_7xx_clkdm, 714 &atl_7xx_clkdm, 715 &l3instr_7xx_clkdm, 716 &dss_7xx_clkdm, 717 &emif_7xx_clkdm, 718 &emu_7xx_clkdm, 719 &dsp2_7xx_clkdm, 720 &dsp1_7xx_clkdm, 721 &cam_7xx_clkdm, 722 &l4per_7xx_clkdm, 723 &gpu_7xx_clkdm, 724 &eve4_7xx_clkdm, 725 &eve2_7xx_clkdm, 726 &eve3_7xx_clkdm, 727 &wkupaon_7xx_clkdm, 728 &eve1_7xx_clkdm, 729 NULL 730}; 731 732void __init dra7xx_clockdomains_init(void) 733{ 734 clkdm_register_platform_funcs(&omap4_clkdm_operations); 735 clkdm_register_clkdms(clockdomains_dra7xx); 736 clkdm_complete_init(); 737} 738