1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2014 Marvell
4 *
5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
6 * Gregory Clement <gregory.clement@free-electrons.com>
7 */
8
9#include <linux/linkage.h>
10#include <asm/assembler.h>
11
12
13ENTRY(armada_38x_scu_power_up)
14	mrc     p15, 4, r1, c15, c0	@ get SCU base address
15	orr	r1, r1, #0x8		@ SCU CPU Power Status Register
16	mrc	p15, 0, r0, cr0, cr0, 5	@ get the CPU ID
17	and	r0, r0, #15
18	add	r1, r1, r0
19	mov	r0, #0x0
20	strb	r0, [r1]		@ switch SCU power state to Normal mode
21	ret	lr
22ENDPROC(armada_38x_scu_power_up)
23
24/*
25 * This is the entry point through which CPUs exiting cpuidle deep
26 * idle state are going.
27 */
28ENTRY(armada_370_xp_cpu_resume)
29ARM_BE8(setend	be )			@ go BE8 if entered LE
30	/*
31	 * Disable the MMU that might have been enabled in BootROM if
32	 * this code is used in the resume path of a suspend/resume
33	 * cycle.
34	 */
35	mrc	p15, 0, r1, c1, c0, 0
36	bic	r1, #1
37	mcr	p15, 0, r1, c1, c0, 0
38	bl	ll_add_cpu_to_smp_group
39	bl	ll_enable_coherency
40	b	cpu_resume
41ENDPROC(armada_370_xp_cpu_resume)
42
43ENTRY(armada_38x_cpu_resume)
44	/* do we need it for Armada 38x*/
45ARM_BE8(setend	be )			@ go BE8 if entered LE
46	bl	v7_invalidate_l1
47	bl	armada_38x_scu_power_up
48	b	cpu_resume
49ENDPROC(armada_38x_cpu_resume)
50
51.global mvebu_boot_wa_start
52.global mvebu_boot_wa_end
53
54/* The following code will be executed from SRAM */
55ENTRY(mvebu_boot_wa_start)
56ARM_BE8(setend	be)
57	adr	r0, 1f
58	ldr	r0, [r0]		@ load the address of the
59					@ resume register
60	ldr	r0, [r0]		@ load the value in the
61					@ resume register
62ARM_BE8(rev	r0, r0)			@ the value is stored LE
63	mov	pc, r0			@ jump to this value
64/*
65 * the last word of this piece of code will be filled by the physical
66 * address of the boot address register just after being copied in SRAM
67 */
681:
69	.long   .
70mvebu_boot_wa_end:
71ENDPROC(mvebu_boot_wa_end)
72