1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * AURORA shared L2 cache controller support 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Yehuda Yitschak <yehuday@marvell.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 */ 10 11#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H 12#define __ASM_ARM_HARDWARE_AURORA_L2_H 13 14#define AURORA_SYNC_REG 0x700 15#define AURORA_RANGE_BASE_ADDR_REG 0x720 16#define AURORA_FLUSH_PHY_ADDR_REG 0x7f0 17#define AURORA_INVAL_RANGE_REG 0x774 18#define AURORA_CLEAN_RANGE_REG 0x7b4 19#define AURORA_FLUSH_RANGE_REG 0x7f4 20 21#define AURORA_ACR_REPLACEMENT_OFFSET 27 22#define AURORA_ACR_REPLACEMENT_MASK \ 23 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET) 24#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR \ 25 (0 << AURORA_ACR_REPLACEMENT_OFFSET) 26#define AURORA_ACR_REPLACEMENT_TYPE_LFSR \ 27 (1 << AURORA_ACR_REPLACEMENT_OFFSET) 28#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \ 29 (3 << AURORA_ACR_REPLACEMENT_OFFSET) 30 31#define AURORA_ACR_PARITY_EN (1 << 21) 32#define AURORA_ACR_ECC_EN (1 << 20) 33 34#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0 35#define AURORA_ACR_FORCE_WRITE_POLICY_MASK \ 36 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 37#define AURORA_ACR_FORCE_WRITE_POLICY_DIS \ 38 (0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 39#define AURORA_ACR_FORCE_WRITE_BACK_POLICY \ 40 (1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 41#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \ 42 (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 43 44#define AURORA_ERR_CNT_REG 0x600 45#define AURORA_ERR_ATTR_CAP_REG 0x608 46#define AURORA_ERR_ADDR_CAP_REG 0x60c 47#define AURORA_ERR_WAY_CAP_REG 0x610 48#define AURORA_ERR_INJECT_CTL_REG 0x614 49#define AURORA_ERR_INJECT_MASK_REG 0x618 50 51#define AURORA_ERR_CNT_CLR_OFFSET 31 52#define AURORA_ERR_CNT_CLR \ 53 (0x1 << AURORA_ERR_CNT_CLR_OFFSET) 54#define AURORA_ERR_CNT_UE_OFFSET 16 55#define AURORA_ERR_CNT_UE_MASK \ 56 (0x7fff << AURORA_ERR_CNT_UE_OFFSET) 57#define AURORA_ERR_CNT_CE_OFFSET 0 58#define AURORA_ERR_CNT_CE_MASK \ 59 (0xffff << AURORA_ERR_CNT_CE_OFFSET) 60 61#define AURORA_ERR_ATTR_SRC_OFF 16 62#define AURORA_ERR_ATTR_SRC_MSK \ 63 (0x7 << AURORA_ERR_ATTR_SRC_OFF) 64#define AURORA_ERR_ATTR_TXN_OFF 12 65#define AURORA_ERR_ATTR_TXN_MSK \ 66 (0xf << AURORA_ERR_ATTR_TXN_OFF) 67#define AURORA_ERR_ATTR_ERR_OFF 8 68#define AURORA_ERR_ATTR_ERR_MSK \ 69 (0x3 << AURORA_ERR_ATTR_ERR_OFF) 70#define AURORA_ERR_ATTR_CAP_VALID_OFF 0 71#define AURORA_ERR_ATTR_CAP_VALID \ 72 (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF) 73 74#define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0 75 76#define AURORA_ERR_WAY_IDX_OFF 8 77#define AURORA_ERR_WAY_IDX_MSK \ 78 (0xfff << AURORA_ERR_WAY_IDX_OFF) 79#define AURORA_ERR_WAY_CAP_WAY_OFFSET 1 80#define AURORA_ERR_WAY_CAP_WAY_MASK \ 81 (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET) 82 83#define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0 84#define AURORA_ERR_ATTR_TXN_OFF 12 85#define AURORA_ERR_INJECT_CTL_EN_MASK 0x3 86#define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2 87#define AURORA_ERR_INJECT_CTL_EN_ECC 0x1 88 89#define AURORA_MAX_RANGE_SIZE 1024 90 91#define AURORA_WAY_SIZE_SHIFT 2 92 93#define AURORA_CTRL_FW 0x100 94 95/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make 96 * the distinction between a number coming from hardware and a number 97 * coming from the device tree */ 98#define AURORA_CACHE_ID 0x100 99 100#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */ 101