1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Samsung Exynos DTS pinctrl constants 4 * 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * Copyright (c) 2022 Linaro Ltd 8 * Author: Krzysztof Kozlowski <krzk@kernel.org> 9 */ 10 11#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ 12#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ 13 14#define EXYNOS_PIN_PULL_NONE 0 15#define EXYNOS_PIN_PULL_DOWN 1 16#define EXYNOS_PIN_PULL_UP 3 17 18/* Pin function in power down mode */ 19#define EXYNOS_PIN_PDN_OUT0 0 20#define EXYNOS_PIN_PDN_OUT1 1 21#define EXYNOS_PIN_PDN_INPUT 2 22#define EXYNOS_PIN_PDN_PREV 3 23 24/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ 25#define EXYNOS4_PIN_DRV_LV1 0 26#define EXYNOS4_PIN_DRV_LV2 2 27#define EXYNOS4_PIN_DRV_LV3 1 28#define EXYNOS4_PIN_DRV_LV4 3 29 30/* Drive strengths for Exynos5260 */ 31#define EXYNOS5260_PIN_DRV_LV1 0 32#define EXYNOS5260_PIN_DRV_LV2 1 33#define EXYNOS5260_PIN_DRV_LV4 2 34#define EXYNOS5260_PIN_DRV_LV6 3 35 36/* 37 * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except 38 * GPIO_HSI block) 39 */ 40#define EXYNOS5420_PIN_DRV_LV1 0 41#define EXYNOS5420_PIN_DRV_LV2 1 42#define EXYNOS5420_PIN_DRV_LV3 2 43#define EXYNOS5420_PIN_DRV_LV4 3 44 45#define EXYNOS_PIN_FUNC_INPUT 0 46#define EXYNOS_PIN_FUNC_OUTPUT 1 47#define EXYNOS_PIN_FUNC_2 2 48#define EXYNOS_PIN_FUNC_3 3 49#define EXYNOS_PIN_FUNC_4 4 50#define EXYNOS_PIN_FUNC_5 5 51#define EXYNOS_PIN_FUNC_6 6 52#define EXYNOS_PIN_FUNC_EINT 0xf 53#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT 54 55#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */ 56