1/*
2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
3 */
4
5/dts-v1/;
6
7#include "gemini.dtsi"
8#include <dt-bindings/input/input.h>
9
10/ {
11	model = "D-Link DIR-685 Xtreme N Storage Router";
12	compatible = "dlink,dir-685", "cortina,gemini";
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	memory@0 {
17		/* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
18		device_type = "memory";
19		reg = <0x00000000 0x8000000>;
20	};
21
22	chosen {
23		bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300";
24		stdout-path = "uart0:19200n8";
25	};
26
27	gpio_keys {
28		compatible = "gpio-keys";
29
30		button-reset {
31			debounce-interval = <100>;
32			wakeup-source;
33			linux,code = <KEY_RESTART>;
34			label = "reset";
35			/* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
36			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
37		};
38		button-eject {
39			debounce-interval = <100>;
40			wakeup-source;
41			linux,code = <KEY_EJECTCD>;
42			label = "unmount";
43			/* Collides with LPC LFRAME, UART RTS, SSP TXD */
44			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
45		};
46	};
47
48	vdisp: regulator {
49		compatible = "regulator-fixed";
50		regulator-name = "display-power";
51		regulator-min-microvolt = <3600000>;
52		regulator-max-microvolt = <3600000>;
53		/* Collides with LCD E */
54		gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
55		enable-active-high;
56	};
57
58	spi {
59		compatible = "spi-gpio";
60		#address-cells = <1>;
61		#size-cells = <0>;
62
63		/* Collides with IDE pins, that's cool (we do not use them) */
64		sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
65		miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
66		mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
67		cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
68		num-chipselects = <1>;
69
70		panel: display@0 {
71			compatible = "dlink,dir-685-panel", "ilitek,ili9322";
72			reg = <0>;
73			/* 50 ns min period = 20 MHz */
74			spi-max-frequency = <20000000>;
75			vcc-supply = <&vdisp>;
76			iovcc-supply = <&vdisp>;
77			vci-supply = <&vdisp>;
78
79			port {
80				panel_in: endpoint {
81					remote-endpoint = <&display_out>;
82				};
83			};
84		};
85	};
86
87	leds {
88		compatible = "gpio-leds";
89		led-wps {
90			label = "dir685:blue:WPS";
91			/* Collides with ICE */
92			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
93			default-state = "on";
94			linux,default-trigger = "heartbeat";
95		};
96		/*
97		 * These two LEDs are on the side of the device.
98		 * For electrical reasons, both LEDs cannot be active
99		 * at the same time so only blue or orange can be on at
100		 * one time. Enabling both makes the LED go dark.
101		 * The LEDs both sit inside the unmount button and the
102		 * label on the case says "unmount".
103		 */
104		led-blue-hd {
105			label = "dir685:blue:HD";
106			/* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */
107			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
108			default-state = "off";
109			linux,default-trigger = "disk-read";
110		};
111		led-orange-hd {
112			label = "dir685:orange:HD";
113			/* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */
114			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
115			default-state = "off";
116			linux,default-trigger = "disk-write";
117		};
118	};
119
120	/*
121	 * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
122	 * sensor. It is turned on when the temperature exceeds 46 degrees
123	 * and turned off when the temperatures goes below 41 degrees
124	 * (celsius).
125	 */
126	fan0: gpio-fan {
127		compatible = "gpio-fan";
128		/* Collides with IDE */
129		gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
130		gpio-fan,speed-map = <0 0>, <10000 1>;
131		#cooling-cells = <2>;
132	};
133
134	thermal-zones {
135		chassis-thermal {
136			/* Poll every 20 seconds */
137			polling-delay = <20000>;
138			/* Poll every 2nd second when cooling */
139			polling-delay-passive = <2000>;
140			/*  Use the thermal sensor in the hard drive */
141			thermal-sensors = <&drive0>;
142
143			/* Tripping points from the fan.script in the rootfs */
144			trips {
145				alert: chassis-alert {
146					/* At 43 degrees turn on the fan */
147					temperature = <43000>;
148					hysteresis = <3000>;
149					type = "active";
150				};
151				crit: chassis-crit {
152					/* Just shut down at 60 degrees */
153					temperature = <60000>;
154					hysteresis = <2000>;
155					type = "critical";
156				};
157			};
158
159			cooling-maps {
160				map0 {
161					trip = <&alert>;
162					cooling-device = <&fan0 1 1>;
163				};
164			};
165		};
166	};
167
168	/*
169	 * The touchpad input is connected to a GPIO bit-banged
170	 * I2C bus.
171	 */
172	i2c {
173		compatible = "i2c-gpio";
174		/* Collides with ICE */
175		sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
176		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
177		#address-cells = <1>;
178		#size-cells = <0>;
179
180		touchkeys@26 {
181			compatible = "dlink,dir685-touchkeys";
182			reg = <0x26>;
183			interrupt-parent = <&gpio0>;
184			/* Collides with NAND flash */
185			interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
186		};
187	};
188
189	/* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */
190	ethernet-switch {
191		compatible = "realtek,rtl8366rb";
192		/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
193		mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
194		mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
195		reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
196		realtek,disable-leds;
197
198		switch_intc: interrupt-controller {
199			/* GPIO 15 provides the interrupt */
200			interrupt-parent = <&gpio0>;
201			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
202			interrupt-controller;
203			#address-cells = <0>;
204			#interrupt-cells = <1>;
205		};
206
207		ethernet-ports {
208			#address-cells = <1>;
209			#size-cells = <0>;
210
211			ethernet-port@0 {
212				reg = <0>;
213				label = "lan0";
214				phy-handle = <&phy0>;
215			};
216			ethernet-port@1 {
217				reg = <1>;
218				label = "lan1";
219				phy-handle = <&phy1>;
220			};
221			ethernet-port@2 {
222				reg = <2>;
223				label = "lan2";
224				phy-handle = <&phy2>;
225			};
226			ethernet-port@3 {
227				reg = <3>;
228				label = "lan3";
229				phy-handle = <&phy3>;
230			};
231			ethernet-port@4 {
232				reg = <4>;
233				label = "wan";
234				phy-handle = <&phy4>;
235			};
236			rtl8366rb_cpu_port: ethernet-port@5 {
237				reg = <5>;
238				label = "cpu";
239				ethernet = <&gmac0>;
240				phy-mode = "rgmii";
241				fixed-link {
242					speed = <1000>;
243					full-duplex;
244					pause;
245				};
246			};
247
248		};
249
250		mdio {
251			compatible = "realtek,smi-mdio";
252			#address-cells = <1>;
253			#size-cells = <0>;
254
255			phy0: ethernet-phy@0 {
256				reg = <0>;
257				interrupt-parent = <&switch_intc>;
258				interrupts = <0>;
259			};
260			phy1: ethernet-phy@1 {
261				reg = <1>;
262				interrupt-parent = <&switch_intc>;
263				interrupts = <1>;
264			};
265			phy2: ethernet-phy@2 {
266				reg = <2>;
267				interrupt-parent = <&switch_intc>;
268				interrupts = <2>;
269			};
270			phy3: ethernet-phy@3 {
271				reg = <3>;
272				interrupt-parent = <&switch_intc>;
273				interrupts = <3>;
274			};
275			phy4: ethernet-phy@4 {
276				reg = <4>;
277				interrupt-parent = <&switch_intc>;
278				interrupts = <12>;
279			};
280		};
281	};
282
283	soc {
284		flash@30000000 {
285			/*
286			 * Flash access collides with the Chip Enable signal for
287			 * the display panel, that reuse the parallel flash Chip
288			 * Select 1 (CS1). We switch the pin control state so we
289			 * enable these pins for flash access only when we need
290			 * then, and when disabled they can be used for GPIO which
291			 * is what the display panel needs.
292			 */
293			status = "okay";
294			pinctrl-names = "enabled", "disabled";
295			pinctrl-0 = <&pflash_default_pins>;
296			pinctrl-1 = <&pflash_disabled_pins>;
297
298			/* 32MB of flash */
299			reg = <0x30000000 0x02000000>;
300
301			partitions {
302				compatible = "fixed-partitions";
303				#address-cells = <1>;
304				#size-cells = <1>;
305
306				/*
307				 * This "RedBoot" is the Storlink derivative.
308				 */
309				partition@0 {
310					label = "RedBoot";
311					reg = <0x00000000 0x00040000>;
312					read-only;
313				};
314				/*
315				 * This firmware image contains the kernel catenated
316				 * with the squashfs root filesystem. For some reason
317				 * this is called "upgrade" on the vendor system.
318				 */
319				partition@40000 {
320					label = "upgrade";
321					reg = <0x00040000 0x01f40000>;
322					read-only;
323				};
324				/* RGDB, Residental Gateway Database? */
325				partition@1f80000 {
326					label = "rgdb";
327					reg = <0x01f80000 0x00040000>;
328					read-only;
329				};
330				/*
331				 * This partition contains MAC addresses for WAN,
332				 * WLAN and LAN, and the country code (for wireless
333				 * I guess).
334				 */
335				partition@1fc0000 {
336					label = "nvram";
337					reg = <0x01fc0000 0x00020000>;
338					read-only;
339				};
340				partition@1fe0000 {
341					label = "LangPack";
342					reg = <0x01fe0000 0x00020000>;
343					read-only;
344				};
345			};
346		};
347
348		syscon: syscon@40000000 {
349			pinctrl {
350				/*
351				 * gpio0bgrp cover line 5, 6 used by TK I2C
352				 * gpio0bgrp cover line 7 used by WPS LED
353				 * gpio0cgrp cover line 8, 13 used by keys
354				 *           and 11, 12 used by the HD LEDs
355				 *           and line 14, 15 used by RTL8366
356				 *           RESET and phy ready
357				 * gpio0egrp cover line 16 used by VDISP
358				 * gpio0fgrp cover line 17 used by TK IRQ
359				 * gpio0ggrp cover line 20 used by panel CS
360				 * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO
361				 */
362				gpio0_default_pins: pinctrl-gpio0 {
363					mux {
364						function = "gpio0";
365						groups = "gpio0bgrp",
366						"gpio0cgrp",
367						"gpio0egrp",
368						"gpio0fgrp",
369						"gpio0hgrp";
370					};
371				};
372				/*
373				 * gpio1bgrp cover line 5,8,7 used by panel SPI
374				 * also line 6 used by the fan
375				 *
376				 */
377				gpio1_default_pins: pinctrl-gpio1 {
378					mux {
379						function = "gpio1";
380						groups = "gpio1bgrp";
381					};
382				};
383				/*
384				 * These GPIO groups will be mapped in over some
385				 * of the flash pins when the flash is not in
386				 * active use.
387				 */
388				pflash_disabled_pins: pinctrl-pflash-disabled {
389					mux {
390						function = "gpio0";
391						groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
392							 "gpio0kgrp";
393					};
394				};
395				pinctrl-gmii {
396					mux {
397						function = "gmii";
398						groups = "gmii_gmac0_grp";
399					};
400					conf0 {
401						pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV",
402						     "Y7 GMAC0 RXC", "Y11 GMAC1 RXC",
403						     "T8 GMAC0 TXEN", "W11 GMAC1 TXEN",
404						     "U8 GMAC0 TXC", "V11 GMAC1 TXC",
405						     "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
406						     "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
407						     "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
408						     "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
409						     "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
410						     "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
411						     "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
412						     "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
413						skew-delay = <7>;
414					};
415					/* Set up drive strength on GMAC0 to 16 mA */
416					conf1 {
417						groups = "gmii_gmac0_grp";
418						drive-strength = <16>;
419					};
420				};
421			};
422		};
423
424		sata: sata@46000000 {
425			cortina,gemini-ata-muxmode = <0>;
426			cortina,gemini-enable-sata-bridge;
427			status = "okay";
428		};
429
430		gpio0: gpio@4d000000 {
431			pinctrl-names = "default";
432			pinctrl-0 = <&gpio0_default_pins>;
433		};
434
435		gpio1: gpio@4e000000 {
436			pinctrl-names = "default";
437			pinctrl-0 = <&gpio1_default_pins>;
438		};
439
440		pci@50000000 {
441			status = "okay";
442		};
443
444		ethernet@60000000 {
445			status = "okay";
446
447			ethernet-port@0 {
448				phy-mode = "rgmii";
449				fixed-link {
450					speed = <1000>;
451					full-duplex;
452					pause;
453				};
454			};
455			ethernet-port@1 {
456				/* Not used in this platform */
457			};
458		};
459
460		ide@63000000 {
461			status = "okay";
462
463			/*
464			 * This drive may have a temperature sensor with a
465			 * thermal zone we can use for thermal control of the
466			 * chassis temperature using the fan.
467			 */
468			drive0: ide-port@0 {
469				reg = <0>;
470				#thermal-sensor-cells = <0>;
471			};
472		};
473
474		display-controller@6a000000 {
475			status = "okay";
476
477			port {
478				display_out: endpoint {
479					remote-endpoint = <&panel_in>;
480				};
481			};
482		};
483
484		usb@68000000 {
485			status = "okay";
486		};
487
488		usb@69000000 {
489			status = "okay";
490		};
491	};
492};
493