1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. Versatile Express 4 * 5 * CoreTile Express A9x4 6 * Cortex-A9 MPCore (V2P-CA9) 7 * 8 * HBI-0191B 9 */ 10 11/dts-v1/; 12#include "vexpress-v2m.dtsi" 13 14/ { 15 model = "V2P-CA9"; 16 arm,hbi = <0x191>; 17 arm,vexpress,site = <0xf>; 18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 23 chosen { 24 stdout-path = &v2m_serial0; 25 }; 26 27 aliases { 28 serial0 = &v2m_serial0; 29 serial1 = &v2m_serial1; 30 serial2 = &v2m_serial2; 31 serial3 = &v2m_serial3; 32 i2c0 = &v2m_i2c_dvi; 33 i2c1 = &v2m_i2c_pcie; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 A9_0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a9"; 43 reg = <0>; 44 next-level-cache = <&L2>; 45 }; 46 47 A9_1: cpu@1 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a9"; 50 reg = <1>; 51 next-level-cache = <&L2>; 52 }; 53 54 A9_2: cpu@2 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a9"; 57 reg = <2>; 58 next-level-cache = <&L2>; 59 }; 60 61 A9_3: cpu@3 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a9"; 64 reg = <3>; 65 next-level-cache = <&L2>; 66 }; 67 }; 68 69 memory@60000000 { 70 device_type = "memory"; 71 reg = <0x60000000 0x40000000>; 72 }; 73 74 reserved-memory { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 ranges; 78 79 /* Chipselect 3 is physically at 0x4c000000 */ 80 vram: vram@4c000000 { 81 /* 8 MB of designated video RAM */ 82 compatible = "shared-dma-pool"; 83 reg = <0x4c000000 0x00800000>; 84 no-map; 85 }; 86 }; 87 88 clcd@10020000 { 89 compatible = "arm,pl111", "arm,primecell"; 90 reg = <0x10020000 0x1000>; 91 interrupt-names = "combined"; 92 interrupts = <0 44 4>; 93 clocks = <&oscclk1>, <&oscclk2>; 94 clock-names = "clcdclk", "apb_pclk"; 95 /* 1024x768 16bpp @65MHz */ 96 max-memory-bandwidth = <95000000>; 97 98 port { 99 clcd_pads_ct: endpoint { 100 remote-endpoint = <&dvi_bridge_in_ct>; 101 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 102 }; 103 }; 104 }; 105 106 memory-controller@100e0000 { 107 compatible = "arm,pl341", "arm,primecell"; 108 reg = <0x100e0000 0x1000>; 109 clocks = <&oscclk2>; 110 clock-names = "apb_pclk"; 111 }; 112 113 memory-controller@100e1000 { 114 compatible = "arm,pl354", "arm,primecell"; 115 reg = <0x100e1000 0x1000>; 116 interrupts = <0 45 4>, 117 <0 46 4>; 118 clocks = <&oscclk2>; 119 clock-names = "apb_pclk"; 120 }; 121 122 timer@100e4000 { 123 compatible = "arm,sp804", "arm,primecell"; 124 reg = <0x100e4000 0x1000>; 125 interrupts = <0 48 4>, 126 <0 49 4>; 127 clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>; 128 clock-names = "timer0clk", "timer1clk", "apb_pclk"; 129 status = "disabled"; 130 }; 131 132 watchdog@100e5000 { 133 compatible = "arm,sp805", "arm,primecell"; 134 reg = <0x100e5000 0x1000>; 135 interrupts = <0 51 4>; 136 clocks = <&oscclk2>, <&oscclk2>; 137 clock-names = "wdog_clk", "apb_pclk"; 138 }; 139 140 scu@1e000000 { 141 compatible = "arm,cortex-a9-scu"; 142 reg = <0x1e000000 0x58>; 143 }; 144 145 timer@1e000600 { 146 compatible = "arm,cortex-a9-twd-timer"; 147 reg = <0x1e000600 0x20>; 148 interrupts = <1 13 0xf04>; 149 }; 150 151 watchdog@1e000620 { 152 compatible = "arm,cortex-a9-twd-wdt"; 153 reg = <0x1e000620 0x20>; 154 interrupts = <1 14 0xf04>; 155 }; 156 157 gic: interrupt-controller@1e001000 { 158 compatible = "arm,cortex-a9-gic"; 159 #interrupt-cells = <3>; 160 #address-cells = <0>; 161 interrupt-controller; 162 reg = <0x1e001000 0x1000>, 163 <0x1e000100 0x100>; 164 }; 165 166 L2: cache-controller@1e00a000 { 167 compatible = "arm,pl310-cache"; 168 reg = <0x1e00a000 0x1000>; 169 interrupts = <0 43 4>; 170 cache-unified; 171 cache-level = <2>; 172 arm,data-latency = <1 1 1>; 173 arm,tag-latency = <1 1 1>; 174 }; 175 176 pmu { 177 compatible = "arm,cortex-a9-pmu"; 178 interrupts = <0 60 4>, 179 <0 61 4>, 180 <0 62 4>, 181 <0 63 4>; 182 interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; 183 184 }; 185 186 dcc { 187 compatible = "arm,vexpress,config-bus"; 188 arm,vexpress,config-bridge = <&v2m_sysreg>; 189 190 oscclk0: extsaxiclk { 191 /* ACLK clock to the AXI master port on the test chip */ 192 compatible = "arm,vexpress-osc"; 193 arm,vexpress-sysreg,func = <1 0>; 194 freq-range = <30000000 50000000>; 195 #clock-cells = <0>; 196 clock-output-names = "extsaxiclk"; 197 }; 198 199 oscclk1: clcdclk { 200 /* Reference clock for the CLCD */ 201 compatible = "arm,vexpress-osc"; 202 arm,vexpress-sysreg,func = <1 1>; 203 freq-range = <10000000 80000000>; 204 #clock-cells = <0>; 205 clock-output-names = "clcdclk"; 206 }; 207 208 smbclk: oscclk2: tcrefclk { 209 /* Reference clock for the test chip internal PLLs */ 210 compatible = "arm,vexpress-osc"; 211 arm,vexpress-sysreg,func = <1 2>; 212 freq-range = <33000000 100000000>; 213 #clock-cells = <0>; 214 clock-output-names = "tcrefclk"; 215 }; 216 217 volt-vd10 { 218 /* Test Chip internal logic voltage */ 219 compatible = "arm,vexpress-volt"; 220 arm,vexpress-sysreg,func = <2 0>; 221 regulator-name = "VD10"; 222 regulator-always-on; 223 label = "VD10"; 224 }; 225 226 volt-vd10-s2 { 227 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ 228 compatible = "arm,vexpress-volt"; 229 arm,vexpress-sysreg,func = <2 1>; 230 regulator-name = "VD10_S2"; 231 regulator-always-on; 232 label = "VD10_S2"; 233 }; 234 235 volt-vd10-s3 { 236 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ 237 compatible = "arm,vexpress-volt"; 238 arm,vexpress-sysreg,func = <2 2>; 239 regulator-name = "VD10_S3"; 240 regulator-always-on; 241 label = "VD10_S3"; 242 }; 243 244 volt-vcc1v8 { 245 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ 246 compatible = "arm,vexpress-volt"; 247 arm,vexpress-sysreg,func = <2 3>; 248 regulator-name = "VCC1V8"; 249 regulator-always-on; 250 label = "VCC1V8"; 251 }; 252 253 volt-ddr2vtt { 254 /* DDR2 SDRAM VTT termination voltage */ 255 compatible = "arm,vexpress-volt"; 256 arm,vexpress-sysreg,func = <2 4>; 257 regulator-name = "DDR2VTT"; 258 regulator-always-on; 259 label = "DDR2VTT"; 260 }; 261 262 volt-vcc3v3 { 263 /* Local board supply for miscellaneous logic external to the Test Chip */ 264 arm,vexpress-sysreg,func = <2 5>; 265 compatible = "arm,vexpress-volt"; 266 regulator-name = "VCC3V3"; 267 regulator-always-on; 268 label = "VCC3V3"; 269 }; 270 271 amp-vd10-s2 { 272 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ 273 compatible = "arm,vexpress-amp"; 274 arm,vexpress-sysreg,func = <3 0>; 275 label = "VD10_S2"; 276 }; 277 278 amp-vd10-s3 { 279 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ 280 compatible = "arm,vexpress-amp"; 281 arm,vexpress-sysreg,func = <3 1>; 282 label = "VD10_S3"; 283 }; 284 285 power-vd10-s2 { 286 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ 287 compatible = "arm,vexpress-power"; 288 arm,vexpress-sysreg,func = <12 0>; 289 label = "PVD10_S2"; 290 }; 291 292 power-vd10-s3 { 293 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ 294 compatible = "arm,vexpress-power"; 295 arm,vexpress-sysreg,func = <12 1>; 296 label = "PVD10_S3"; 297 }; 298 }; 299 300 site2: hsb@e0000000 { 301 compatible = "simple-bus"; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 ranges = <0 0xe0000000 0x20000000>; 305 #interrupt-cells = <1>; 306 interrupt-map-mask = <0 3>; 307 interrupt-map = <0 0 &gic 0 36 4>, 308 <0 1 &gic 0 37 4>, 309 <0 2 &gic 0 38 4>, 310 <0 3 &gic 0 39 4>; 311 }; 312}; 313