1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree for the ARM Integrator/AP platform 4 * with the IM-PD1 example logical module mounted. 5 */ 6 7#include "integratorap.dts" 8 9/ { 10 model = "ARM Integrator/AP with IM-PD1"; 11 compatible = "arm,integrator-ap"; 12 13 reserved-memory { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges; 17 18 impd1_ram: vram@c2000000 { 19 /* 1 MB of designated video RAM on the IM-PD1 */ 20 compatible = "shared-dma-pool"; 21 reg = <0xc2000000 0x00100000>; 22 no-map; 23 }; 24 }; 25}; 26 27&lm0 { 28 syscon@0 { 29 compatible = "arm,im-pd1-syscon", "syscon"; 30 reg = <0x00000000 0x1000>; 31 ranges; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 vco1: clock-controller@0 { 36 compatible = "arm,impd1-vco1"; 37 reg = <0x00 0x04>; 38 #clock-cells = <0>; 39 lock-offset = <0x08>; 40 vco-offset = <0x00>; 41 clocks = <&sysclk>; 42 clock-output-names = "IM-PD1-VCO1"; 43 }; 44 45 vco2: clock-controller@4 { 46 compatible = "arm,impd1-vco2"; 47 reg = <0x04 0x04>; 48 #clock-cells = <0>; 49 lock-offset = <0x08>; 50 vco-offset = <0x04>; 51 clocks = <&sysclk>; 52 clock-output-names = "IM-PD1-VCO2"; 53 }; 54 }; 55 56 /* Also used for the Smart Card Interface SCI */ 57 impd1_uartclk: clock@1_4 { 58 compatible = "fixed-factor-clock"; 59 #clock-cells = <0>; 60 clock-div = <4>; 61 clock-mult = <1>; 62 clocks = <&vco2>; 63 clock-output-names = "VCO2_DIV4"; 64 }; 65 66 /* For the SSP the clock is divided by 64 */ 67 impd1_sspclk: clock@1_64 { 68 compatible = "fixed-factor-clock"; 69 #clock-cells = <0>; 70 clock-div = <64>; 71 clock-mult = <1>; 72 clocks = <&vco2>; 73 clock-output-names = "VCO2_DIV64"; 74 }; 75 76 /* Fixed regulator for the MMC */ 77 impd1_3v3: regulator { 78 compatible = "regulator-fixed"; 79 regulator-name = "3V3"; 80 regulator-min-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>; 82 regulator-always-on; 83 }; 84 85 /* Push buttons on the IM-PD1 */ 86 gpio_keys { 87 compatible = "gpio-keys"; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 button@0 { 92 debounce-interval = <50>; 93 linux,code = <KEY_UP>; 94 label = "UP"; 95 gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>; 96 }; 97 button@1 { 98 debounce-interval = <50>; 99 linux,code = <KEY_DOWN>; 100 label = "DOWN"; 101 gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>; 102 }; 103 button@2 { 104 debounce-interval = <50>; 105 linux,code = <KEY_LEFT>; 106 label = "LEFT"; 107 gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>; 108 }; 109 button@3 { 110 debounce-interval = <50>; 111 linux,code = <KEY_RIGHT>; 112 label = "UP"; 113 gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>; 114 }; 115 button@4 { 116 debounce-interval = <50>; 117 linux,code = <KEY_ESC>; 118 label = "ESC"; 119 gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>; 120 }; 121 button@5 { 122 debounce-interval = <50>; 123 linux,code = <KEY_ENTER>; 124 label = "ENTER"; 125 gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>; 126 }; 127 }; 128 129 130 bridge { 131 compatible = "ti,ths8134b", "ti,ths8134"; 132 133 ports { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 port@0 { 137 reg = <0>; 138 vga_bridge_in: endpoint { 139 remote-endpoint = <&clcd_pads_vga_dac>; 140 }; 141 }; 142 143 port@1 { 144 reg = <1>; 145 146 vga_bridge_out: endpoint { 147 remote-endpoint = <&vga_con_in>; 148 }; 149 }; 150 }; 151 }; 152 153 vga { 154 compatible = "vga-connector"; 155 label = "J30"; 156 157 port { 158 vga_con_in: endpoint { 159 remote-endpoint = <&vga_bridge_out>; 160 }; 161 }; 162 }; 163 164 serial@100000 { 165 compatible = "arm,pl011", "arm,primecell"; 166 reg = <0x00100000 0x1000>; 167 interrupts-extended = <&impd1_vic 1>; 168 clocks = <&impd1_uartclk>, <&sysclk>; 169 clock-names = "uartclk", "apb_pclk"; 170 }; 171 172 serial@200000 { 173 compatible = "arm,pl011", "arm,primecell"; 174 reg = <0x00200000 0x1000>; 175 interrupts-extended = <&impd1_vic 2>; 176 clocks = <&impd1_uartclk>, <&sysclk>; 177 clock-names = "uartclk", "apb_pclk"; 178 }; 179 180 spi@300000 { 181 compatible = "arm,pl022", "arm,primecell"; 182 reg = <0x00300000 0x1000>; 183 interrupts-extended = <&impd1_vic 3>; 184 clocks = <&impd1_sspclk>, <&sysclk>; 185 clock-names = "sspclk", "apb_pclk"; 186 }; 187 188 impd1_gpio0: gpio@400000 { 189 compatible = "arm,pl061", "arm,primecell"; 190 reg = <0x00400000 0x1000>; 191 gpio-controller; 192 #gpio-cells = <2>; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 interrupts-extended = <&impd1_vic 4>; 196 clocks = <&sysclk>; 197 clock-names = "apb_pclk"; 198 }; 199 200 impd1_gpio1: gpio@500000 { 201 compatible = "arm,pl061", "arm,primecell"; 202 reg = <0x00500000 0x1000>; 203 gpio-controller; 204 #gpio-cells = <2>; 205 interrupt-controller; 206 #interrupt-cells = <2>; 207 interrupts-extended = <&impd1_vic 5>; 208 clocks = <&sysclk>; 209 clock-names = "apb_pclk"; 210 }; 211 212 rtc@600000 { 213 compatible = "arm,pl030", "arm,primecell"; 214 reg = <0x00600000 0x1000>; 215 interrupts-extended = <&impd1_vic 6>; 216 clocks = <&sysclk>; 217 clock-names = "apb_pclk"; 218 }; 219 220 mmc@700000 { 221 compatible = "arm,pl181", "arm,primecell"; 222 reg = <0x00700000 0x1000>; 223 interrupts-extended = <&impd1_vic 7>, 224 <&impd1_vic 8>; 225 clocks = <&sysclk>, <&sysclk>; 226 clock-names = "mclk", "apb_pclk"; 227 bus-width = <1>; 228 max-frequency = <515633>; 229 vmmc-supply = <&impd1_3v3>; 230 wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>; 231 cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>; 232 }; 233 234 aaci@800000 { 235 compatible = "arm,pl041", "arm,primecell"; 236 reg = <0x00800000 0x1000>; 237 interrupts-extended = <&impd1_vic 9>; 238 clocks = <&sysclk>; 239 clock-names = "apb_pclk"; 240 }; 241 242 display@1000000 { 243 compatible = "arm,pl110", "arm,primecell"; 244 reg = <0x01000000 0x1000>; 245 interrupts-extended = <&impd1_vic 11>; 246 clocks = <&vco1>, <&sysclk>; 247 clock-names = "clcdclk", "apb_pclk"; 248 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ 249 max-memory-bandwidth = <40000000>; 250 memory-region = <&impd1_ram>; 251 dma-ranges; 252 253 port@0 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 257 clcd_pads_vga_dac: endpoint@0 { 258 reg = <0>; 259 remote-endpoint = <&vga_bridge_in>; 260 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 261 }; 262 }; 263 }; 264 265 impd1_vic: interrupt-controller@3000000 { 266 compatible = "arm,pl192-vic"; 267 interrupt-controller; 268 #interrupt-cells = <1>; 269 reg = <0x03000000 0x1000>; 270 /* Valid interrupts, 0-9 and 11 */ 271 valid-mask = <0x00000bff>; 272 /* LM site 0 has IRQ 9 on the PIC */ 273 interrupts-extended = <&pic 9>; 274 }; 275}; 276