1/* 2 * Copyright 2015 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23/dts-v1/; 24#include <dt-bindings/interrupt-controller/irq.h> 25#include <dt-bindings/gpio/gpio.h> 26 27/ { 28 #address-cells = <1>; 29 #size-cells = <1>; 30 model = "ARM RealView PB11MPcore"; 31 compatible = "arm,realview-pb11mp"; 32 33 chosen { }; 34 35 aliases { 36 serial0 = &pb11mp_serial0; 37 serial1 = &pb11mp_serial1; 38 serial2 = &pb11mp_serial2; 39 serial3 = &pb11mp_serial3; 40 }; 41 42 memory { 43 device_type = "memory"; 44 /* 45 * The PB11MPCore has 512 MiB memory @ 0x70000000 46 * and the first 256 are also remapped @ 0x00000000 47 */ 48 reg = <0x70000000 0x20000000>; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 enable-method = "arm,realview-smp"; 55 56 MP11_0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,arm11mpcore"; 59 reg = <0>; 60 next-level-cache = <&L2>; 61 }; 62 63 MP11_1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,arm11mpcore"; 66 reg = <1>; 67 next-level-cache = <&L2>; 68 }; 69 70 MP11_2: cpu@2 { 71 device_type = "cpu"; 72 compatible = "arm,arm11mpcore"; 73 reg = <2>; 74 next-level-cache = <&L2>; 75 }; 76 77 MP11_3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,arm11mpcore"; 80 reg = <3>; 81 next-level-cache = <&L2>; 82 }; 83 }; 84 85 /* Primary TestChip GIC synthesized with the CPU */ 86 intc_tc11mp: interrupt-controller@1f000100 { 87 compatible = "arm,tc11mp-gic"; 88 #interrupt-cells = <3>; 89 #address-cells = <1>; 90 interrupt-controller; 91 reg = <0x1f001000 0x1000>, 92 <0x1f000100 0x100>; 93 }; 94 95 L2: cache-controller { 96 compatible = "arm,l220-cache"; 97 reg = <0x1f002000 0x1000>; 98 interrupt-parent = <&intc_tc11mp>; 99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, 100 <0 30 IRQ_TYPE_LEVEL_HIGH>, 101 <0 31 IRQ_TYPE_LEVEL_HIGH>; 102 cache-unified; 103 cache-level = <2>; 104 /* 105 * Override default cache size, sets and 106 * associativity as these may be erroneously set 107 * up by boot loader(s), probably for safety 108 * since th outer sync operation can cause the 109 * cache to hang unless disabled. 110 */ 111 cache-size = <1048576>; // 1MB 112 cache-sets = <4096>; 113 cache-line-size = <32>; 114 arm,shared-override; 115 arm,parity-enable; 116 arm,outer-sync-disable; 117 }; 118 119 scu@1f000000 { 120 compatible = "arm,arm11mp-scu"; 121 reg = <0x1f000000 0x100>; 122 }; 123 124 timer@1f000600 { 125 compatible = "arm,arm11mp-twd-timer"; 126 reg = <0x1f000600 0x20>; 127 interrupt-parent = <&intc_tc11mp>; 128 interrupts = <1 13 0xf04>; 129 }; 130 131 watchdog@1f000620 { 132 compatible = "arm,arm11mp-twd-wdt"; 133 reg = <0x1f000620 0x20>; 134 interrupt-parent = <&intc_tc11mp>; 135 interrupts = <1 14 0xf04>; 136 }; 137 138 /* PMU with one IRQ line per core */ 139 pmu { 140 compatible = "arm,arm11mpcore-pmu"; 141 interrupt-parent = <&intc_tc11mp>; 142 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, 143 <0 18 IRQ_TYPE_LEVEL_HIGH>, 144 <0 19 IRQ_TYPE_LEVEL_HIGH>, 145 <0 20 IRQ_TYPE_LEVEL_HIGH>; 146 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; 147 }; 148 149 /* The voltage to the MMC card is hardwired at 3.3V */ 150 vmmc: regulator-vmmc { 151 compatible = "regulator-fixed"; 152 regulator-name = "vmmc"; 153 regulator-min-microvolt = <3300000>; 154 regulator-max-microvolt = <3300000>; 155 regulator-boot-on; 156 }; 157 158 veth: regulator-veth { 159 compatible = "regulator-fixed"; 160 regulator-name = "veth"; 161 regulator-min-microvolt = <3300000>; 162 regulator-max-microvolt = <3300000>; 163 regulator-boot-on; 164 }; 165 166 xtal24mhz: xtal24mhz@24M { 167 #clock-cells = <0>; 168 compatible = "fixed-clock"; 169 clock-frequency = <24000000>; 170 }; 171 172 refclk32khz: refclk32khz { 173 compatible = "fixed-clock"; 174 #clock-cells = <0>; 175 clock-frequency = <32768>; 176 }; 177 178 timclk: timclk@1M { 179 #clock-cells = <0>; 180 compatible = "fixed-factor-clock"; 181 clock-div = <24>; 182 clock-mult = <1>; 183 clocks = <&xtal24mhz>; 184 }; 185 186 mclk: mclk@24M { 187 #clock-cells = <0>; 188 compatible = "fixed-factor-clock"; 189 clock-div = <1>; 190 clock-mult = <1>; 191 clocks = <&xtal24mhz>; 192 }; 193 194 kmiclk: kmiclk@24M { 195 #clock-cells = <0>; 196 compatible = "fixed-factor-clock"; 197 clock-div = <1>; 198 clock-mult = <1>; 199 clocks = <&xtal24mhz>; 200 }; 201 202 sspclk: sspclk@24M { 203 #clock-cells = <0>; 204 compatible = "fixed-factor-clock"; 205 clock-div = <1>; 206 clock-mult = <1>; 207 clocks = <&xtal24mhz>; 208 }; 209 210 uartclk: uartclk@24M { 211 #clock-cells = <0>; 212 compatible = "fixed-factor-clock"; 213 clock-div = <1>; 214 clock-mult = <1>; 215 clocks = <&xtal24mhz>; 216 }; 217 218 wdogclk: wdogclk@24M { 219 #clock-cells = <0>; 220 compatible = "fixed-factor-clock"; 221 clock-div = <1>; 222 clock-mult = <1>; 223 clocks = <&xtal24mhz>; 224 }; 225 226 /* FIXME: this actually hangs off the PLL clocks */ 227 pclk: pclk@0 { 228 #clock-cells = <0>; 229 compatible = "fixed-clock"; 230 clock-frequency = <0>; 231 }; 232 233 flash0@40000000 { 234 /* 2 * 32MiB NOR Flash memory */ 235 compatible = "arm,versatile-flash", "cfi-flash"; 236 reg = <0x40000000 0x04000000>; 237 bank-width = <4>; 238 partitions { 239 compatible = "arm,arm-firmware-suite"; 240 }; 241 }; 242 243 flash1@44000000 { 244 // 2 * 32MiB NOR Flash memory 245 compatible = "arm,versatile-flash", "cfi-flash"; 246 reg = <0x44000000 0x04000000>; 247 bank-width = <4>; 248 partitions { 249 compatible = "arm,arm-firmware-suite"; 250 }; 251 }; 252 253 bridge { 254 compatible = "ti,ths8134a", "ti,ths8134"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 258 ports { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 262 port@0 { 263 reg = <0>; 264 265 vga_bridge_in: endpoint { 266 remote-endpoint = <&clcd_pads>; 267 }; 268 }; 269 270 port@1 { 271 reg = <1>; 272 273 vga_bridge_out: endpoint { 274 remote-endpoint = <&vga_con_in>; 275 }; 276 }; 277 }; 278 }; 279 280 vga { 281 /* 282 * This DDC I2C is connected directly to the DVI portions 283 * of the connector, so it's not really working when the 284 * monitor is connected to the VGA connector. 285 */ 286 compatible = "vga-connector"; 287 ddc-i2c-bus = <&i2c1>; 288 289 port { 290 vga_con_in: endpoint { 291 remote-endpoint = <&vga_bridge_out>; 292 }; 293 }; 294 }; 295 296 soc { 297 #address-cells = <1>; 298 #size-cells = <1>; 299 compatible = "arm,realview-pb11mp-soc", "simple-bus"; 300 regmap = <&pb11mp_syscon>; 301 ranges; 302 303 pb11mp_syscon: syscon@10000000 { 304 compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd"; 305 reg = <0x10000000 0x1000>; 306 ranges = <0x0 0x10000000 0x1000>; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 310 led@8,0 { 311 compatible = "register-bit-led"; 312 reg = <0x08 0x04>; 313 offset = <0x08>; 314 mask = <0x01>; 315 label = "versatile:0"; 316 linux,default-trigger = "heartbeat"; 317 default-state = "on"; 318 }; 319 led@8,1 { 320 compatible = "register-bit-led"; 321 reg = <0x08 0x04>; 322 offset = <0x08>; 323 mask = <0x02>; 324 label = "versatile:1"; 325 linux,default-trigger = "mmc0"; 326 default-state = "off"; 327 }; 328 led@8,2 { 329 compatible = "register-bit-led"; 330 reg = <0x08 0x04>; 331 offset = <0x08>; 332 mask = <0x04>; 333 label = "versatile:2"; 334 linux,default-trigger = "cpu0"; 335 default-state = "off"; 336 }; 337 led@8,3 { 338 compatible = "register-bit-led"; 339 reg = <0x08 0x04>; 340 offset = <0x08>; 341 mask = <0x08>; 342 label = "versatile:3"; 343 linux,default-trigger = "cpu1"; 344 default-state = "off"; 345 }; 346 led@8,4 { 347 compatible = "register-bit-led"; 348 reg = <0x08 0x04>; 349 offset = <0x08>; 350 mask = <0x10>; 351 label = "versatile:4"; 352 linux,default-trigger = "cpu2"; 353 default-state = "off"; 354 }; 355 led@8,5 { 356 compatible = "register-bit-led"; 357 reg = <0x08 0x04>; 358 offset = <0x08>; 359 mask = <0x20>; 360 label = "versatile:5"; 361 linux,default-trigger = "cpu3"; 362 default-state = "off"; 363 }; 364 led@8,6 { 365 compatible = "register-bit-led"; 366 reg = <0x08 0x04>; 367 offset = <0x08>; 368 mask = <0x40>; 369 label = "versatile:6"; 370 default-state = "off"; 371 }; 372 led@8,7 { 373 compatible = "register-bit-led"; 374 reg = <0x08 0x04>; 375 offset = <0x08>; 376 mask = <0x80>; 377 label = "versatile:7"; 378 default-state = "off"; 379 }; 380 381 oscclk0: clock-controller@c { 382 compatible = "arm,syscon-icst307"; 383 reg = <0x0c 0x04>; 384 #clock-cells = <0>; 385 lock-offset = <0x20>; 386 vco-offset = <0x0C>; 387 clocks = <&xtal24mhz>; 388 }; 389 oscclk1: clock-controller@10 { 390 compatible = "arm,syscon-icst307"; 391 reg = <0x10 0x04>; 392 #clock-cells = <0>; 393 lock-offset = <0x20>; 394 vco-offset = <0x10>; 395 clocks = <&xtal24mhz>; 396 }; 397 oscclk2: clock-controller@14 { 398 compatible = "arm,syscon-icst307"; 399 reg = <0x14 0x04>; 400 #clock-cells = <0>; 401 lock-offset = <0x20>; 402 vco-offset = <0x14>; 403 clocks = <&xtal24mhz>; 404 }; 405 oscclk3: clock-controller@18 { 406 compatible = "arm,syscon-icst307"; 407 reg = <0x18 0x04>; 408 #clock-cells = <0>; 409 lock-offset = <0x20>; 410 vco-offset = <0x18>; 411 clocks = <&xtal24mhz>; 412 }; 413 oscclk4: clock-controller@1c { 414 compatible = "arm,syscon-icst307"; 415 reg = <0x1c 0x04>; 416 #clock-cells = <0>; 417 lock-offset = <0x20>; 418 vco-offset = <0x1c>; 419 clocks = <&xtal24mhz>; 420 }; 421 oscclk5: clock-controller@d4 { 422 compatible = "arm,syscon-icst307"; 423 reg = <0xd4 0x04>; 424 #clock-cells = <0>; 425 lock-offset = <0x20>; 426 vco-offset = <0xd4>; 427 clocks = <&xtal24mhz>; 428 }; 429 oscclk6: clock-controller@d8 { 430 compatible = "arm,syscon-icst307"; 431 reg = <0xd8 0x04>; 432 #clock-cells = <0>; 433 lock-offset = <0x20>; 434 vco-offset = <0xd8>; 435 clocks = <&xtal24mhz>; 436 }; 437 }; 438 439 sp810_syscon: sysctl@10001000 { 440 compatible = "arm,sp810", "arm,primecell"; 441 reg = <0x10001000 0x1000>; 442 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 443 clock-names = "refclk", "timclk", "apb_pclk"; 444 #clock-cells = <1>; 445 clock-output-names = "timerclk0", 446 "timerclk1", 447 "timerclk2", 448 "timerclk3"; 449 assigned-clocks = <&sp810_syscon 0>, 450 <&sp810_syscon 1>, 451 <&sp810_syscon 2>, 452 <&sp810_syscon 3>; 453 assigned-clock-parents = <&timclk>, 454 <&timclk>, 455 <&timclk>, 456 <&timclk>; 457 }; 458 459 i2c0: i2c@10002000 { 460 #address-cells = <1>; 461 #size-cells = <0>; 462 compatible = "arm,versatile-i2c"; 463 reg = <0x10002000 0x1000>; 464 465 rtc@68 { 466 compatible = "dallas,ds1338"; 467 reg = <0x68>; 468 }; 469 }; 470 471 aaci: aaci@10004000 { 472 compatible = "arm,pl041", "arm,primecell"; 473 reg = <0x10004000 0x1000>; 474 interrupt-parent = <&intc_tc11mp>; 475 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&pclk>; 477 clock-names = "apb_pclk"; 478 }; 479 480 mci: mmcsd@10005000 { 481 compatible = "arm,pl18x", "arm,primecell"; 482 reg = <0x10005000 0x1000>; 483 interrupt-parent = <&intc_tc11mp>; 484 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, 485 <0 15 IRQ_TYPE_LEVEL_HIGH>; 486 /* Due to frequent FIFO overruns, use just 500 kHz */ 487 max-frequency = <500000>; 488 bus-width = <4>; 489 cap-sd-highspeed; 490 cap-mmc-highspeed; 491 clocks = <&mclk>, <&pclk>; 492 clock-names = "mclk", "apb_pclk"; 493 vmmc-supply = <&vmmc>; 494 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 495 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 496 }; 497 498 kmi0: kmi@10006000 { 499 compatible = "arm,pl050", "arm,primecell"; 500 reg = <0x10006000 0x1000>; 501 interrupt-parent = <&intc_tc11mp>; 502 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&kmiclk>, <&pclk>; 504 clock-names = "KMIREFCLK", "apb_pclk"; 505 }; 506 507 kmi1: kmi@10007000 { 508 compatible = "arm,pl050", "arm,primecell"; 509 reg = <0x10007000 0x1000>; 510 interrupt-parent = <&intc_tc11mp>; 511 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&kmiclk>, <&pclk>; 513 clock-names = "KMIREFCLK", "apb_pclk"; 514 }; 515 516 pb11mp_serial0: serial@10009000 { 517 compatible = "arm,pl011", "arm,primecell"; 518 reg = <0x10009000 0x1000>; 519 interrupt-parent = <&intc_tc11mp>; 520 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&uartclk>, <&pclk>; 522 clock-names = "uartclk", "apb_pclk"; 523 }; 524 525 pb11mp_serial1: serial@1000a000 { 526 compatible = "arm,pl011", "arm,primecell"; 527 reg = <0x1000a000 0x1000>; 528 interrupt-parent = <&intc_tc11mp>; 529 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&uartclk>, <&pclk>; 531 clock-names = "uartclk", "apb_pclk"; 532 }; 533 534 pb11mp_serial2: serial@1000b000 { 535 compatible = "arm,pl011", "arm,primecell"; 536 reg = <0x1000b000 0x1000>; 537 interrupt-parent = <&intc_pb11mp>; 538 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&uartclk>, <&pclk>; 540 clock-names = "uartclk", "apb_pclk"; 541 }; 542 543 pb11mp_serial3: serial@1000c000 { 544 compatible = "arm,pl011", "arm,primecell"; 545 reg = <0x1000c000 0x1000>; 546 interrupt-parent = <&intc_pb11mp>; 547 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&uartclk>, <&pclk>; 549 clock-names = "uartclk", "apb_pclk"; 550 }; 551 552 spi@1000d000 { 553 compatible = "arm,pl022", "arm,primecell"; 554 reg = <0x1000d000 0x1000>; 555 interrupt-parent = <&intc_pb11mp>; 556 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&sspclk>, <&pclk>; 558 clock-names = "sspclk", "apb_pclk"; 559 }; 560 561 watchdog@1000f000 { 562 compatible = "arm,sp805", "arm,primecell"; 563 reg = <0x1000f000 0x1000>; 564 interrupt-parent = <&intc_pb11mp>; 565 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&wdogclk>, <&pclk>; 567 clock-names = "wdog_clk", "apb_pclk"; 568 status = "disabled"; 569 }; 570 571 watchdog@10010000 { 572 compatible = "arm,sp805", "arm,primecell"; 573 reg = <0x10010000 0x1000>; 574 interrupt-parent = <&intc_pb11mp>; 575 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&wdogclk>, <&pclk>; 577 clock-names = "wdog_clk", "apb_pclk"; 578 }; 579 580 timer01: timer@10011000 { 581 compatible = "arm,sp804", "arm,primecell"; 582 reg = <0x10011000 0x1000>; 583 interrupt-parent = <&intc_tc11mp>; 584 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; 585 arm,sp804-has-irq = <1>; 586 clocks = <&sp810_syscon 0>, 587 <&sp810_syscon 1>, 588 <&pclk>; 589 clock-names = "timer0clk", 590 "timer1clk", 591 "apb_pclk"; 592 }; 593 594 timer23: timer@10012000 { 595 compatible = "arm,sp804", "arm,primecell"; 596 reg = <0x10012000 0x1000>; 597 interrupt-parent = <&intc_tc11mp>; 598 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 599 arm,sp804-has-irq = <1>; 600 clocks = <&sp810_syscon 2>, 601 <&sp810_syscon 3>, 602 <&pclk>; 603 clock-names = "timer0clk", 604 "timer1clk", 605 "apb_pclk"; 606 }; 607 608 gpio0: gpio@10013000 { 609 compatible = "arm,pl061", "arm,primecell"; 610 reg = <0x10013000 0x1000>; 611 gpio-controller; 612 interrupt-parent = <&intc_pb11mp>; 613 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 614 #gpio-cells = <2>; 615 interrupt-controller; 616 #interrupt-cells = <2>; 617 clocks = <&pclk>; 618 clock-names = "apb_pclk"; 619 }; 620 621 gpio1: gpio@10014000 { 622 compatible = "arm,pl061", "arm,primecell"; 623 reg = <0x10014000 0x1000>; 624 gpio-controller; 625 interrupt-parent = <&intc_pb11mp>; 626 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 627 #gpio-cells = <2>; 628 interrupt-controller; 629 #interrupt-cells = <2>; 630 clocks = <&pclk>; 631 clock-names = "apb_pclk"; 632 }; 633 634 gpio2: gpio@10015000 { 635 compatible = "arm,pl061", "arm,primecell"; 636 reg = <0x10015000 0x1000>; 637 gpio-controller; 638 interrupt-parent = <&intc_pb11mp>; 639 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 640 #gpio-cells = <2>; 641 interrupt-controller; 642 #interrupt-cells = <2>; 643 clocks = <&pclk>; 644 clock-names = "apb_pclk"; 645 }; 646 647 i2c1: i2c@10016000 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 compatible = "arm,versatile-i2c"; 651 reg = <0x10016000 0x1000>; 652 }; 653 654 rtc: rtc@10017000 { 655 compatible = "arm,pl031", "arm,primecell"; 656 reg = <0x10017000 0x1000>; 657 interrupt-parent = <&intc_tc11mp>; 658 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&pclk>; 660 clock-names = "apb_pclk"; 661 }; 662 663 timer45: timer@10018000 { 664 compatible = "arm,sp804", "arm,primecell"; 665 reg = <0x10018000 0x1000>; 666 clocks = <&timclk>, <&timclk>, <&pclk>; 667 clock-names = "timer0clk", "timer1clk", "apb_pclk"; 668 status = "disabled"; 669 }; 670 671 timer67: timer@10019000 { 672 compatible = "arm,sp804", "arm,primecell"; 673 reg = <0x10019000 0x1000>; 674 clocks = <&timclk>, <&timclk>, <&pclk>; 675 clock-names = "timer0clk", "timer1clk", "apb_pclk"; 676 status = "disabled"; 677 }; 678 679 680 clcd@10020000 { 681 compatible = "arm,pl111", "arm,primecell"; 682 reg = <0x10020000 0x1000>; 683 interrupt-parent = <&intc_pb11mp>; 684 interrupt-names = "combined"; 685 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&oscclk4>, <&pclk>; 687 clock-names = "clcdclk", "apb_pclk"; 688 /* 1024x768 16bpp @65MHz works fine */ 689 max-memory-bandwidth = <95000000>; 690 691 port { 692 clcd_pads: endpoint { 693 remote-endpoint = <&vga_bridge_in>; 694 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 695 }; 696 }; 697 }; 698 699 /* 700 * This GIC on the Platform Baseboard is cascaded off the 701 * TestChip GIC 702 */ 703 intc_pb11mp: interrupt-controller@1e000000 { 704 compatible = "arm,arm11mp-gic"; 705 #interrupt-cells = <3>; 706 #address-cells = <1>; 707 interrupt-controller; 708 reg = <0x1e001000 0x1000>, 709 <0x1e000000 0x100>; 710 interrupt-parent = <&intc_tc11mp>; 711 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 712 }; 713 714 /* SMSC 9118 ethernet with PHY and EEPROM */ 715 ethernet@4e000000 { 716 compatible = "smsc,lan9118", "smsc,lan9115"; 717 reg = <0x4e000000 0x10000>; 718 interrupt-parent = <&intc_tc11mp>; 719 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 720 phy-mode = "mii"; 721 reg-io-width = <4>; 722 smsc,irq-active-high; 723 smsc,irq-push-pull; 724 vdd33a-supply = <&veth>; 725 vddvario-supply = <&veth>; 726 }; 727 728 usb@4f000000 { 729 compatible = "nxp,usb-isp1761"; 730 reg = <0x4f000000 0x20000>; 731 interrupt-parent = <&intc_tc11mp>; 732 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 733 dr_mode = "peripheral"; 734 }; 735 }; 736}; 737