1/* 2 * Copyright 2014 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23/dts-v1/; 24#include <dt-bindings/interrupt-controller/irq.h> 25#include <dt-bindings/gpio/gpio.h> 26 27/ { 28 #address-cells = <1>; 29 #size-cells = <1>; 30 model = "ARM RealView PB1176"; 31 compatible = "arm,realview-pb1176"; 32 33 chosen { }; 34 35 aliases { 36 serial0 = &pb1176_serial0; 37 serial1 = &pb1176_serial1; 38 serial2 = &pb1176_serial2; 39 serial3 = &pb1176_serial3; 40 serial4 = &fpga_serial; 41 }; 42 43 memory { 44 device_type = "memory"; 45 /* 128 MiB memory @ 0x0 */ 46 reg = <0x00000000 0x08000000>; 47 }; 48 49 /* The voltage to the MMC card is hardwired at 3.3V */ 50 vmmc: regulator-vmmc { 51 compatible = "regulator-fixed"; 52 regulator-name = "vmmc"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 regulator-boot-on; 56 }; 57 58 veth: regulator-veth { 59 compatible = "regulator-fixed"; 60 regulator-name = "veth"; 61 regulator-min-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>; 63 regulator-boot-on; 64 }; 65 66 xtal24mhz: xtal24mhz@24M { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <24000000>; 70 }; 71 72 timclk: timclk@1M { 73 #clock-cells = <0>; 74 compatible = "fixed-factor-clock"; 75 clock-div = <24>; 76 clock-mult = <1>; 77 clocks = <&xtal24mhz>; 78 }; 79 80 mclk: mclk@24M { 81 #clock-cells = <0>; 82 compatible = "fixed-factor-clock"; 83 clock-div = <1>; 84 clock-mult = <1>; 85 clocks = <&xtal24mhz>; 86 }; 87 88 kmiclk: kmiclk@24M { 89 #clock-cells = <0>; 90 compatible = "fixed-factor-clock"; 91 clock-div = <1>; 92 clock-mult = <1>; 93 clocks = <&xtal24mhz>; 94 }; 95 96 sspclk: sspclk@24M { 97 #clock-cells = <0>; 98 compatible = "fixed-factor-clock"; 99 clock-div = <1>; 100 clock-mult = <1>; 101 clocks = <&xtal24mhz>; 102 }; 103 104 uartclk: uartclk@24M { 105 #clock-cells = <0>; 106 compatible = "fixed-factor-clock"; 107 clock-div = <1>; 108 clock-mult = <1>; 109 clocks = <&xtal24mhz>; 110 }; 111 112 /* FIXME: this actually hangs off the PLL clocks */ 113 pclk: pclk@0 { 114 #clock-cells = <0>; 115 compatible = "fixed-clock"; 116 clock-frequency = <0>; 117 }; 118 119 flash@30000000 { 120 compatible = "arm,versatile-flash", "cfi-flash"; 121 reg = <0x30000000 0x4000000>; 122 bank-width = <4>; 123 partitions { 124 compatible = "arm,arm-firmware-suite"; 125 }; 126 }; 127 128 fpga_flash@38000000 { 129 compatible = "arm,versatile-flash", "cfi-flash"; 130 reg = <0x38000000 0x800000>; 131 bank-width = <4>; 132 partitions { 133 compatible = "arm,arm-firmware-suite"; 134 }; 135 }; 136 137 /* 138 * The "secure flash" contains things like the boot 139 * monitor so we don't want people to accidentally 140 * screw this up. Mark the device tree node disabled 141 * by default. 142 */ 143 secflash@3c000000 { 144 compatible = "arm,versatile-flash", "cfi-flash"; 145 reg = <0x3c000000 0x4000000>; 146 bank-width = <4>; 147 status = "disabled"; 148 }; 149 150 /* SMSC 9118 ethernet with PHY and EEPROM */ 151 ethernet@3a000000 { 152 compatible = "smsc,lan9118", "smsc,lan9115"; 153 reg = <0x3a000000 0x10000>; 154 interrupt-parent = <&intc_fpga1176>; 155 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 156 phy-mode = "mii"; 157 reg-io-width = <4>; 158 smsc,irq-active-high; 159 smsc,irq-push-pull; 160 vdd33a-supply = <&veth>; 161 vddvario-supply = <&veth>; 162 }; 163 164 usb@3b000000 { 165 compatible = "nxp,usb-isp1761"; 166 reg = <0x3b000000 0x20000>; 167 interrupt-parent = <&intc_fpga1176>; 168 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 169 dr_mode = "peripheral"; 170 }; 171 172 bridge { 173 compatible = "ti,ths8134a", "ti,ths8134"; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 ports { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 181 port@0 { 182 reg = <0>; 183 184 vga_bridge_in: endpoint { 185 remote-endpoint = <&clcd_pads>; 186 }; 187 }; 188 189 port@1 { 190 reg = <1>; 191 192 vga_bridge_out: endpoint { 193 remote-endpoint = <&vga_con_in>; 194 }; 195 }; 196 }; 197 }; 198 199 vga { 200 compatible = "vga-connector"; 201 202 port { 203 vga_con_in: endpoint { 204 remote-endpoint = <&vga_bridge_out>; 205 }; 206 }; 207 }; 208 209 soc { 210 #address-cells = <1>; 211 #size-cells = <1>; 212 compatible = "arm,realview-pb1176-soc", "simple-bus"; 213 regmap = <&syscon>; 214 ranges; 215 216 syscon: syscon@10000000 { 217 compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; 218 reg = <0x10000000 0x1000>; 219 ranges = <0x0 0x10000000 0x1000>; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 223 led@8,0 { 224 compatible = "register-bit-led"; 225 reg = <0x08 0x04>; 226 offset = <0x08>; 227 mask = <0x01>; 228 label = "versatile:0"; 229 linux,default-trigger = "heartbeat"; 230 default-state = "on"; 231 }; 232 led@8,1 { 233 compatible = "register-bit-led"; 234 reg = <0x08 0x04>; 235 offset = <0x08>; 236 mask = <0x02>; 237 label = "versatile:1"; 238 linux,default-trigger = "mmc0"; 239 default-state = "off"; 240 }; 241 led@8,2 { 242 compatible = "register-bit-led"; 243 reg = <0x08 0x04>; 244 offset = <0x08>; 245 mask = <0x04>; 246 label = "versatile:2"; 247 linux,default-trigger = "cpu0"; 248 default-state = "off"; 249 }; 250 led@8,3 { 251 compatible = "register-bit-led"; 252 reg = <0x08 0x04>; 253 offset = <0x08>; 254 mask = <0x08>; 255 label = "versatile:3"; 256 default-state = "off"; 257 }; 258 led@8,4 { 259 compatible = "register-bit-led"; 260 reg = <0x08 0x04>; 261 offset = <0x08>; 262 mask = <0x10>; 263 label = "versatile:4"; 264 default-state = "off"; 265 }; 266 led@8,5 { 267 compatible = "register-bit-led"; 268 reg = <0x08 0x04>; 269 offset = <0x08>; 270 mask = <0x20>; 271 label = "versatile:5"; 272 default-state = "off"; 273 }; 274 led@8,6 { 275 compatible = "register-bit-led"; 276 reg = <0x08 0x04>; 277 offset = <0x08>; 278 mask = <0x40>; 279 label = "versatile:6"; 280 default-state = "off"; 281 }; 282 led@8,7 { 283 compatible = "register-bit-led"; 284 reg = <0x08 0x04>; 285 offset = <0x08>; 286 mask = <0x80>; 287 label = "versatile:7"; 288 default-state = "off"; 289 }; 290 oscclk0: clock-controller@c { 291 compatible = "arm,syscon-icst307"; 292 reg = <0x0c 0x04>; 293 #clock-cells = <0>; 294 lock-offset = <0x20>; 295 vco-offset = <0x0C>; 296 clocks = <&xtal24mhz>; 297 }; 298 oscclk1: clock-controller@10 { 299 compatible = "arm,syscon-icst307"; 300 reg = <0x10 0x04>; 301 #clock-cells = <0>; 302 lock-offset = <0x20>; 303 vco-offset = <0x10>; 304 clocks = <&xtal24mhz>; 305 }; 306 oscclk2: clock-controller@14 { 307 compatible = "arm,syscon-icst307"; 308 reg = <0x14 0x04>; 309 #clock-cells = <0>; 310 lock-offset = <0x20>; 311 vco-offset = <0x14>; 312 clocks = <&xtal24mhz>; 313 }; 314 oscclk3: clock-controller@18 { 315 compatible = "arm,syscon-icst307"; 316 reg = <0x18 0x04>; 317 #clock-cells = <0>; 318 lock-offset = <0x20>; 319 vco-offset = <0x18>; 320 clocks = <&xtal24mhz>; 321 }; 322 oscclk4: clock-controller@1c { 323 compatible = "arm,syscon-icst307"; 324 reg = <0x1c 0x04>; 325 #clock-cells = <0>; 326 lock-offset = <0x20>; 327 vco-offset = <0x1c>; 328 clocks = <&xtal24mhz>; 329 }; 330 }; 331 332 /* Primary DevChip GIC synthesized with the CPU */ 333 intc_dc1176: interrupt-controller@10120000 { 334 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 335 #interrupt-cells = <3>; 336 #address-cells = <1>; 337 interrupt-controller; 338 reg = <0x10121000 0x1000>, 339 <0x10120000 0x100>; 340 }; 341 342 L2: cache-controller { 343 compatible = "arm,l220-cache"; 344 reg = <0x10110000 0x1000>; 345 interrupt-parent = <&intc_dc1176>; 346 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; 347 cache-unified; 348 cache-level = <2>; 349 /* 350 * Override default cache size, sets and 351 * associativity as these may be erroneously set 352 * up by boot loader(s). 353 */ 354 arm,override-auxreg; 355 cache-size = <131072>; // 128kB 356 cache-sets = <512>; 357 cache-line-size = <32>; 358 }; 359 360 pmu { 361 compatible = "arm,arm1176-pmu"; 362 interrupt-parent = <&intc_dc1176>; 363 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 364 }; 365 366 timer01: timer@10104000 { 367 compatible = "arm,sp804", "arm,primecell"; 368 reg = <0x10104000 0x1000>; 369 interrupt-parent = <&intc_dc1176>; 370 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&timclk>, <&timclk>, <&pclk>; 372 clock-names = "timer1", "timer2", "apb_pclk"; 373 }; 374 375 timer23: timer@10105000 { 376 compatible = "arm,sp804", "arm,primecell"; 377 reg = <0x10105000 0x1000>; 378 interrupt-parent = <&intc_dc1176>; 379 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 380 arm,sp804-has-irq = <1>; 381 clocks = <&timclk>, <&timclk>, <&pclk>; 382 clock-names = "timer1", "timer2", "apb_pclk"; 383 }; 384 385 pb1176_rtc: rtc@10108000 { 386 compatible = "arm,pl031", "arm,primecell"; 387 reg = <0x10108000 0x1000>; 388 interrupt-parent = <&intc_dc1176>; 389 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&pclk>; 391 clock-names = "apb_pclk"; 392 }; 393 394 pb1176_gpio0: gpio@1010a000 { 395 compatible = "arm,pl061", "arm,primecell"; 396 reg = <0x1010a000 0x1000>; 397 gpio-controller; 398 interrupt-parent = <&intc_dc1176>; 399 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 400 #gpio-cells = <2>; 401 interrupt-controller; 402 #interrupt-cells = <2>; 403 clocks = <&pclk>; 404 clock-names = "apb_pclk"; 405 }; 406 407 pb1176_ssp: spi@1010b000 { 408 compatible = "arm,pl022", "arm,primecell"; 409 reg = <0x1010b000 0x1000>; 410 interrupt-parent = <&intc_dc1176>; 411 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&sspclk>, <&pclk>; 413 clock-names = "sspclk", "apb_pclk"; 414 }; 415 416 pb1176_serial0: serial@1010c000 { 417 compatible = "arm,pl011", "arm,primecell"; 418 reg = <0x1010c000 0x1000>; 419 interrupt-parent = <&intc_dc1176>; 420 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&uartclk>, <&pclk>; 422 clock-names = "uartclk", "apb_pclk"; 423 }; 424 425 pb1176_serial1: serial@1010d000 { 426 compatible = "arm,pl011", "arm,primecell"; 427 reg = <0x1010d000 0x1000>; 428 interrupt-parent = <&intc_dc1176>; 429 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&uartclk>, <&pclk>; 431 clock-names = "uartclk", "apb_pclk"; 432 }; 433 434 pb1176_serial2: serial@1010e000 { 435 compatible = "arm,pl011", "arm,primecell"; 436 reg = <0x1010e000 0x1000>; 437 interrupt-parent = <&intc_dc1176>; 438 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&uartclk>, <&pclk>; 440 clock-names = "uartclk", "apb_pclk"; 441 }; 442 443 pb1176_serial3: serial@1010f000 { 444 compatible = "arm,pl011", "arm,primecell"; 445 reg = <0x1010f000 0x1000>; 446 interrupt-parent = <&intc_dc1176>; 447 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&uartclk>, <&pclk>; 449 clock-names = "uartclk", "apb_pclk"; 450 }; 451 452 /* Direct-mapped development chip ROM */ 453 pb1176_rom@10200000 { 454 compatible = "mtd-rom"; 455 reg = <0x10200000 0x4000>; 456 bank-width = <1>; 457 }; 458 459 clcd@10112000 { 460 compatible = "arm,pl111", "arm,primecell"; 461 reg = <0x10112000 0x1000>; 462 interrupt-parent = <&intc_dc1176>; 463 interrupt-names = "combined"; 464 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&oscclk0>, <&pclk>; 466 clock-names = "clcdclk", "apb_pclk"; 467 /* 1024x768 16bpp @65MHz works fine */ 468 max-memory-bandwidth = <95000000>; 469 470 port { 471 clcd_pads: endpoint { 472 remote-endpoint = <&vga_bridge_in>; 473 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 474 }; 475 }; 476 }; 477 }; 478 479 /* These peripherals are inside the FPGA rather than the DevChip */ 480 fpga { 481 #address-cells = <1>; 482 #size-cells = <1>; 483 compatible = "simple-bus"; 484 ranges; 485 486 i2c0: i2c@10002000 { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 compatible = "arm,versatile-i2c"; 490 reg = <0x10002000 0x1000>; 491 492 rtc@68 { 493 compatible = "dallas,ds1338"; 494 reg = <0x68>; 495 }; 496 }; 497 498 fpga_aaci: aaci@10004000 { 499 compatible = "arm,pl041", "arm,primecell"; 500 reg = <0x10004000 0x1000>; 501 interrupt-parent = <&intc_fpga1176>; 502 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&pclk>; 504 clock-names = "apb_pclk"; 505 }; 506 507 fpga_mci: mmcsd@10005000 { 508 compatible = "arm,pl18x", "arm,primecell"; 509 reg = <0x10005000 0x1000>; 510 interrupt-parent = <&intc_fpga1176>; 511 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, 512 <0 2 IRQ_TYPE_LEVEL_HIGH>; 513 /* Due to frequent FIFO overruns, use just 500 kHz */ 514 max-frequency = <500000>; 515 bus-width = <4>; 516 cap-sd-highspeed; 517 cap-mmc-highspeed; 518 clocks = <&mclk>, <&pclk>; 519 clock-names = "mclk", "apb_pclk"; 520 vmmc-supply = <&vmmc>; 521 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; 522 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; 523 }; 524 525 fpga_kmi0: kmi@10006000 { 526 compatible = "arm,pl050", "arm,primecell"; 527 reg = <0x10006000 0x1000>; 528 interrupt-parent = <&intc_fpga1176>; 529 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&kmiclk>, <&pclk>; 531 clock-names = "KMIREFCLK", "apb_pclk"; 532 }; 533 534 fpga_kmi1: kmi@10007000 { 535 compatible = "arm,pl050", "arm,primecell"; 536 reg = <0x10007000 0x1000>; 537 interrupt-parent = <&intc_fpga1176>; 538 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&kmiclk>, <&pclk>; 540 clock-names = "KMIREFCLK", "apb_pclk"; 541 }; 542 543 fpga_charlcd: charlcd@10008000 { 544 compatible = "arm,versatile-lcd"; 545 reg = <0x10008000 0x1000>; 546 interrupt-parent = <&intc_fpga1176>; 547 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&pclk>; 549 clock-names = "apb_pclk"; 550 }; 551 552 fpga_serial: serial@10009000 { 553 compatible = "arm,pl011", "arm,primecell"; 554 reg = <0x10009000 0x1000>; 555 interrupt-parent = <&intc_fpga1176>; 556 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&uartclk>, <&pclk>; 558 clock-names = "uartclk", "apb_pclk"; 559 }; 560 561 /* This GIC on the board is cascaded off the DevChip GIC */ 562 intc_fpga1176: interrupt-controller@10040000 { 563 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 564 #interrupt-cells = <3>; 565 #address-cells = <1>; 566 interrupt-controller; 567 reg = <0x10041000 0x1000>, 568 <0x10040000 0x100>; 569 interrupt-parent = <&intc_dc1176>; 570 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 571 }; 572 573 fpga_gpio0: gpio@10014000 { 574 compatible = "arm,pl061", "arm,primecell"; 575 reg = <0x10014000 0x1000>; 576 gpio-controller; 577 interrupt-parent = <&intc_fpga1176>; 578 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 579 #gpio-cells = <2>; 580 interrupt-controller; 581 #interrupt-cells = <2>; 582 clocks = <&pclk>; 583 clock-names = "apb_pclk"; 584 }; 585 586 fpga_gpio1: gpio@10015000 { 587 compatible = "arm,pl061", "arm,primecell"; 588 reg = <0x10015000 0x1000>; 589 gpio-controller; 590 interrupt-parent = <&intc_fpga1176>; 591 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 592 #gpio-cells = <2>; 593 interrupt-controller; 594 #interrupt-cells = <2>; 595 clocks = <&pclk>; 596 clock-names = "apb_pclk"; 597 }; 598 599 fpga_rtc: rtc@10017000 { 600 compatible = "arm,pl031", "arm,primecell"; 601 reg = <0x10017000 0x1000>; 602 interrupt-parent = <&intc_fpga1176>; 603 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&pclk>; 605 clock-names = "apb_pclk"; 606 }; 607 }; 608}; 609