1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller
8
9maintainers:
10  - Anson Huang <Anson.Huang@nxp.com>
11
12allOf:
13  - $ref: watchdog.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - const: fsl,imx7ulp-wdt
19      - items:
20          - const: fsl,imx8ulp-wdt
21          - const: fsl,imx7ulp-wdt
22      - const: fsl,imx93-wdt
23
24  reg:
25    maxItems: 1
26
27  interrupts:
28    maxItems: 1
29
30  clocks:
31    maxItems: 1
32
33  fsl,ext-reset-output:
34    description:
35      When set, wdog can generate external reset from the wdog_any pin.
36    type: boolean
37
38required:
39  - compatible
40  - interrupts
41  - reg
42  - clocks
43
44unevaluatedProperties: false
45
46examples:
47  - |
48    #include <dt-bindings/interrupt-controller/arm-gic.h>
49    #include <dt-bindings/clock/imx7ulp-clock.h>
50
51    watchdog@403d0000 {
52        compatible = "fsl,imx7ulp-wdt";
53        reg = <0x403d0000 0x10000>;
54        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
55        clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
56        assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
57        assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
58        timeout-sec = <40>;
59    };
60
61...
62