1This document describes the device tree bindings associated with the
2keystone network coprocessor(NetCP) driver support.
3
4The network coprocessor (NetCP) is a hardware accelerator that processes
5Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
6switch sub-module to send and receive packets. NetCP also includes a packet
7accelerator (PA) module to perform packet classification operations such as
8header matching, and packet modification operations such as checksum
9generation. NetCP can also optionally include a Security Accelerator (SA)
10capable of performing IPSec operations on ingress/egress packets.
11
12Keystone II SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which
13includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
14per Ethernet port.
15
16Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17sub-modules exist as a loadable kernel module which plug in to the netcp core.
18These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19mandatory to have the ethernet switch sub-module for the ethernet interface to
20be operational. Any other sub-module like the PA is optional.
21
22NetCP Ethernet SubSystem Layout:
23
24-----------------------------
25  NetCP subsystem(10G or 1G)
26-----------------------------
27	|
28	|-> NetCP Devices ->	|
29	|			|-> GBE/XGBE Switch
30	|			|
31	|			|-> Packet Accelerator
32	|			|
33	|			|-> Security Accelerator
34	|
35	|
36	|
37	|-> NetCP Interfaces ->	|
38				|-> Ethernet Port 0
39				|
40				|-> Ethernet Port 1
41				|
42				|-> Ethernet Port 2
43				|
44				|-> Ethernet Port 3
45
46
47NetCP subsystem properties:
48Required properties:
49- compatible:	Should be "ti,netcp-1.0"
50- clocks:	phandle to the reference clocks for the subsystem.
51- dma-id:	Navigator packet dma instance id.
52- ranges:	address range of NetCP (includes, Ethernet SS, PA and SA)
53
54Optional properties:
55- reg:		register location and the size for the following register
56		regions in the specified order.
57		- Efuse MAC address register
58- dma-coherent:	Present if dma operations are coherent
59- big-endian:	Keystone devices can be operated in a mode where the DSP is in
60		the big endian mode. In such cases enable this option. This
61		option should also be enabled if the ARM is operated in
62		big endian mode with the DSP in little endian.
63
64NetCP device properties: Device specification for NetCP sub-modules.
651Gb/10Gb (gbe/xgbe) ethernet switch sub-module specifications.
66Required properties:
67- label:	Must be "netcp-gbe" for 1Gb & "netcp-xgbe" for 10Gb.
68- compatible:	Must be one of below:-
69		"ti,netcp-gbe" for 1GbE on NetCP 1.4
70		"ti,netcp-gbe-5" for 1GbE N NetCP 1.5 (N=5)
71		"ti,netcp-gbe-9" for 1GbE N NetCP 1.5 (N=9)
72		"ti,netcp-gbe-2" for 1GbE N NetCP 1.5 (N=2)
73		"ti,netcp-xgbe" for 10 GbE
74
75- reg:		register location and the size for the following register
76		regions in the specified order.
77		- switch subsystem registers
78		- sgmii port3/4 module registers (only for NetCP 1.4)
79		- switch module registers
80		- serdes registers (only for 10G)
81
82		NetCP 1.4 ethss, here is the order
83			index #0 - switch subsystem registers
84			index #1 - sgmii port3/4 module registers
85			index #2 - switch module registers
86
87		NetCP 1.5 ethss 9 port, 5 port and 2 port
88			index #0 - switch subsystem registers
89			index #1 - switch module registers
90			index #2 - serdes registers
91
92- tx-channel:	the navigator packet dma channel name for tx.
93- tx-queue:	the navigator queue number associated with the tx dma channel.
94- interfaces:	specification for each of the switch port to be registered as a
95		network interface in the stack.
96-- slave-port:	Switch port number, 0 based numbering.
97-- link-interface:	type of link interface, supported options are
98			- mac<->mac auto negotiate mode: 0
99			- mac<->phy mode: 1
100			- mac<->mac forced mode: 2
101			- mac<->fiber mode: 3
102			- mac<->phy mode with no mdio: 4
103			- 10Gb mac<->phy mode : 10
104			- 10Gb mac<->mac forced mode : 11
105----phy-handle:	phandle to PHY device
106
107- cpts:		sub-node time synchronization (CPTS) submodule configuration
108-- clocks:	CPTS reference clock. Should point on cpts-refclk-mux clock.
109-- clock-names: should be "cpts"
110-- cpts-refclk-mux: multiplexer clock definition sub-node for CPTS reference (RFTCLK) clock
111--- #clock-cells: should be 0
112--- clocks:	list of CPTS reference (RFTCLK) clock's parents as defined in Data manual
113--- ti,mux-tbl: array of multiplexer indexes as defined in Data manual
114--- assigned-clocks: should point on cpts-refclk-mux clock
115--- assigned-clock-parents: should point on required RFTCLK clock parent to be selected
116-- cpts_clock_mult: (optional) Numerator to convert input clock ticks
117		into nanoseconds
118-- cpts_clock_shift: (optional) Denominator to convert input clock ticks into
119		nanoseconds.
120		Mult and shift will be calculated basing on CPTS
121		rftclk frequency if both cpts_clock_shift and
122		cpts_clock_mult properties are not provided.
123
124Optional properties:
125- enable-ale:	NetCP driver keeps the address learning feature in the ethernet
126		switch module disabled. This attribute is to enable the address
127		learning.
128- secondary-slave-ports:	specification for each of the switch port not be
129				registered as a network interface. NetCP driver
130				will only initialize these ports and attach PHY
131				driver to them if needed.
132
133NetCP interface properties: Interface specification for NetCP sub-modules.
134Required properties:
135- rx-channel:	the navigator packet dma channel name for rx.
136- rx-queue:	the navigator queue number associated with rx dma channel.
137- rx-pool:	specifies the number of descriptors to be used & the region-id
138		for creating the rx descriptor pool.
139- tx-pool:	specifies the number of descriptors to be used & the region-id
140		for creating the tx descriptor pool.
141- rx-queue-depth:	number of descriptors in each of the free descriptor
142			queue (FDQ) for the pktdma Rx flow. There can be at
143			present a maximum of 4 queues per Rx flow.
144- rx-buffer-size:	the buffer size for each of the Rx flow FDQ.
145- tx-completion-queue:	the navigator queue number where the descriptors are
146			recycled after Tx DMA completion.
147
148Optional properties:
149- efuse-mac:	If this is 1, then the MAC address for the interface is
150		obtained from the device efuse mac address register.
151		If this is 2, the two DWORDs occupied by the MAC address
152		are swapped.  The netcp driver will swap the two DWORDs
153		back to the proper order when this property is set to 2
154		when it obtains the mac address from efuse.
155- "netcp-device label":	phandle to the device specification for each of NetCP
156			sub-module attached to this interface.
157
158The MAC address will be determined using the optional properties defined in
159ethernet.txt and only if efuse-mac is set to 0. If all of the optional MAC
160address properties are not present, then the driver will use a random MAC
161address.
162
163Example binding:
164
165netcp: netcp@2000000 {
166	reg = <0x2620110 0x8>;
167	reg-names = "efuse";
168	compatible = "ti,netcp-1.0";
169	#address-cells = <1>;
170	#size-cells = <1>;
171	ranges  = <0 0x2000000 0xfffff>;
172	clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
173	dma-coherent;
174	/* big-endian; */
175	dma-id = <0>;
176
177	netcp-devices {
178		#address-cells = <1>;
179		#size-cells = <1>;
180		ranges;
181		gbe@90000 {
182			label = "netcp-gbe";
183			reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
184			/* enable-ale; */
185			tx-queue = <648>;
186			tx-channel = <8>;
187
188			cpts {
189				clocks = <&cpts_refclk_mux>;
190				clock-names = "cpts";
191
192				cpts_refclk_mux: cpts-refclk-mux {
193					#clock-cells = <0>;
194					clocks = <&chipclk12>, <&chipclk13>,
195						 <&timi0>, <&timi1>,
196						 <&tsipclka>, <&tsrefclk>,
197						 <&tsipclkb>;
198					ti,mux-tbl = <0x0>, <0x1>, <0x2>,
199						<0x3>, <0x4>, <0x8>, <0xC>;
200					assigned-clocks = <&cpts_refclk_mux>;
201					assigned-clock-parents = <&chipclk12>;
202				};
203			};
204
205			interfaces {
206				gbe0: interface-0 {
207					slave-port = <0>;
208					link-interface	= <4>;
209				};
210				gbe1: interface-1 {
211					slave-port = <1>;
212					link-interface	= <4>;
213				};
214			};
215
216			secondary-slave-ports {
217				port-2 {
218					slave-port = <2>;
219					link-interface	= <2>;
220				};
221				port-3 {
222					slave-port = <3>;
223					link-interface	= <2>;
224				};
225			};
226		};
227	};
228
229	netcp-interfaces {
230		interface-0 {
231			rx-channel = <22>;
232			rx-pool = <1024 12>;
233			tx-pool = <1024 12>;
234			rx-queue-depth = <128 128 0 0>;
235			rx-buffer-size = <1518 4096 0 0>;
236			rx-queue = <8704>;
237			tx-completion-queue = <8706>;
238			efuse-mac = <1>;
239			netcp-gbe = <&gbe0>;
240
241		};
242		interface-1 {
243			rx-channel = <23>;
244			rx-pool = <1024 12>;
245			tx-pool = <1024 12>;
246			rx-queue-depth = <128 128 0 0>;
247			rx-buffer-size = <1518 4096 0 0>;
248			rx-queue = <8705>;
249			tx-completion-queue = <8707>;
250			efuse-mac = <0>;
251			local-mac-address = [02 18 31 7e 3e 6f];
252			netcp-gbe = <&gbe1>;
253		};
254	};
255};
256
257CPTS board configuration - select external CPTS RFTCLK:
258
259&tsrefclk{
260	clock-frequency = <500000000>;
261};
262
263&cpts_refclk_mux {
264	assigned-clock-parents = <&tsrefclk>;
265};
266