111820Sjulian# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 211820Sjulian%YAML 1.2 311820Sjulian--- 411820Sjulian$id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml# 511820Sjulian$schema: http://devicetree.org/meta-schemas/core.yaml# 611820Sjulian 711820Sjuliantitle: Arasan SDHCI Controller 811820Sjulian 911820Sjulianmaintainers: 1011820Sjulian - Adrian Hunter <adrian.hunter@intel.com> 1111820Sjulian 1211820SjulianallOf: 1311820Sjulian - $ref: mmc-controller.yaml# 1411820Sjulian - if: 1511820Sjulian properties: 1611820Sjulian compatible: 1711820Sjulian contains: 1811820Sjulian const: arasan,sdhci-5.1 1911820Sjulian then: 2011820Sjulian required: 2111820Sjulian - phys 2211820Sjulian - phy-names 2311820Sjulian - if: 2411820Sjulian properties: 2511820Sjulian compatible: 2611820Sjulian contains: 2711820Sjulian enum: 2811820Sjulian - xlnx,zynqmp-8.9a 2911820Sjulian - xlnx,versal-8.9a 3011820Sjulian - xlnx,versal-net-emmc 3111820Sjulian then: 3211820Sjulian properties: 3311820Sjulian clock-output-names: 3411820Sjulian oneOf: 3511820Sjulian - items: 3611820Sjulian - const: clk_out_sd0 3750479Speter - const: clk_in_sd0 3811820Sjulian - items: 3911820Sjulian - const: clk_out_sd1 4011820Sjulian - const: clk_in_sd1 4111820Sjulian 4211820Sjulianproperties: 4311820Sjulian compatible: 4411820Sjulian oneOf: 4511820Sjulian - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY 4611820Sjulian - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY 4711820Sjulian - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY 4811820Sjulian - items: 4911820Sjulian - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY 5011820Sjulian - const: arasan,sdhci-5.1 5111820Sjulian description: 5211820Sjulian For this device it is strongly suggested to include 5311820Sjulian arasan,soc-ctl-syscon. 5411820Sjulian - items: 5511820Sjulian - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY 5611820Sjulian - const: arasan,sdhci-8.9a 5711820Sjulian description: 5811820Sjulian For this device it is strongly suggested to include 5911820Sjulian clock-output-names and '#clock-cells'. 6011820Sjulian - items: 6111820Sjulian - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY 6211820Sjulian - const: arasan,sdhci-8.9a 6311820Sjulian description: 6411820Sjulian For this device it is strongly suggested to include 6511820Sjulian clock-output-names and '#clock-cells'. 6611820Sjulian - const: xlnx,versal-net-emmc # Versal Net eMMC PHY 6711820Sjulian description: 6811820Sjulian For this device it is strongly suggested to include 6911820Sjulian clock-output-names and '#clock-cells'. 7011820Sjulian - items: 7111820Sjulian - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY 7211820Sjulian - const: arasan,sdhci-5.1 7311820Sjulian description: 7411820Sjulian For this device it is strongly suggested to include 7511820Sjulian arasan,soc-ctl-syscon. 7611820Sjulian - items: 7711820Sjulian - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY 7811820Sjulian - const: arasan,sdhci-5.1 7911820Sjulian description: 8045988Sjhay For this device it is strongly suggested to include 8111820Sjulian arasan,soc-ctl-syscon. 8211820Sjulian - items: 8311820Sjulian - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY 8411820Sjulian - const: arasan,sdhci-5.1 8511820Sjulian description: 8611820Sjulian For this device it is strongly suggested to include 8711820Sjulian arasan,soc-ctl-syscon. 8811820Sjulian - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller 8911820Sjulian description: 9011820Sjulian For this device it is strongly suggested to include 9115248Sjhay arasan,soc-ctl-syscon. 9211820Sjulian - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller 9311820Sjulian description: 9411820Sjulian For this device it is strongly suggested to include 9511820Sjulian arasan,soc-ctl-syscon. 9611820Sjulian 9711820Sjulian reg: 9811820Sjulian maxItems: 1 9911820Sjulian 10027244Sjhay clocks: 10127244Sjhay minItems: 2 10211820Sjulian maxItems: 3 10311820Sjulian 10427244Sjhay clock-names: 10527244Sjhay minItems: 2 10611820Sjulian items: 10711820Sjulian - const: clk_xin 108 - const: clk_ahb 109 - const: gate 110 111 interrupts: 112 maxItems: 1 113 114 phys: 115 maxItems: 1 116 117 phy-names: 118 const: phy_arasan 119 120 resets: 121 maxItems: 1 122 123 arasan,soc-ctl-syscon: 124 $ref: /schemas/types.yaml#/definitions/phandle 125 description: 126 A phandle to a syscon device (see ../mfd/syscon.txt) used to access 127 core corecfg registers. Offsets of registers in this syscon are 128 determined based on the main compatible string for the device. 129 130 clock-output-names: 131 minItems: 1 132 maxItems: 2 133 description: 134 Name of the card clock which will be exposed by this device. 135 136 '#clock-cells': 137 enum: [0, 1] 138 description: 139 With this property in place we will export one or two clocks 140 representing the Card Clock. These clocks are expected to be 141 consumed by our PHY. 142 143 xlnx,fails-without-test-cd: 144 $ref: /schemas/types.yaml#/definitions/flag 145 description: 146 When present, the controller doesn't work when the CD line is not 147 connected properly, and the line is not connected properly. 148 Test mode can be used to force the controller to function. 149 150 xlnx,int-clock-stable-broken: 151 $ref: /schemas/types.yaml#/definitions/flag 152 description: 153 When present, the controller always reports that the internal clock 154 is stable even when it is not. 155 156 xlnx,mio-bank: 157 $ref: /schemas/types.yaml#/definitions/uint32 158 enum: [0, 1, 2] 159 default: 0 160 description: 161 The MIO bank number in which the command and data lines are configured. 162 163 iommus: 164 maxItems: 1 165 166 power-domains: 167 maxItems: 1 168 169dependencies: 170 '#clock-cells': [ clock-output-names ] 171 172required: 173 - compatible 174 - reg 175 - interrupts 176 - clocks 177 - clock-names 178 179unevaluatedProperties: false 180 181examples: 182 - | 183 mmc@e0100000 { 184 compatible = "arasan,sdhci-8.9a"; 185 reg = <0xe0100000 0x1000>; 186 clock-names = "clk_xin", "clk_ahb"; 187 clocks = <&clkc 21>, <&clkc 32>; 188 interrupt-parent = <&gic>; 189 interrupts = <0 24 4>; 190 }; 191 192 - | 193 mmc@e2800000 { 194 compatible = "arasan,sdhci-5.1"; 195 reg = <0xe2800000 0x1000>; 196 clock-names = "clk_xin", "clk_ahb"; 197 clocks = <&cru 8>, <&cru 18>; 198 interrupt-parent = <&gic>; 199 interrupts = <0 24 4>; 200 phys = <&emmc_phy>; 201 phy-names = "phy_arasan"; 202 }; 203 204 - | 205 #include <dt-bindings/clock/rk3399-cru.h> 206 #include <dt-bindings/interrupt-controller/arm-gic.h> 207 #include <dt-bindings/interrupt-controller/irq.h> 208 mmc@fe330000 { 209 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 210 reg = <0xfe330000 0x10000>; 211 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 213 clock-names = "clk_xin", "clk_ahb"; 214 arasan,soc-ctl-syscon = <&grf>; 215 assigned-clocks = <&cru SCLK_EMMC>; 216 assigned-clock-rates = <200000000>; 217 clock-output-names = "emmc_cardclock"; 218 phys = <&emmc_phy>; 219 phy-names = "phy_arasan"; 220 #clock-cells = <0>; 221 }; 222 223 - | 224 mmc@ff160000 { 225 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 226 interrupt-parent = <&gic>; 227 interrupts = <0 48 4>; 228 reg = <0xff160000 0x1000>; 229 clocks = <&clk200>, <&clk200>, <&clk1200>; 230 clock-names = "clk_xin", "clk_ahb", "gate"; 231 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 232 #clock-cells = <1>; 233 clk-phase-sd-hs = <63>, <72>; 234 }; 235 236 - | 237 mmc@f1040000 { 238 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; 239 interrupt-parent = <&gic>; 240 interrupts = <0 126 4>; 241 reg = <0xf1040000 0x10000>; 242 clocks = <&clk200>, <&clk200>, <&clk1200>; 243 clock-names = "clk_xin", "clk_ahb", "gate"; 244 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 245 #clock-cells = <1>; 246 clk-phase-sd-hs = <132>, <60>; 247 }; 248 249 - | 250 #define LGM_CLK_EMMC5 251 #define LGM_CLK_NGI 252 #define LGM_GCLK_EMMC 253 mmc@ec700000 { 254 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1"; 255 reg = <0xec700000 0x300>; 256 interrupt-parent = <&ioapic1>; 257 interrupts = <44 1>; 258 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>, 259 <&cgu0 LGM_GCLK_EMMC>; 260 clock-names = "clk_xin", "clk_ahb", "gate"; 261 clock-output-names = "emmc_cardclock"; 262 #clock-cells = <0>; 263 phys = <&emmc_phy>; 264 phy-names = "phy_arasan"; 265 arasan,soc-ctl-syscon = <&sysconf>; 266 }; 267 268 - | 269 #define LGM_CLK_SDIO 270 #define LGM_GCLK_SDXC 271 mmc@ec600000 { 272 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1"; 273 reg = <0xec600000 0x300>; 274 interrupt-parent = <&ioapic1>; 275 interrupts = <43 1>; 276 clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>, 277 <&cgu0 LGM_GCLK_SDXC>; 278 clock-names = "clk_xin", "clk_ahb", "gate"; 279 clock-output-names = "sdxc_cardclock"; 280 #clock-cells = <0>; 281 phys = <&sdxc_phy>; 282 phy-names = "phy_arasan"; 283 arasan,soc-ctl-syscon = <&sysconf>; 284 }; 285 286 - | 287 #define KEEM_BAY_PSS_AUX_EMMC 288 #define KEEM_BAY_PSS_EMMC 289 mmc@33000000 { 290 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1"; 291 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 292 reg = <0x33000000 0x300>; 293 clock-names = "clk_xin", "clk_ahb"; 294 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>, 295 <&scmi_clk KEEM_BAY_PSS_EMMC>; 296 phys = <&emmc_phy>; 297 phy-names = "phy_arasan"; 298 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>; 299 assigned-clock-rates = <200000000>; 300 clock-output-names = "emmc_cardclock"; 301 #clock-cells = <0>; 302 arasan,soc-ctl-syscon = <&mmc_phy_syscon>; 303 }; 304 305 - | 306 #define KEEM_BAY_PSS_AUX_SD0 307 #define KEEM_BAY_PSS_SD0 308 mmc@31000000 { 309 compatible = "intel,keembay-sdhci-5.1-sd"; 310 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 311 reg = <0x31000000 0x300>; 312 clock-names = "clk_xin", "clk_ahb"; 313 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>, 314 <&scmi_clk KEEM_BAY_PSS_SD0>; 315 arasan,soc-ctl-syscon = <&sd0_phy_syscon>; 316 }; 317