1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arasan SDHCI Controller
8
9maintainers:
10  - Adrian Hunter <adrian.hunter@intel.com>
11
12allOf:
13  - $ref: mmc-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: arasan,sdhci-5.1
19    then:
20      required:
21        - phys
22        - phy-names
23  - if:
24      properties:
25        compatible:
26          contains:
27            enum:
28              - xlnx,zynqmp-8.9a
29              - xlnx,versal-8.9a
30              - xlnx,versal-net-emmc
31    then:
32      properties:
33        clock-output-names:
34          oneOf:
35            - items:
36                - const: clk_out_sd0
37                - const: clk_in_sd0
38            - items:
39                - const: clk_out_sd1
40                - const: clk_in_sd1
41
42properties:
43  compatible:
44    oneOf:
45      - const: arasan,sdhci-8.9a                # generic Arasan SDHCI 8.9a PHY
46      - const: arasan,sdhci-4.9a                # generic Arasan SDHCI 4.9a PHY
47      - const: arasan,sdhci-5.1                 # generic Arasan SDHCI 5.1 PHY
48      - items:
49          - const: rockchip,rk3399-sdhci-5.1    # rk3399 eMMC PHY
50          - const: arasan,sdhci-5.1
51        description:
52          For this device it is strongly suggested to include
53          arasan,soc-ctl-syscon.
54      - items:
55          - const: xlnx,zynqmp-8.9a             # ZynqMP SDHCI 8.9a PHY
56          - const: arasan,sdhci-8.9a
57        description:
58          For this device it is strongly suggested to include
59          clock-output-names and '#clock-cells'.
60      - items:
61          - const: xlnx,versal-8.9a             # Versal SDHCI 8.9a PHY
62          - const: arasan,sdhci-8.9a
63        description:
64          For this device it is strongly suggested to include
65          clock-output-names and '#clock-cells'.
66      - const: xlnx,versal-net-emmc     # Versal Net eMMC PHY
67        description:
68          For this device it is strongly suggested to include
69          clock-output-names and '#clock-cells'.
70      - items:
71          - const: intel,lgm-sdhci-5.1-emmc     # Intel LGM eMMC PHY
72          - const: arasan,sdhci-5.1
73        description:
74          For this device it is strongly suggested to include
75          arasan,soc-ctl-syscon.
76      - items:
77          - const: intel,lgm-sdhci-5.1-sdxc     # Intel LGM SDXC PHY
78          - const: arasan,sdhci-5.1
79        description:
80          For this device it is strongly suggested to include
81          arasan,soc-ctl-syscon.
82      - items:
83          - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
84          - const: arasan,sdhci-5.1
85        description:
86          For this device it is strongly suggested to include
87          arasan,soc-ctl-syscon.
88      - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
89        description:
90          For this device it is strongly suggested to include
91          arasan,soc-ctl-syscon.
92      - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
93        description:
94          For this device it is strongly suggested to include
95          arasan,soc-ctl-syscon.
96
97  reg:
98    maxItems: 1
99
100  clocks:
101    minItems: 2
102    maxItems: 3
103
104  clock-names:
105    minItems: 2
106    items:
107      - const: clk_xin
108      - const: clk_ahb
109      - const: gate
110
111  interrupts:
112    maxItems: 1
113
114  phys:
115    maxItems: 1
116
117  phy-names:
118    const: phy_arasan
119
120  resets:
121    maxItems: 1
122
123  arasan,soc-ctl-syscon:
124    $ref: /schemas/types.yaml#/definitions/phandle
125    description:
126      A phandle to a syscon device (see ../mfd/syscon.txt) used to access
127      core corecfg registers. Offsets of registers in this syscon are
128      determined based on the main compatible string for the device.
129
130  clock-output-names:
131    minItems: 1
132    maxItems: 2
133    description:
134      Name of the card clock which will be exposed by this device.
135
136  '#clock-cells':
137    enum: [0, 1]
138    description:
139      With this property in place we will export one or two clocks
140      representing the Card Clock. These clocks are expected to be
141      consumed by our PHY.
142
143  xlnx,fails-without-test-cd:
144    $ref: /schemas/types.yaml#/definitions/flag
145    description:
146      When present, the controller doesn't work when the CD line is not
147      connected properly, and the line is not connected properly.
148      Test mode can be used to force the controller to function.
149
150  xlnx,int-clock-stable-broken:
151    $ref: /schemas/types.yaml#/definitions/flag
152    description:
153      When present, the controller always reports that the internal clock
154      is stable even when it is not.
155
156  xlnx,mio-bank:
157    $ref: /schemas/types.yaml#/definitions/uint32
158    enum: [0, 1, 2]
159    default: 0
160    description:
161      The MIO bank number in which the command and data lines are configured.
162
163  iommus:
164    maxItems: 1
165
166  power-domains:
167    maxItems: 1
168
169dependencies:
170  '#clock-cells': [ clock-output-names ]
171
172required:
173  - compatible
174  - reg
175  - interrupts
176  - clocks
177  - clock-names
178
179unevaluatedProperties: false
180
181examples:
182  - |
183    mmc@e0100000 {
184          compatible = "arasan,sdhci-8.9a";
185          reg = <0xe0100000 0x1000>;
186          clock-names = "clk_xin", "clk_ahb";
187          clocks = <&clkc 21>, <&clkc 32>;
188          interrupt-parent = <&gic>;
189          interrupts = <0 24 4>;
190    };
191
192  - |
193    mmc@e2800000 {
194          compatible = "arasan,sdhci-5.1";
195          reg = <0xe2800000 0x1000>;
196          clock-names = "clk_xin", "clk_ahb";
197          clocks = <&cru 8>, <&cru 18>;
198          interrupt-parent = <&gic>;
199          interrupts = <0 24 4>;
200          phys = <&emmc_phy>;
201          phy-names = "phy_arasan";
202    };
203
204  - |
205    #include <dt-bindings/clock/rk3399-cru.h>
206    #include <dt-bindings/interrupt-controller/arm-gic.h>
207    #include <dt-bindings/interrupt-controller/irq.h>
208    mmc@fe330000 {
209          compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
210          reg = <0xfe330000 0x10000>;
211          interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
212          clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
213          clock-names = "clk_xin", "clk_ahb";
214          arasan,soc-ctl-syscon = <&grf>;
215          assigned-clocks = <&cru SCLK_EMMC>;
216          assigned-clock-rates = <200000000>;
217          clock-output-names = "emmc_cardclock";
218          phys = <&emmc_phy>;
219          phy-names = "phy_arasan";
220          #clock-cells = <0>;
221    };
222
223  - |
224    mmc@ff160000 {
225          compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
226          interrupt-parent = <&gic>;
227          interrupts = <0 48 4>;
228          reg = <0xff160000 0x1000>;
229          clocks = <&clk200>, <&clk200>, <&clk1200>;
230          clock-names = "clk_xin", "clk_ahb", "gate";
231          clock-output-names = "clk_out_sd0", "clk_in_sd0";
232          #clock-cells = <1>;
233          clk-phase-sd-hs = <63>, <72>;
234    };
235
236  - |
237    mmc@f1040000 {
238          compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
239          interrupt-parent = <&gic>;
240          interrupts = <0 126 4>;
241          reg = <0xf1040000 0x10000>;
242          clocks = <&clk200>, <&clk200>, <&clk1200>;
243          clock-names = "clk_xin", "clk_ahb", "gate";
244          clock-output-names = "clk_out_sd0", "clk_in_sd0";
245          #clock-cells = <1>;
246          clk-phase-sd-hs = <132>, <60>;
247    };
248
249  - |
250    #define LGM_CLK_EMMC5
251    #define LGM_CLK_NGI
252    #define LGM_GCLK_EMMC
253    mmc@ec700000 {
254          compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
255          reg = <0xec700000 0x300>;
256          interrupt-parent = <&ioapic1>;
257          interrupts = <44 1>;
258          clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
259                   <&cgu0 LGM_GCLK_EMMC>;
260          clock-names = "clk_xin", "clk_ahb", "gate";
261          clock-output-names = "emmc_cardclock";
262          #clock-cells = <0>;
263          phys = <&emmc_phy>;
264          phy-names = "phy_arasan";
265          arasan,soc-ctl-syscon = <&sysconf>;
266    };
267
268  - |
269    #define LGM_CLK_SDIO
270    #define LGM_GCLK_SDXC
271    mmc@ec600000 {
272          compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
273          reg = <0xec600000 0x300>;
274          interrupt-parent = <&ioapic1>;
275          interrupts = <43 1>;
276          clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
277                   <&cgu0 LGM_GCLK_SDXC>;
278          clock-names = "clk_xin", "clk_ahb", "gate";
279          clock-output-names = "sdxc_cardclock";
280          #clock-cells = <0>;
281          phys = <&sdxc_phy>;
282          phy-names = "phy_arasan";
283          arasan,soc-ctl-syscon = <&sysconf>;
284    };
285
286  - |
287    #define KEEM_BAY_PSS_AUX_EMMC
288    #define KEEM_BAY_PSS_EMMC
289    mmc@33000000 {
290          compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
291          interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
292          reg = <0x33000000 0x300>;
293          clock-names = "clk_xin", "clk_ahb";
294          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
295                   <&scmi_clk KEEM_BAY_PSS_EMMC>;
296          phys = <&emmc_phy>;
297          phy-names = "phy_arasan";
298          assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
299          assigned-clock-rates = <200000000>;
300          clock-output-names = "emmc_cardclock";
301          #clock-cells = <0>;
302          arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
303    };
304
305  - |
306    #define KEEM_BAY_PSS_AUX_SD0
307    #define KEEM_BAY_PSS_SD0
308    mmc@31000000 {
309          compatible = "intel,keembay-sdhci-5.1-sd";
310          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
311          reg = <0x31000000 0x300>;
312          clock-names = "clk_xin", "clk_ahb";
313          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
314                   <&scmi_clk KEEM_BAY_PSS_SD0>;
315          arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
316    };
317