1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/ti,ads131e08.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
8
9maintainers:
10  - Jonathan Cameron <jic23@kernel.org>
11
12description: |
13  The ADS131E0x are a family of multichannel, simultaneous sampling,
14  24-bit, delta-sigma, analog-to-digital converters (ADCs) with a
15  built-in programmable gain amplifier (PGA), internal reference
16  and an onboard oscillator.
17  The communication with ADC chip is via the SPI bus (mode 1).
18
19  https://www.ti.com/lit/ds/symlink/ads131e08.pdf
20
21properties:
22  compatible:
23    enum:
24      - ti,ads131e04
25      - ti,ads131e06
26      - ti,ads131e08
27
28  reg:
29    maxItems: 1
30
31  spi-cpha: true
32
33  clocks:
34    description: |
35      Device tree identifier to the clock source (2.048 MHz).
36      Note: clock source is selected using CLKSEL pin.
37    maxItems: 1
38
39  clock-names:
40    items:
41      - const: adc-clk
42
43  interrupts:
44    description: |
45      IRQ line for the ADC data ready.
46    maxItems: 1
47
48  vref-supply:
49    description: |
50      Optional external voltage reference. If not supplied, internal voltage
51      reference is used.
52
53  ti,vref-internal:
54    description: |
55      Select the internal voltage reference value.
56      0: 2.4V
57      1: 4.0V
58      If this field is left empty, 2.4V is selected.
59      Note: internal voltage reference is used only if vref-supply is not supplied.
60    $ref: /schemas/types.yaml#/definitions/uint32
61    enum: [0, 1]
62    default: 0
63
64  '#address-cells':
65    const: 1
66
67  '#size-cells':
68    const: 0
69
70required:
71  - compatible
72  - reg
73  - spi-cpha
74  - clocks
75  - clock-names
76  - interrupts
77
78patternProperties:
79  "^channel@([0-7])$":
80    $ref: adc.yaml
81    type: object
82    description: |
83      Represents the external channels which are connected to the ADC.
84
85    properties:
86      reg:
87        description: |
88          The channel number.
89          Up to 4 channels, numbered from 0 to 3 for ti,ads131e04.
90          Up to 6 channels, numbered from 0 to 5 for ti,ads131e06.
91          Up to 8 channels, numbered from 0 to 7 for ti,ads131e08.
92        items:
93          minimum: 0
94          maximum: 7
95
96      ti,gain:
97        description: |
98          The PGA gain value for the channel.
99          If this field is left empty, PGA gain 1 is used.
100        $ref: /schemas/types.yaml#/definitions/uint32
101        enum: [1, 2, 4, 8, 12]
102        default: 1
103
104      ti,mux:
105        description: |
106          Channel input selection(muliplexer).
107          0: Normal input.
108          1: Input shorted to (VREFP + VREFN) / 2 (for offset or noise measurements).
109          3: MVDD (for supply measurement)
110          4: Temperature sensor
111          If this field is left empty, normal input is selected.
112        $ref: /schemas/types.yaml#/definitions/uint32
113        enum: [0, 1, 3, 4]
114        default: 0
115
116    required:
117      - reg
118
119    additionalProperties: false
120
121allOf:
122  - $ref: /schemas/spi/spi-peripheral-props.yaml#
123
124unevaluatedProperties: false
125
126examples:
127  - |
128    #include <dt-bindings/interrupt-controller/irq.h>
129
130    spi {
131      #address-cells = <1>;
132      #size-cells = <0>;
133
134      adc@0 {
135        compatible = "ti,ads131e08";
136        reg = <0>;
137        spi-max-frequency = <1000000>;
138        spi-cpha;
139        clocks = <&clk2048k>;
140        clock-names = "adc-clk";
141        interrupt-parent = <&gpio5>;
142        interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
143        vref-supply = <&adc_vref>;
144
145        #address-cells = <1>;
146        #size-cells = <0>;
147
148        channel@0 {
149          reg = <0>;
150        };
151
152        channel@1 {
153          reg = <1>;
154        };
155
156        channel@2 {
157          reg = <2>;
158          ti,gain = <2>;
159        };
160
161        channel@3 {
162          reg = <3>;
163        };
164
165        channel@4 {
166          reg = <4>;
167        };
168
169        channel@5 {
170          reg = <5>;
171        };
172
173        channel@6 {
174          reg = <6>;
175        };
176
177        channel@7 {
178          reg = <7>;
179          ti,mux = <4>;
180        };
181      };
182    };
183