1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 5 * Copyright (c) 1995 Paul Kranenburg 6 * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by David Miller. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 35 * 36 * $FreeBSD$ 37 */ 38 39#ifndef _MACHINE_INSTR_H_ 40#define _MACHINE_INSTR_H_ 41 42/* 43 * Definitions for all instruction formats 44 */ 45#define IF_OP_SHIFT 30 46#define IF_OP_BITS 2 47#define IF_IMM_SHIFT 0 /* Immediate/Displacement */ 48 49/* 50 * Definitions for format 2 51 */ 52#define IF_F2_RD_SHIFT 25 53#define IF_F2_RD_BITS 5 54#define IF_F2_A_SHIFT 29 55#define IF_F2_A_BITS 1 56#define IF_F2_COND_SHIFT 25 57#define IF_F2_COND_BITS 4 58#define IF_F2_RCOND_SHIFT 25 59#define IF_F2_RCOND_BITS 3 60#define IF_F2_OP2_SHIFT 22 61#define IF_F2_OP2_BITS 3 62#define IF_F2_CC1_SHIFT 21 63#define IF_F2_CC1_BITS 1 64#define IF_F2_CC0_SHIFT 20 65#define IF_F2_CC0_BITS 1 66#define IF_F2_CC_SHIFT 20 /* CC0 and CC1 combined. */ 67#define IF_F2_CC_BITS 2 68#define IF_F2_D16HI_SHIFT 20 69#define IF_F2_D16HI_BITS 2 70#define IF_F2_P_SHIFT 19 71#define IF_F2_P_BITS 1 72#define IF_F2_RS1_SHIFT 14 73#define IF_F2_RS1_BITS 5 74 75/* 76 * Definitions for format 3 77 */ 78#define IF_F3_OP3_SHIFT 19 79#define IF_F3_OP3_BITS 6 80#define IF_F3_RD_SHIFT IF_F2_RD_SHIFT 81#define IF_F3_RD_BITS IF_F2_RD_BITS 82#define IF_F3_FCN_SHIFT 25 83#define IF_F3_FCN_BITS 5 84#define IF_F3_CC1_SHIFT 26 85#define IF_F3_CC1_BITS 1 86#define IF_F3_CC0_SHIFT 25 87#define IF_F3_CC0_BITS 1 88#define IF_F3_CC_SHIFT 25 /* CC0 and CC1 combined. */ 89#define IF_F3_CC_BITS 2 90#define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT 91#define IF_F3_RS1_BITS IF_F2_RS1_BITS 92#define IF_F3_I_SHIFT 13 93#define IF_F3_I_BITS 1 94#define IF_F3_X_SHIFT 12 95#define IF_F3_X_BITS 1 96#define IF_F3_RCOND_SHIFT 10 97#define IF_F3_RCOND_BITS 3 98#define IF_F3_IMM_ASI_SHIFT 5 99#define IF_F3_IMM_ASI_BITS 8 100#define IF_F3_OPF_SHIFT 5 101#define IF_F3_OPF_BITS 9 102#define IF_F3_CMASK_SHIFT 4 103#define IF_F3_CMASK_BITS 3 104#define IF_F3_RS2_SHIFT 0 105#define IF_F3_RS2_BITS 5 106#define IF_F3_SHCNT32_SHIFT 0 107#define IF_F3_SHCNT32_BITS 5 108#define IF_F3_SHCNT64_SHIFT 0 109#define IF_F3_SHCNT64_BITS 6 110 111/* 112 * Definitions for format 4 113 */ 114#define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT 115#define IF_F4_OP3_BITS IF_F3_OP3_BITS 116#define IF_F4_RD_SHIFT IF_F2_RD_SHIFT 117#define IF_F4_RD_BITS IF_F2_RD_BITS 118#define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT 119#define IF_F4_RS1_BITS IF_F2_RS1_BITS 120#define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */ 121#define IF_F4_TCOND_BITS IF_F2_COND_BITS 122#define IF_F4_CC2_SHIFT 18 123#define IF_F4_CC2_BITS 1 124#define IF_F4_COND_SHIFT 14 125#define IF_F4_COND_BITS 4 126#define IF_F4_I_SHIFT IF_F3_I_SHIFT 127#define IF_F4_I_BITS IF_F3_I_BITS 128#define IF_F4_OPF_CC_SHIFT 11 129#define IF_F4_OPF_CC_BITS 3 130#define IF_F4_CC1_SHIFT 12 131#define IF_F4_CC1_BITS 1 132#define IF_F4_CC0_SHIFT 11 133#define IF_F4_CC0_BITS 1 134#define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT 135#define IF_F4_RCOND_BITS IF_F3_RCOND_BITS 136#define IF_F4_OPF_LOW_SHIFT 5 137#define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT 138#define IF_F4_RS2_BITS IF_F3_RS2_BITS 139#define IF_F4_SW_TRAP_SHIFT 0 140#define IF_F4_SW_TRAP_BITS 7 141 142/* 143 * Macros to decode instructions 144 */ 145/* Extract a field */ 146#define IF_MASK(s, w) (((1 << (w)) - 1) << (s)) 147#define IF_EXTRACT(x, s, w) (((x) & IF_MASK((s), (w))) >> (s)) 148#define IF_DECODE(x, f) \ 149 IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 150 151/* Sign-extend a field of width W */ 152#define IF_SEXT(x, w) \ 153 (((x) & (1L << ((w) - 1))) != 0 ? \ 154 (-1L - ((x) ^ ((1L << (w)) - 1))) : (x)) 155 156#if 0 157/* 158 * The following C variant is from db_disassemble.c, and surely faster, but it 159 * relies on behaviour that is undefined by the C standard (>> in conjunction 160 * with signed negative arguments). 161 */ 162#define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w)) 163/* Assembler version of the above */ 164#define IF_SEXT(v, w) \ 165 { u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" : 166 "=r" (t) : "r" (v) : "i" (64 - w)); t)} 167#endif 168 169/* All instruction formats */ 170#define IF_OP(i) IF_DECODE(i, OP) 171 172/* Instruction format 2 */ 173#define IF_F2_RD(i) IF_DECODE((i), F2_RD) 174#define IF_F2_A(i) IF_DECODE((i), F2_A) 175#define IF_F2_COND(i) IF_DECODE((i), F2_COND) 176#define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND) 177#define IF_F2_OP2(i) IF_DECODE((i), F2_OP2) 178#define IF_F2_CC1(i) IF_DECODE((i), F2_CC1) 179#define IF_F2_CC0(i) IF_DECODE((i), F2_CC0) 180#define IF_F2_CC(i) IF_DECODE((i), F2_CC) 181#define IF_F2_D16HI(i) IF_DECODE((i), F2_D16HI) 182#define IF_F2_P(i) IF_DECODE((i), F2_P) 183#define IF_F2_RS1(i) IF_DECODE((i), F2_RS1) 184 185/* Instruction format 3 */ 186#define IF_F3_OP3(i) IF_DECODE((i), F3_OP3) 187#define IF_F3_RD(i) IF_F2_RD((i)) 188#define IF_F3_FCN(i) IF_DECODE((i), F3_FCN) 189#define IF_F3_CC1(i) IF_DECODE((i), F3_CC1) 190#define IF_F3_CC0(i) IF_DECODE((i), F3_CC0) 191#define IF_F3_CC(i) IF_DECODE((i), F3_CC) 192#define IF_F3_RS1(i) IF_F2_RS1((i)) 193#define IF_F3_I(i) IF_DECODE((i), F3_I) 194#define IF_F3_X(i) IF_DECODE((i), F3_X) 195#define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND) 196#define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI) 197#define IF_F3_OPF(i) IF_DECODE((i), F3_OPF) 198#define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK) 199#define IF_F3_RS2(i) IF_DECODE((i), F3_RS2) 200#define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32) 201#define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64) 202 203/* Instruction format 4 */ 204#define IF_F4_OP3(i) IF_F3_OP3((i)) 205#define IF_F4_RD(i) IF_F3_RD((i)) 206#define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND) 207#define IF_F4_RS1(i) IF_F3_RS1((i)) 208#define IF_F4_CC2(i) IF_DECODE((i), F4_CC2) 209#define IF_F4_COND(i) IF_DECODE((i), F4_COND) 210#define IF_F4_I(i) IF_F3_I((i)) 211#define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC) 212#define IF_F4_RCOND(i) IF_F3_RCOND((i)) 213#define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w)) 214#define IF_F4_RS2(i) IF_F3_RS2((i)) 215#define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP) 216 217/* Extract an immediate from an instruction, with an without sign extension */ 218#define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w)) 219#define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); }) 220 221/* 222 * Macros to encode instructions 223 */ 224#define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s)) 225#define IF_ENCODE(x, f) \ 226 IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 227 228/* All instruction formats */ 229#define EIF_OP(x) IF_ENCODE((x), OP) 230 231/* Instruction format 2 */ 232#define EIF_F2_RD(x) IF_ENCODE((x), F2_RD) 233#define EIF_F2_A(x) IF_ENCODE((x), F2_A) 234#define EIF_F2_COND(x) IF_ENCODE((x), F2_COND) 235#define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND) 236#define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2) 237#define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1) 238#define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0) 239#define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI) 240#define EIF_F2_P(x) IF_ENCODE((x), F2_P) 241#define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1) 242 243/* Instruction format 3 */ 244#define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3) 245#define EIF_F3_RD(x) EIF_F2_RD((x)) 246#define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN) 247#define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1) 248#define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0) 249#define EIF_F3_RS1(x) EIF_F2_RS1((x)) 250#define EIF_F3_I(x) IF_ENCODE((x), F3_I) 251#define EIF_F3_X(x) IF_ENCODE((x), F3_X) 252#define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND) 253#define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI) 254#define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF) 255#define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK) 256#define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2) 257#define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32) 258#define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64) 259 260/* Instruction format 4 */ 261#define EIF_F4_OP3(x) EIF_F3_OP3((x)) 262#define EIF_F4_RD(x) EIF_F2_RD((x)) 263#define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND) 264#define EIF_F4_RS1(x) EIF_F2_RS1((x)) 265#define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2) 266#define EIF_F4_COND(x) IF_ENCODE((x), F4_COND) 267#define EIF_F4_I(x) EIF_F3_I((x)) 268#define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC) 269#define EIF_F4_RCOND(x) EIF_F3_RCOND((x)) 270#define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w)) 271#define EIF_F4_RS2(x) EIF_F3_RS2((x)) 272#define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP) 273 274/* Immediates */ 275#define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w)) 276#define EIF_SIMM(x, w) IF_EIMM((x), (w)) 277 278/* 279 * OP field values (specifying the instruction format) 280 */ 281#define IOP_FORM2 0x00 /* Format 2: sethi, branches */ 282#define IOP_CALL 0x01 /* Format 1: call */ 283#define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */ 284#define IOP_LDST 0x03 /* Format 4: loads and stores */ 285 286/* 287 * OP2/OP3 values (specifying the actual instruction) 288 */ 289/* OP2 values for format 2 (OP = 0) */ 290#define INS0_ILLTRAP 0x00 291#define INS0_BPcc 0x01 292#define INS0_Bicc 0x02 293#define INS0_BPr 0x03 294#define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */ 295#define INS0_FBPfcc 0x05 296#define INS0_FBfcc 0x06 297/* undefined 0x07 */ 298 299/* OP3 values for Format 3 and 4 (OP = 2) */ 300#define INS2_ADD 0x00 301#define INS2_AND 0x01 302#define INS2_OR 0x02 303#define INS2_XOR 0x03 304#define INS2_SUB 0x04 305#define INS2_ANDN 0x05 306#define INS2_ORN 0x06 307#define INS2_XNOR 0x07 308#define INS2_ADDC 0x08 309#define INS2_MULX 0x09 310#define INS2_UMUL 0x0a 311#define INS2_SMUL 0x0b 312#define INS2_SUBC 0x0c 313#define INS2_UDIVX 0x0d 314#define INS2_UDIV 0x0e 315#define INS2_SDIV 0x0f 316#define INS2_ADDcc 0x10 317#define INS2_ANDcc 0x11 318#define INS2_ORcc 0x12 319#define INS2_XORcc 0x13 320#define INS2_SUBcc 0x14 321#define INS2_ANDNcc 0x15 322#define INS2_ORNcc 0x16 323#define INS2_XNORcc 0x17 324#define INS2_ADDCcc 0x18 325/* undefined 0x19 */ 326#define INS2_UMULcc 0x1a 327#define INS2_SMULcc 0x1b 328#define INS2_SUBCcc 0x1c 329/* undefined 0x1d */ 330#define INS2_UDIVcc 0x1e 331#define INS2_SDIVcc 0x1f 332#define INS2_TADDcc 0x20 333#define INS2_TSUBcc 0x21 334#define INS2_TADDccTV 0x22 335#define INS2_TSUBccTV 0x23 336#define INS2_MULScc 0x24 337#define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */ 338#define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */ 339#define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */ 340#define INS2_RD 0x28 /* and MEMBAR, STBAR */ 341/* undefined 0x29 */ 342#define INS2_RDPR 0x2a 343#define INS2_FLUSHW 0x2b 344#define INS2_MOVcc 0x2c 345#define INS2_SDIVX 0x2d 346#define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */ 347#define INS2_MOVr 0x2f 348#define INS2_WR 0x30 /* and SIR */ 349#define INS2_SV_RSTR 0x31 /* saved, restored */ 350#define INS2_WRPR 0x32 351/* undefined 0x33 */ 352#define INS2_FPop1 0x34 /* further encoded in opf field */ 353#define INS2_FPop2 0x35 /* further encoded in opf field */ 354#define INS2_IMPLDEP1 0x36 355#define INS2_IMPLDEP2 0x37 356#define INS2_JMPL 0x38 357#define INS2_RETURN 0x39 358#define INS2_Tcc 0x3a 359#define INS2_FLUSH 0x3b 360#define INS2_SAVE 0x3c 361#define INS2_RESTORE 0x3d 362#define INS2_DONE_RETR 0x3e /* done, retry */ 363/* undefined 0x3f */ 364 365/* OP3 values for format 3 (OP = 3) */ 366#define INS3_LDUW 0x00 367#define INS3_LDUB 0x01 368#define INS3_LDUH 0x02 369#define INS3_LDD 0x03 370#define INS3_STW 0x04 371#define INS3_STB 0x05 372#define INS3_STH 0x06 373#define INS3_STD 0x07 374#define INS3_LDSW 0x08 375#define INS3_LDSB 0x09 376#define INS3_LDSH 0x0a 377#define INS3_LDX 0x0b 378/* undefined 0x0c */ 379#define INS3_LDSTUB 0x0d 380#define INS3_STX 0x0e 381#define INS3_SWAP 0x0f 382#define INS3_LDUWA 0x10 383#define INS3_LDUBA 0x11 384#define INS3_LDUHA 0x12 385#define INS3_LDDA 0x13 386#define INS3_STWA 0x14 387#define INS3_STBA 0x15 388#define INS3_STHA 0x16 389#define INS3_STDA 0x17 390#define INS3_LDSWA 0x18 391#define INS3_LDSBA 0x19 392#define INS3_LDSHA 0x1a 393#define INS3_LDXA 0x1b 394/* undefined 0x1c */ 395#define INS3_LDSTUBA 0x1d 396#define INS3_STXA 0x1e 397#define INS3_SWAPA 0x1f 398#define INS3_LDF 0x20 399#define INS3_LDFSR 0x21 /* and LDXFSR */ 400#define INS3_LDQF 0x22 401#define INS3_LDDF 0x23 402#define INS3_STF 0x24 403#define INS3_STFSR 0x25 /* and STXFSR */ 404#define INS3_STQF 0x26 405#define INS3_STDF 0x27 406/* undefined 0x28 - 0x2c */ 407#define INS3_PREFETCH 0x2d 408/* undefined 0x2e - 0x2f */ 409#define INS3_LDFA 0x30 410/* undefined 0x31 */ 411#define INS3_LDQFA 0x32 412#define INS3_LDDFA 0x33 413#define INS3_STFA 0x34 414/* undefined 0x35 */ 415#define INS3_STQFA 0x36 416#define INS3_STDFA 0x37 417/* undefined 0x38 - 0x3b */ 418#define INS3_CASA 0x39 419#define INS3_PREFETCHA 0x3a 420#define INS3_CASXA 0x3b 421 422/* 423 * OPF values (floating point instructions, IMPLDEP) 424 */ 425/* 426 * These values are or'ed to the FPop values to get the instructions. 427 * They describe the operand type(s). 428 */ 429#define INSFP_i 0x000 /* 32-bit int */ 430#define INSFP_s 0x001 /* 32-bit single */ 431#define INSFP_d 0x002 /* 64-bit double */ 432#define INSFP_q 0x003 /* 128-bit quad */ 433/* FPop1. The comments give the types for which this instruction is defined. */ 434#define INSFP1_FMOV 0x000 /* s, d, q */ 435#define INSFP1_FNEG 0x004 /* s, d, q */ 436#define INSFP1_FABS 0x008 /* s, d, q */ 437#define INSFP1_FSQRT 0x028 /* s, d, q */ 438#define INSFP1_FADD 0x040 /* s, d, q */ 439#define INSFP1_FSUB 0x044 /* s, d, q */ 440#define INSFP1_FMUL 0x048 /* s, d, q */ 441#define INSFP1_FDIV 0x04c /* s, d, q */ 442#define INSFP1_FsMULd 0x068 /* s */ 443#define INSFP1_FdMULq 0x06c /* d */ 444#define INSFP1_FTOx 0x080 /* s, d, q */ 445#define INSFP1_FxTOs 0x084 /* special: i only */ 446#define INSFP1_FxTOd 0x088 /* special: i only */ 447#define INSFP1_FxTOq 0x08c /* special: i only */ 448#define INSFP1_FTOs 0x0c4 /* i, d, q */ 449#define INSFP1_FTOd 0x0c8 /* i, s, q */ 450#define INSFP1_FTOq 0x0cc /* i, s, d */ 451#define INSFP1_FTOi 0x0d0 /* i, s, d */ 452 453/* FPop2 */ 454#define INSFP2_FMOV_CCMUL 0x40 455#define INSFP2_FMOV_CCOFFS 0x00 456/* Use the IFCC_* constants for cc. Operand types: s, d, q */ 457#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS) 458#define INSFP2_FMOV_RCMUL 0x20 459#define INSFP2_FMOV_RCOFFS 0x04 460/* Use the IRCOND_* constants for rc. Operand types: s, d, q */ 461#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS) 462#define INSFP2_FCMP 0x050 /* s, d, q */ 463#define INSFP2_FCMPE 0x054 /* s, d, q */ 464 465/* Decode 5-bit register field into 6-bit number (for doubles and quads). */ 466#define INSFPdq_RN(rn) (((rn) & ~1) | (((rn) & 1) << 5)) 467 468/* IMPLDEP1 for Sun UltraSparc */ 469#define IIDP1_EDGE8 0x00 470#define IIDP1_EDGE8N 0x01 /* US-III */ 471#define IIDP1_EDGE8L 0x02 472#define IIDP1_EDGE8LN 0x03 /* US-III */ 473#define IIDP1_EDGE16 0x04 474#define IIDP1_EDGE16N 0x05 /* US-III */ 475#define IIDP1_EDGE16L 0x06 476#define IIDP1_EDGE16LN 0x07 /* US-III */ 477#define IIDP1_EDGE32 0x08 478#define IIDP1_EDGE32N 0x09 /* US-III */ 479#define IIDP1_EDGE32L 0x0a 480#define IIDP1_EDGE32LN 0x0b /* US-III */ 481#define IIDP1_ARRAY8 0x10 482#define IIDP1_ARRAY16 0x12 483#define IIDP1_ARRAY32 0x14 484#define IIDP1_ALIGNADDRESS 0x18 485#define IIDP1_BMASK 0x19 /* US-III */ 486#define IIDP1_ALIGNADDRESS_L 0x1a 487#define IIDP1_FCMPLE16 0x20 488#define IIDP1_FCMPNE16 0x22 489#define IIDP1_FCMPLE32 0x24 490#define IIDP1_FCMPNE32 0x26 491#define IIDP1_FCMPGT16 0x28 492#define IIDP1_FCMPEQ16 0x2a 493#define IIDP1_FCMPGT32 0x2c 494#define IIDP1_FCMPEQ32 0x2e 495#define IIDP1_FMUL8x16 0x31 496#define IIDP1_FMUL8x16AU 0x33 497#define IIDP1_FMUL8X16AL 0x35 498#define IIDP1_FMUL8SUx16 0x36 499#define IIDP1_FMUL8ULx16 0x37 500#define IIDP1_FMULD8SUx16 0x38 501#define IIDP1_FMULD8ULx16 0x39 502#define IIDP1_FPACK32 0x3a 503#define IIDP1_FPACK16 0x3b 504#define IIDP1_FPACKFIX 0x3d 505#define IIDP1_PDIST 0x3e 506#define IIDP1_FALIGNDATA 0x48 507#define IIDP1_FPMERGE 0x4b 508#define IIDP1_BSHUFFLE 0x4c /* US-III */ 509#define IIDP1_FEXPAND 0x4d 510#define IIDP1_FPADD16 0x50 511#define IIDP1_FPADD16S 0x51 512#define IIDP1_FPADD32 0x52 513#define IIDP1_FPADD32S 0x53 514#define IIDP1_SUB16 0x54 515#define IIDP1_SUB16S 0x55 516#define IIDP1_SUB32 0x56 517#define IIDP1_SUB32S 0x57 518#define IIDP1_FZERO 0x60 519#define IIDP1_FZEROS 0x61 520#define IIDP1_FNOR 0x62 521#define IIDP1_FNORS 0x63 522#define IIDP1_FANDNOT2 0x64 523#define IIDP1_FANDNOT2S 0x65 524#define IIDP1_NOT2 0x66 525#define IIDP1_NOT2S 0x67 526#define IIDP1_FANDNOT1 0x68 527#define IIDP1_FANDNOT1S 0x69 528#define IIDP1_FNOT1 0x6a 529#define IIDP1_FNOT1S 0x6b 530#define IIDP1_FXOR 0x6c 531#define IIDP1_FXORS 0x6d 532#define IIDP1_FNAND 0x6e 533#define IIDP1_FNANDS 0x6f 534#define IIDP1_FAND 0x70 535#define IIDP1_FANDS 0x71 536#define IIDP1_FXNOR 0x72 537#define IIDP1_FXNORS 0x73 538#define IIDP1_FSRC1 0x74 539#define IIDP1_FSRC1S 0x75 540#define IIDP1_FORNOT2 0x76 541#define IIDP1_FORNOT2S 0x77 542#define IIDP1_FSRC2 0x78 543#define IIDP1_FSRC2S 0x79 544#define IIDP1_FORNOT1 0x7a 545#define IIDP1_FORNOT1S 0x7b 546#define IIDP1_FOR 0x7c 547#define IIDP1_FORS 0x7d 548#define IIDP1_FONE 0x7e 549#define IIDP1_FONES 0x7f 550#define IIDP1_SHUTDOWN 0x80 551#define IIDP1_SIAM 0x81 /* US-III */ 552 553/* 554 * Instruction modifiers 555 */ 556/* cond values for integer ccr's */ 557#define IICOND_N 0x00 558#define IICOND_E 0x01 559#define IICOND_LE 0x02 560#define IICOND_L 0x03 561#define IICOND_LEU 0x04 562#define IICOND_CS 0x05 563#define IICOND_NEG 0x06 564#define IICOND_VS 0x07 565#define IICOND_A 0x08 566#define IICOND_NE 0x09 567#define IICOND_G 0x0a 568#define IICOND_GE 0x0b 569#define IICOND_GU 0x0c 570#define IICOND_CC 0x0d 571#define IICOND_POS 0x0e 572#define IICOND_VC 0x0f 573 574/* cond values for fp ccr's */ 575#define IFCOND_N 0x00 576#define IFCOND_NE 0x01 577#define IFCOND_LG 0x02 578#define IFCOND_UL 0x03 579#define IFCOND_L 0x04 580#define IFCOND_UG 0x05 581#define IFCOND_G 0x06 582#define IFCOND_U 0x07 583#define IFCOND_A 0x08 584#define IFCOND_E 0x09 585#define IFCOND_UE 0x0a 586#define IFCOND_GE 0x0b 587#define IFCOND_UGE 0x0c 588#define IFCOND_LE 0x0d 589#define IFCOND_ULE 0x0e 590#define IFCOND_O 0x0f 591 592/* rcond values for BPr, MOVr, FMOVr */ 593#define IRCOND_Z 0x01 594#define IRCOND_LEZ 0x02 595#define IRCOND_LZ 0x03 596#define IRCOND_NZ 0x05 597#define IRCOND_GZ 0x06 598#define IRCOND_GEZ 0x07 599 600/* cc values for MOVcc and FMOVcc */ 601#define IFCC_ICC 0x04 602#define IFCC_XCC 0x06 603/* if true, the lower 2 bits are the fcc number */ 604#define IFCC_FCC(c) ((c) & 3) 605#define IFCC_GET_FCC(c) ((c) & 3) 606#define IFCC_ISFCC(c) (((c) & 4) == 0) 607 608/* cc values for BPc and Tcc */ 609#define IBCC_ICC 0x00 610#define IBCC_XCC 0x02 611 612/* 613 * Integer registers 614 */ 615#define IREG_G0 0x00 616#define IREG_O0 0x08 617#define IREG_L0 0x10 618#define IREQ_I0 0x18 619 620#endif /* !_MACHINE_INSTR_H_ */ 621