1/*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include "opt_wlan.h" 31 32#include <sys/param.h> 33#include <sys/lock.h> 34#include <sys/mutex.h> 35#include <sys/mbuf.h> 36#include <sys/kernel.h> 37#include <sys/socket.h> 38#include <sys/systm.h> 39#include <sys/malloc.h> 40#include <sys/queue.h> 41#include <sys/taskqueue.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/linker.h> 45 46#include <net/if.h> 47#include <net/ethernet.h> 48#include <net/if_media.h> 49 50#include <net80211/ieee80211_var.h> 51#include <net80211/ieee80211_radiotap.h> 52 53#include <dev/rtwn/if_rtwnreg.h> 54#include <dev/rtwn/if_rtwnvar.h> 55 56#include <dev/rtwn/rtl8812a/r12a_var.h> 57 58#include <dev/rtwn/rtl8812a/usb/r12au.h> 59#include <dev/rtwn/rtl8812a/usb/r12au_reg.h> 60 61void 62r12au_init_rx_agg(struct rtwn_softc *sc) 63{ 64 struct r12a_softc *rs = sc->sc_priv; 65 66 /* Rx aggregation (USB). */ 67 rtwn_write_2(sc, R92C_RXDMA_AGG_PG_TH, 68 rs->ac_usb_dma_size | (rs->ac_usb_dma_time << 8)); 69 rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0, 70 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 71} 72 73void 74r12au_init_burstlen_usb2(struct rtwn_softc *sc) 75{ 76 const uint8_t dma_count = R12A_DMA_MODE | SM(R12A_BURST_CNT, 3); 77 78 if ((rtwn_read_1(sc, R92C_USB_INFO) & 0x30) == 0) { 79 /* Set burst packet length to 512 B. */ 80 rtwn_setbits_1(sc, R12A_RXDMA_PRO, R12A_BURST_SZ_M, 81 dma_count | SM(R12A_BURST_SZ, R12A_BURST_SZ_USB2)); 82 } else { 83 /* Set burst packet length to 64 B. */ 84 rtwn_setbits_1(sc, R12A_RXDMA_PRO, R12A_BURST_SZ_M, 85 dma_count | SM(R12A_BURST_SZ, R12A_BURST_SZ_USB1)); 86 } 87} 88 89void 90r12au_init_burstlen(struct rtwn_softc *sc) 91{ 92 const uint8_t dma_count = R12A_DMA_MODE | SM(R12A_BURST_CNT, 3); 93 94 if (rtwn_read_1(sc, R92C_TYPE_ID + 3) & 0x80) 95 r12au_init_burstlen_usb2(sc); 96 else { /* USB 3.0 */ 97 /* Set burst packet length to 1 KB. */ 98 rtwn_setbits_1(sc, R12A_RXDMA_PRO, R12A_BURST_SZ_M, 99 dma_count | SM(R12A_BURST_SZ, R12A_BURST_SZ_USB3)); 100 101 rtwn_setbits_1(sc, 0xf008, 0x18, 0); 102 } 103} 104 105static void 106r12au_arfb_init(struct rtwn_softc *sc) 107{ 108 /* ARFB table 9 for 11ac 5G 2SS. */ 109 rtwn_write_4(sc, R12A_ARFR_5G(0), 0x00000010); 110 rtwn_write_4(sc, R12A_ARFR_5G(0) + 4, 0xfffff000); 111 112 /* ARFB table 10 for 11ac 5G 1SS. */ 113 rtwn_write_4(sc, R12A_ARFR_5G(1), 0x00000010); 114 rtwn_write_4(sc, R12A_ARFR_5G(1) + 4, 0x003ff000); 115 116 /* ARFB table 11 for 11ac 2G 1SS. */ 117 rtwn_write_4(sc, R12A_ARFR_2G(0), 0x00000015); 118 rtwn_write_4(sc, R12A_ARFR_2G(0) + 4, 0x003ff000); 119 120 /* ARFB table 12 for 11ac 2G 2SS. */ 121 rtwn_write_4(sc, R12A_ARFR_2G(1), 0x00000015); 122 rtwn_write_4(sc, R12A_ARFR_2G(1) + 4, 0xffcff000); 123} 124 125void 126r12au_init_ampdu_fwhw(struct rtwn_softc *sc) 127{ 128 rtwn_setbits_1(sc, R92C_FWHW_TXQ_CTRL, 129 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW, 0); 130} 131 132void 133r12au_init_ampdu(struct rtwn_softc *sc) 134{ 135 struct r12a_softc *rs = sc->sc_priv; 136 137 /* Rx interval (USB3). */ 138 rtwn_write_1(sc, 0xf050, 0x01); 139 140 /* burst length = 4 */ 141 rtwn_write_2(sc, R92C_RXDMA_STATUS, 0x7400); 142 143 rtwn_write_1(sc, R92C_RXDMA_STATUS + 1, 0xf5); 144 145 /* Setup AMPDU aggregation. */ 146 rtwn_write_1(sc, R12A_AMPDU_MAX_TIME, rs->ampdu_max_time); 147 rtwn_write_4(sc, R12A_AMPDU_MAX_LENGTH, 0xffffffff); 148 149 /* 80 MHz clock (again?) */ 150 rtwn_write_1(sc, R92C_USTIME_TSF, 0x50); 151 rtwn_write_1(sc, R92C_USTIME_EDCA, 0x50); 152 153 rtwn_r12a_init_burstlen(sc); 154 155 /* Enable single packet AMPDU. */ 156 rtwn_setbits_1(sc, R12A_HT_SINGLE_AMPDU, 0, 157 R12A_HT_SINGLE_AMPDU_PKT_ENA); 158 159 /* 11K packet length for VHT. */ 160 rtwn_write_1(sc, R92C_RX_PKT_LIMIT, 0x18); 161 162 rtwn_write_1(sc, R92C_PIFS, 0); 163 164 rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x1f1f); 165 166 rtwn_r12a_init_ampdu_fwhw(sc); 167 168 /* Do not reset MAC. */ 169 rtwn_setbits_1(sc, R92C_RSV_CTRL, 0, 0x60); 170 171 r12au_arfb_init(sc); 172} 173 174void 175r12au_post_init(struct rtwn_softc *sc) 176{ 177 178 /* Setup RTS BW (equal to data BW). */ 179 rtwn_setbits_1(sc, R92C_QUEUE_CTRL, 0x08, 0); 180 181 rtwn_write_1(sc, R12A_EARLY_MODE_CONTROL + 3, 0x01); 182 183 /* Reset USB mode switch setting. */ 184 rtwn_write_1(sc, R12A_SDIO_CTRL, 0); 185 rtwn_write_1(sc, R92C_ACLK_MON, 0); 186 187 rtwn_write_1(sc, R92C_USB_HRPWM, 0); 188 189#ifndef RTWN_WITHOUT_UCODE 190 if (sc->sc_flags & RTWN_FW_LOADED) { 191 if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) { 192 /* TODO: implement */ 193 sc->sc_ratectl = RTWN_RATECTL_NET80211; 194 } else 195 sc->sc_ratectl = sc->sc_ratectl_sysctl; 196 } else 197#endif 198 sc->sc_ratectl = RTWN_RATECTL_NONE; 199} 200