1/*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include "opt_wlan.h" 31 32#include <sys/param.h> 33#include <sys/lock.h> 34#include <sys/mutex.h> 35#include <sys/mbuf.h> 36#include <sys/kernel.h> 37#include <sys/socket.h> 38#include <sys/systm.h> 39#include <sys/malloc.h> 40#include <sys/queue.h> 41#include <sys/taskqueue.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/linker.h> 45 46#include <net/if.h> 47#include <net/ethernet.h> 48#include <net/if_media.h> 49 50#include <net80211/ieee80211_var.h> 51#include <net80211/ieee80211_radiotap.h> 52 53#include <dev/rtwn/if_rtwnreg.h> 54#include <dev/rtwn/if_rtwnvar.h> 55 56#include <dev/rtwn/if_rtwn_debug.h> 57 58#include <dev/rtwn/rtl8812a/r12a.h> 59#include <dev/rtwn/rtl8812a/r12a_priv.h> 60#include <dev/rtwn/rtl8812a/r12a_reg.h> 61#include <dev/rtwn/rtl8812a/r12a_var.h> 62 63void 64r12a_lc_calib(struct rtwn_softc *sc) 65{ 66 uint32_t chnlbw; 67 uint8_t txmode; 68 69 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 70 "%s: LC calibration started\n", __func__); 71 72 txmode = rtwn_read_1(sc, R12A_SINGLETONE_CONT_TX + 2); 73 74 if ((txmode & 0x07) != 0) { 75 /* Disable all continuous Tx. */ 76 /* 77 * Skipped because BB turns off continuous Tx until 78 * next packet comes in. 79 */ 80 } else { 81 /* Block all Tx queues. */ 82 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 83 } 84 85 /* Enter LCK mode. */ 86 rtwn_rf_setbits(sc, 0, R12A_RF_LCK, 0, R12A_RF_LCK_MODE); 87 88 /* Start calibration. */ 89 chnlbw = rtwn_rf_read(sc, 0, R92C_RF_CHNLBW); 90 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, chnlbw | R92C_RF_CHNLBW_LCSTART); 91 92 /* Give calibration the time to complete. */ 93 rtwn_delay(sc, 150000); /* 150 ms */ 94 95 /* Leave LCK mode. */ 96 rtwn_rf_setbits(sc, 0, R12A_RF_LCK, R12A_RF_LCK_MODE, 0); 97 98 /* Restore configuration. */ 99 if ((txmode & 0x07) != 0) { 100 /* Continuous Tx case. */ 101 /* 102 * Skipped because BB turns off continuous Tx until 103 * next packet comes in. 104 */ 105 } else { 106 /* Unblock all Tx queues. */ 107 rtwn_write_1(sc, R92C_TXPAUSE, 0); 108 } 109 110 /* Recover channel number. */ 111 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, chnlbw); 112 113 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 114 "%s: LC calibration finished\n", __func__); 115} 116 117#ifndef RTWN_WITHOUT_UCODE 118int 119r12a_iq_calib_fw_supported(struct rtwn_softc *sc) 120{ 121 if (sc->fwver == 0x19) 122 return (1); 123 124 return (0); 125} 126#endif 127 128void 129r12a_save_bb_afe_vals(struct rtwn_softc *sc, uint32_t vals[], 130 const uint16_t regs[], int size) 131{ 132 int i; 133 134 /* Select page C. */ 135 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 136 137 for (i = 0; i < size; i++) 138 vals[i] = rtwn_bb_read(sc, regs[i]); 139} 140 141void 142r12a_restore_bb_afe_vals(struct rtwn_softc *sc, uint32_t vals[], 143 const uint16_t regs[], int size) 144{ 145 int i; 146 147 /* Select page C. */ 148 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 149 150 for (i = 0; i < size; i++) 151 rtwn_bb_write(sc, regs[i], vals[i]); 152} 153 154void 155r12a_save_rf_vals(struct rtwn_softc *sc, uint32_t vals[], 156 const uint8_t regs[], int size) 157{ 158 int c, i; 159 160 /* Select page C. */ 161 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 162 163 for (c = 0; c < sc->nrxchains; c++) 164 for (i = 0; i < size; i++) 165 vals[c * size + i] = rtwn_rf_read(sc, c, regs[i]); 166} 167 168void 169r12a_restore_rf_vals(struct rtwn_softc *sc, uint32_t vals[], 170 const uint8_t regs[], int size) 171{ 172 int c, i; 173 174 /* Select page C. */ 175 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 176 177 for (c = 0; c < sc->nrxchains; c++) 178 for (i = 0; i < size; i++) 179 rtwn_rf_write(sc, c, regs[i], vals[c * size + i]); 180} 181 182#ifdef RTWN_TODO 183static void 184r12a_iq_tx(struct rtwn_softc *sc) 185{ 186 /* TODO */ 187} 188 189static void 190r12a_iq_config_mac(struct rtwn_softc *sc) 191{ 192 193 /* Select page C. */ 194 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x80000000, 0); 195 rtwn_write_1(sc, R92C_TXPAUSE, 196 R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | R92C_TX_QUEUE_HIGH); 197 /* BCN_CTRL & BCN_CTRL1 */ 198 rtwn_setbits_1(sc, R92C_BCN_CTRL(0), R92C_BCN_CTRL_EN_BCN, 0); 199 rtwn_setbits_1(sc, R92C_BCN_CTRL(1), R92C_BCN_CTRL_EN_BCN, 0); 200 /* Rx ant off */ 201 rtwn_write_1(sc, R12A_OFDMCCK_EN, 0); 202 /* CCA off */ 203 rtwn_bb_setbits(sc, R12A_CCA_ON_SEC, 0x03, 0x0c); 204 /* CCK RX Path off */ 205 rtwn_write_1(sc, R12A_CCK_RX_PATH + 3, 0x0f); 206} 207#endif 208 209void 210r12a_iq_calib_sw(struct rtwn_softc *sc) 211{ 212#define R12A_MAX_NRXCHAINS 2 213 uint32_t bb_vals[nitems(r12a_iq_bb_regs)]; 214 uint32_t afe_vals[nitems(r12a_iq_afe_regs)]; 215 uint32_t rf_vals[nitems(r12a_iq_rf_regs) * R12A_MAX_NRXCHAINS]; 216 uint32_t rfe[2]; 217 218 KASSERT(sc->nrxchains <= R12A_MAX_NRXCHAINS, 219 ("nrxchains > %d (%d)\n", R12A_MAX_NRXCHAINS, sc->nrxchains)); 220 221 /* Save registers. */ 222 r12a_save_bb_afe_vals(sc, bb_vals, r12a_iq_bb_regs, 223 nitems(r12a_iq_bb_regs)); 224 225 /* Select page C1. */ 226 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000); 227 rfe[0] = rtwn_bb_read(sc, R12A_RFE(0)); 228 rfe[1] = rtwn_bb_read(sc, R12A_RFE(1)); 229 230 r12a_save_bb_afe_vals(sc, afe_vals, r12a_iq_afe_regs, 231 nitems(r12a_iq_afe_regs)); 232 r12a_save_rf_vals(sc, rf_vals, r12a_iq_rf_regs, 233 nitems(r12a_iq_rf_regs)); 234 235#ifdef RTWN_TODO 236 /* Configure MAC. */ 237 rtwn_iq_config_mac(sc); 238 rtwn_iq_tx(sc); 239#endif 240 241 r12a_restore_rf_vals(sc, rf_vals, r12a_iq_rf_regs, 242 nitems(r12a_iq_rf_regs)); 243 r12a_restore_bb_afe_vals(sc, afe_vals, r12a_iq_afe_regs, 244 nitems(r12a_iq_afe_regs)); 245 246 /* Select page C1. */ 247 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0, 0x80000000); 248 249 /* Chain 0. */ 250 rtwn_bb_write(sc, R12A_SLEEP_NAV(0), 0); 251 rtwn_bb_write(sc, R12A_PMPD(0), 0); 252 rtwn_bb_write(sc, 0xc88, 0); 253 rtwn_bb_write(sc, 0xc8c, 0x3c000000); 254 rtwn_bb_setbits(sc, 0xc90, 0, 0x00000080); 255 rtwn_bb_setbits(sc, 0xcc4, 0, 0x20040000); 256 rtwn_bb_setbits(sc, 0xcc8, 0, 0x20000000); 257 258 /* Chain 1. */ 259 rtwn_bb_write(sc, R12A_SLEEP_NAV(1), 0); 260 rtwn_bb_write(sc, R12A_PMPD(1), 0); 261 rtwn_bb_write(sc, 0xe88, 0); 262 rtwn_bb_write(sc, 0xe8c, 0x3c000000); 263 rtwn_bb_setbits(sc, 0xe90, 0, 0x00000080); 264 rtwn_bb_setbits(sc, 0xec4, 0, 0x20040000); 265 rtwn_bb_setbits(sc, 0xec8, 0, 0x20000000); 266 267 rtwn_bb_write(sc, R12A_RFE(0), rfe[0]); 268 rtwn_bb_write(sc, R12A_RFE(1), rfe[1]); 269 270 r12a_restore_bb_afe_vals(sc, bb_vals, r12a_iq_bb_regs, 271 nitems(r12a_iq_bb_regs)); 272#undef R12A_MAX_NRXCHAINS 273} 274 275void 276r12a_iq_calib(struct rtwn_softc *sc) 277{ 278#ifndef RTWN_WITHOUT_UCODE 279 if ((sc->sc_flags & RTWN_FW_LOADED) && 280 rtwn_r12a_iq_calib_fw_supported(sc)) 281 r12a_iq_calib_fw(sc); 282 else 283#endif 284 rtwn_r12a_iq_calib_sw(sc); 285} 286