1/* $OpenBSD: if_rtwnreg.h,v 1.3 2015/06/14 08:02:47 stsp Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 * $FreeBSD$ 21 */ 22 23#ifndef R92CE_REG_H 24#define R92CE_REG_H 25 26#include <dev/rtwn/rtl8192c/r92c_reg.h> 27 28/* 29 * MAC registers. 30 */ 31/* System Configuration. */ 32#define R92C_PCIE_MIO_INTF 0x0e4 33#define R92C_PCIE_MIO_INTD 0x0e8 34/* PCIe Configuration. */ 35#define R92C_PCIE_CTRL_REG 0x300 36#define R92C_INT_MIG 0x304 37#define R92C_BCNQ_DESA 0x308 38#define R92C_HQ_DESA 0x310 39#define R92C_MGQ_DESA 0x318 40#define R92C_VOQ_DESA 0x320 41#define R92C_VIQ_DESA 0x328 42#define R92C_BEQ_DESA 0x330 43#define R92C_BKQ_DESA 0x338 44#define R92C_RX_DESA 0x340 45#define R92C_DBI 0x348 46#define R92C_MDIO 0x354 47#define R92C_DBG_SEL 0x360 48#define R92C_PCIE_HRPWM 0x361 49#define R92C_PCIE_HCPWM 0x363 50#define R92C_UART_CTRL 0x364 51#define R92C_UART_TX_DES 0x370 52#define R92C_UART_RX_DES 0x378 53 54/* Bits for R92C_GPIO_MUXCFG. */ 55#define R92C_GPIO_MUXCFG_RFKILL 0x0008 56 57/* Bits for R92C_GPIO_IO_SEL. */ 58#define R92C_GPIO_IO_SEL_RFKILL 0x0008 59 60/* Bits for R92C_LEDCFG2. */ 61#define R92C_LEDCFG2_EN 0x60 62#define R92C_LEDCFG2_DIS 0x68 63 64/* Bits for R92C_HIMR. */ 65#define R92C_IMR_ROK 0x00000001 /* receive DMA OK */ 66#define R92C_IMR_VODOK 0x00000002 /* AC_VO DMA OK */ 67#define R92C_IMR_VIDOK 0x00000004 /* AC_VI DMA OK */ 68#define R92C_IMR_BEDOK 0x00000008 /* AC_BE DMA OK */ 69#define R92C_IMR_BKDOK 0x00000010 /* AC_BK DMA OK */ 70#define R92C_IMR_TXBDER 0x00000020 /* beacon transmit error */ 71#define R92C_IMR_MGNTDOK 0x00000040 /* management queue DMA OK */ 72#define R92C_IMR_TBDOK 0x00000080 /* beacon transmit OK */ 73#define R92C_IMR_HIGHDOK 0x00000100 /* high queue DMA OK */ 74#define R92C_IMR_BDOK 0x00000200 /* beacon queue DMA OK */ 75#define R92C_IMR_ATIMEND 0x00000400 /* ATIM window end interrupt */ 76#define R92C_IMR_RDU 0x00000800 /* Rx descriptor unavailable */ 77#define R92C_IMR_RXFOVW 0x00001000 /* receive FIFO overflow */ 78#define R92C_IMR_BCNINT 0x00002000 /* beacon DMA interrupt 0 */ 79#define R92C_IMR_PSTIMEOUT 0x00004000 /* powersave timeout */ 80#define R92C_IMR_TXFOVW 0x00008000 /* transmit FIFO overflow */ 81#define R92C_IMR_TIMEOUT1 0x00010000 /* timeout interrupt 1 */ 82#define R92C_IMR_TIMEOUT2 0x00020000 /* timeout interrupt 2 */ 83#define R92C_IMR_BCNDOK1 0x00040000 /* beacon queue DMA OK (1) */ 84#define R92C_IMR_BCNDOK2 0x00080000 /* beacon queue DMA OK (2) */ 85#define R92C_IMR_BCNDOK3 0x00100000 /* beacon queue DMA OK (3) */ 86#define R92C_IMR_BCNDOK4 0x00200000 /* beacon queue DMA OK (4) */ 87#define R92C_IMR_BCNDOK5 0x00400000 /* beacon queue DMA OK (5) */ 88#define R92C_IMR_BCNDOK6 0x00800000 /* beacon queue DMA OK (6) */ 89#define R92C_IMR_BCNDOK7 0x01000000 /* beacon queue DMA OK (7) */ 90#define R92C_IMR_BCNDOK8 0x02000000 /* beacon queue DMA OK (8) */ 91#define R92C_IMR_BCNDMAINT1 0x04000000 /* beacon DMA interrupt 1 */ 92#define R92C_IMR_BCNDMAINT2 0x08000000 /* beacon DMA interrupt 2 */ 93#define R92C_IMR_BCNDMAINT3 0x10000000 /* beacon DMA interrupt 3 */ 94#define R92C_IMR_BCNDMAINT4 0x20000000 /* beacon DMA interrupt 4 */ 95#define R92C_IMR_BCNDMAINT5 0x40000000 /* beacon DMA interrupt 5 */ 96#define R92C_IMR_BCNDMAINT6 0x80000000 /* beacon DMA interrupt 6 */ 97 98/* Shortcut. */ 99#define R92C_IBSS_INT_MASK \ 100 (R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER) 101 102#endif /* R92CE_REG_H */ 103