1/*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD$"); 22 23/*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_var.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55 56#include <net80211/ieee80211_var.h> 57#include <net80211/ieee80211_radiotap.h> 58#include <net80211/ieee80211_regdomain.h> 59#include <net80211/ieee80211_ratectl.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#include <netinet/if_ether.h> 66 67#include <dev/ral/rt2860reg.h> 68#include <dev/ral/rt2860var.h> 69 70#define RAL_DEBUG 71#ifdef RAL_DEBUG 72#define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 73#define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 74#else 75#define DPRINTF(x) 76#define DPRINTFN(n, x) 77#endif 78 79static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 80 const char [IFNAMSIZ], int, enum ieee80211_opmode, 81 int, const uint8_t [IEEE80211_ADDR_LEN], 82 const uint8_t [IEEE80211_ADDR_LEN]); 83static void rt2860_vap_delete(struct ieee80211vap *); 84static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 85static int rt2860_alloc_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87static void rt2860_reset_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89static void rt2860_free_tx_ring(struct rt2860_softc *, 90 struct rt2860_tx_ring *); 91static int rt2860_alloc_tx_pool(struct rt2860_softc *); 92static void rt2860_free_tx_pool(struct rt2860_softc *); 93static int rt2860_alloc_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95static void rt2860_reset_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97static void rt2860_free_rx_ring(struct rt2860_softc *, 98 struct rt2860_rx_ring *); 99static void rt2860_updatestats(struct rt2860_softc *); 100static void rt2860_newassoc(struct ieee80211_node *, int); 101static void rt2860_node_free(struct ieee80211_node *); 102#ifdef IEEE80211_HT 103static int rt2860_ampdu_rx_start(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105static void rt2860_ampdu_rx_stop(struct ieee80211com *, 106 struct ieee80211_node *, uint8_t); 107#endif 108static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 109 int); 110static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 111static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 112static void rt2860_intr_coherent(struct rt2860_softc *); 113static void rt2860_drain_stats_fifo(struct rt2860_softc *); 114static void rt2860_tx_intr(struct rt2860_softc *, int); 115static void rt2860_rx_intr(struct rt2860_softc *); 116static void rt2860_tbtt_intr(struct rt2860_softc *); 117static void rt2860_gp_intr(struct rt2860_softc *); 118static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 119 struct ieee80211_node *); 120static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 121 const struct ieee80211_bpf_params *); 122static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 123 struct ieee80211_node *, 124 const struct ieee80211_bpf_params *params); 125static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 126static void rt2860_start(struct rt2860_softc *); 127static void rt2860_watchdog(void *); 128static void rt2860_parent(struct ieee80211com *); 129static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 130static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 131static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 132static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 133static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 134static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 135static void rt2860_enable_mrr(struct rt2860_softc *); 136static void rt2860_set_txpreamble(struct rt2860_softc *); 137static void rt2860_set_basicrates(struct rt2860_softc *, 138 const struct ieee80211_rateset *); 139static void rt2860_scan_start(struct ieee80211com *); 140static void rt2860_scan_end(struct ieee80211com *); 141static void rt2860_getradiocaps(struct ieee80211com *, int, int *, 142 struct ieee80211_channel[]); 143static void rt2860_set_channel(struct ieee80211com *); 144static void rt2860_select_chan_group(struct rt2860_softc *, int); 145static void rt2860_set_chan(struct rt2860_softc *, u_int); 146static void rt3090_set_chan(struct rt2860_softc *, u_int); 147static void rt5390_set_chan(struct rt2860_softc *, u_int); 148static int rt3090_rf_init(struct rt2860_softc *); 149static void rt5390_rf_init(struct rt2860_softc *); 150static void rt3090_rf_wakeup(struct rt2860_softc *); 151static void rt5390_rf_wakeup(struct rt2860_softc *); 152static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 153 uint8_t *); 154static void rt3090_rf_setup(struct rt2860_softc *); 155static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 156static void rt2860_set_gp_timer(struct rt2860_softc *, int); 157static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 158static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 159static void rt2860_update_promisc(struct ieee80211com *); 160static void rt2860_updateslot(struct ieee80211com *); 161static void rt2860_updateprot(struct rt2860_softc *); 162static int rt2860_updateedca(struct ieee80211com *); 163#ifdef HW_CRYPTO 164static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 165 struct ieee80211_key *); 166static void rt2860_delete_key(struct ieee80211com *, 167 struct ieee80211_node *, struct ieee80211_key *); 168#endif 169static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 170static const char *rt2860_get_rf(uint16_t); 171static int rt2860_read_eeprom(struct rt2860_softc *, 172 uint8_t macaddr[IEEE80211_ADDR_LEN]); 173static int rt2860_bbp_init(struct rt2860_softc *); 174static void rt5390_bbp_init(struct rt2860_softc *); 175static int rt2860_txrx_enable(struct rt2860_softc *); 176static void rt2860_init(void *); 177static void rt2860_init_locked(struct rt2860_softc *); 178static void rt2860_stop(void *); 179static void rt2860_stop_locked(struct rt2860_softc *); 180static int rt2860_load_microcode(struct rt2860_softc *); 181#ifdef NOT_YET 182static void rt2860_calib(struct rt2860_softc *); 183#endif 184static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 185static void rt2860_switch_chan(struct rt2860_softc *, 186 struct ieee80211_channel *); 187static int rt2860_setup_beacon(struct rt2860_softc *, 188 struct ieee80211vap *); 189static void rt2860_enable_tsf_sync(struct rt2860_softc *); 190 191static const struct { 192 uint32_t reg; 193 uint32_t val; 194} rt2860_def_mac[] = { 195 RT2860_DEF_MAC 196}; 197 198static const struct { 199 uint8_t reg; 200 uint8_t val; 201} rt2860_def_bbp[] = { 202 RT2860_DEF_BBP 203}, rt5390_def_bbp[] = { 204 RT5390_DEF_BBP 205}; 206 207static const struct rfprog { 208 uint8_t chan; 209 uint32_t r1, r2, r3, r4; 210} rt2860_rf2850[] = { 211 RT2860_RF2850 212}; 213 214struct { 215 uint8_t n, r, k; 216} rt3090_freqs[] = { 217 RT3070_RF3052 218}; 219 220static const struct { 221 uint8_t reg; 222 uint8_t val; 223} rt3090_def_rf[] = { 224 RT3070_DEF_RF 225}, rt5390_def_rf[] = { 226 RT5390_DEF_RF 227}, rt5392_def_rf[] = { 228 RT5392_DEF_RF 229}; 230 231static const uint8_t rt2860_chan_5ghz[] = 232 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 233 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 234 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 }; 235 236int 237rt2860_attach(device_t dev, int id) 238{ 239 struct rt2860_softc *sc = device_get_softc(dev); 240 struct ieee80211com *ic = &sc->sc_ic; 241 uint32_t tmp; 242 int error, ntries, qid; 243 244 sc->sc_dev = dev; 245 sc->sc_debug = 0; 246 247 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 248 MTX_DEF | MTX_RECURSE); 249 250 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 251 mbufq_init(&sc->sc_snd, ifqmaxlen); 252 253 /* wait for NIC to initialize */ 254 for (ntries = 0; ntries < 100; ntries++) { 255 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 256 if (tmp != 0 && tmp != 0xffffffff) 257 break; 258 DELAY(10); 259 } 260 if (ntries == 100) { 261 device_printf(sc->sc_dev, 262 "timeout waiting for NIC to initialize\n"); 263 error = EIO; 264 goto fail1; 265 } 266 sc->mac_ver = tmp >> 16; 267 sc->mac_rev = tmp & 0xffff; 268 269 if (sc->mac_ver != 0x2860 && 270 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 271 sc->sc_flags |= RT2860_ADVANCED_PS; 272 273 /* retrieve RF rev. no and various other things from EEPROM */ 274 rt2860_read_eeprom(sc, ic->ic_macaddr); 275 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 276 "RF %s (MIMO %dT%dR), address %6D\n", 277 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 278 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 279 280 /* 281 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 282 */ 283 for (qid = 0; qid < 6; qid++) { 284 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 285 device_printf(sc->sc_dev, 286 "could not allocate Tx ring %d\n", qid); 287 goto fail2; 288 } 289 } 290 291 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 292 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 293 goto fail2; 294 } 295 296 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 297 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 298 goto fail3; 299 } 300 301 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 302 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 303 WME_AC_VO : 5; 304 305 ic->ic_softc = sc; 306 ic->ic_name = device_get_nameunit(dev); 307 ic->ic_opmode = IEEE80211_M_STA; 308 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 309 310 /* set device capabilities */ 311 ic->ic_caps = 312 IEEE80211_C_STA /* station mode */ 313 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 314 | IEEE80211_C_HOSTAP /* hostap mode */ 315 | IEEE80211_C_MONITOR /* monitor mode */ 316 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 317 | IEEE80211_C_WDS /* 4-address traffic works */ 318 | IEEE80211_C_MBSS /* mesh point link mode */ 319 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 320 | IEEE80211_C_SHSLOT /* short slot time supported */ 321 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 322#if 0 323 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 324#endif 325 | IEEE80211_C_WME /* 802.11e */ 326 ; 327 328 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 329 ic->ic_channels); 330 331 ieee80211_ifattach(ic); 332 333 ic->ic_wme.wme_update = rt2860_updateedca; 334 ic->ic_scan_start = rt2860_scan_start; 335 ic->ic_scan_end = rt2860_scan_end; 336 ic->ic_getradiocaps = rt2860_getradiocaps; 337 ic->ic_set_channel = rt2860_set_channel; 338 ic->ic_updateslot = rt2860_updateslot; 339 ic->ic_update_promisc = rt2860_update_promisc; 340 ic->ic_raw_xmit = rt2860_raw_xmit; 341 sc->sc_node_free = ic->ic_node_free; 342 ic->ic_node_free = rt2860_node_free; 343 ic->ic_newassoc = rt2860_newassoc; 344 ic->ic_transmit = rt2860_transmit; 345 ic->ic_parent = rt2860_parent; 346 ic->ic_vap_create = rt2860_vap_create; 347 ic->ic_vap_delete = rt2860_vap_delete; 348 349 ieee80211_radiotap_attach(ic, 350 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 351 RT2860_TX_RADIOTAP_PRESENT, 352 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 353 RT2860_RX_RADIOTAP_PRESENT); 354 355#ifdef RAL_DEBUG 356 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 357 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 358 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 359#endif 360 if (bootverbose) 361 ieee80211_announce(ic); 362 363 return 0; 364 365fail3: rt2860_free_rx_ring(sc, &sc->rxq); 366fail2: while (--qid >= 0) 367 rt2860_free_tx_ring(sc, &sc->txq[qid]); 368fail1: mtx_destroy(&sc->sc_mtx); 369 return error; 370} 371 372int 373rt2860_detach(void *xsc) 374{ 375 struct rt2860_softc *sc = xsc; 376 struct ieee80211com *ic = &sc->sc_ic; 377 int qid; 378 379 RAL_LOCK(sc); 380 rt2860_stop_locked(sc); 381 RAL_UNLOCK(sc); 382 383 ieee80211_ifdetach(ic); 384 mbufq_drain(&sc->sc_snd); 385 for (qid = 0; qid < 6; qid++) 386 rt2860_free_tx_ring(sc, &sc->txq[qid]); 387 rt2860_free_rx_ring(sc, &sc->rxq); 388 rt2860_free_tx_pool(sc); 389 390 mtx_destroy(&sc->sc_mtx); 391 392 return 0; 393} 394 395void 396rt2860_shutdown(void *xsc) 397{ 398 struct rt2860_softc *sc = xsc; 399 400 rt2860_stop(sc); 401} 402 403void 404rt2860_suspend(void *xsc) 405{ 406 struct rt2860_softc *sc = xsc; 407 408 rt2860_stop(sc); 409} 410 411void 412rt2860_resume(void *xsc) 413{ 414 struct rt2860_softc *sc = xsc; 415 416 if (sc->sc_ic.ic_nrunning > 0) 417 rt2860_init(sc); 418} 419 420static struct ieee80211vap * 421rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 422 enum ieee80211_opmode opmode, int flags, 423 const uint8_t bssid[IEEE80211_ADDR_LEN], 424 const uint8_t mac[IEEE80211_ADDR_LEN]) 425{ 426 struct rt2860_softc *sc = ic->ic_softc; 427 struct rt2860_vap *rvp; 428 struct ieee80211vap *vap; 429 430 switch (opmode) { 431 case IEEE80211_M_STA: 432 case IEEE80211_M_IBSS: 433 case IEEE80211_M_AHDEMO: 434 case IEEE80211_M_MONITOR: 435 case IEEE80211_M_HOSTAP: 436 case IEEE80211_M_MBSS: 437 /* XXXRP: TBD */ 438 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 439 device_printf(sc->sc_dev, "only 1 vap supported\n"); 440 return NULL; 441 } 442 if (opmode == IEEE80211_M_STA) 443 flags |= IEEE80211_CLONE_NOBEACONS; 444 break; 445 case IEEE80211_M_WDS: 446 if (TAILQ_EMPTY(&ic->ic_vaps) || 447 ic->ic_opmode != IEEE80211_M_HOSTAP) { 448 device_printf(sc->sc_dev, 449 "wds only supported in ap mode\n"); 450 return NULL; 451 } 452 /* 453 * Silently remove any request for a unique 454 * bssid; WDS vap's always share the local 455 * mac address. 456 */ 457 flags &= ~IEEE80211_CLONE_BSSID; 458 break; 459 default: 460 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 461 return NULL; 462 } 463 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 464 vap = &rvp->ral_vap; 465 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 466 467 /* override state transition machine */ 468 rvp->ral_newstate = vap->iv_newstate; 469 vap->iv_newstate = rt2860_newstate; 470#if 0 471 vap->iv_update_beacon = rt2860_beacon_update; 472#endif 473 474 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 475 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 476 477 ieee80211_ratectl_init(vap); 478 /* complete setup */ 479 ieee80211_vap_attach(vap, ieee80211_media_change, 480 ieee80211_media_status, mac); 481 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 482 ic->ic_opmode = opmode; 483 return vap; 484} 485 486static void 487rt2860_vap_delete(struct ieee80211vap *vap) 488{ 489 struct rt2860_vap *rvp = RT2860_VAP(vap); 490 491 ieee80211_ratectl_deinit(vap); 492 ieee80211_vap_detach(vap); 493 free(rvp, M_80211_VAP); 494} 495 496static void 497rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 498{ 499 if (error != 0) 500 return; 501 502 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 503 504 *(bus_addr_t *)arg = segs[0].ds_addr; 505} 506 507static int 508rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 509{ 510 int size, error; 511 512 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 513 514 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 515 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 516 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 517 if (error != 0) { 518 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 519 goto fail; 520 } 521 522 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 523 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 524 if (error != 0) { 525 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 526 goto fail; 527 } 528 529 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 530 size, rt2860_dma_map_addr, &ring->paddr, 0); 531 if (error != 0) { 532 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 533 goto fail; 534 } 535 536 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 537 538 return 0; 539 540fail: rt2860_free_tx_ring(sc, ring); 541 return error; 542} 543 544void 545rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 546{ 547 struct rt2860_tx_data *data; 548 int i; 549 550 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 551 if ((data = ring->data[i]) == NULL) 552 continue; /* nothing mapped in this slot */ 553 554 if (data->m != NULL) { 555 bus_dmamap_sync(sc->txwi_dmat, data->map, 556 BUS_DMASYNC_POSTWRITE); 557 bus_dmamap_unload(sc->txwi_dmat, data->map); 558 m_freem(data->m); 559 data->m = NULL; 560 } 561 if (data->ni != NULL) { 562 ieee80211_free_node(data->ni); 563 data->ni = NULL; 564 } 565 566 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 567 ring->data[i] = NULL; 568 } 569 570 ring->queued = 0; 571 ring->cur = ring->next = 0; 572} 573 574void 575rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 576{ 577 struct rt2860_tx_data *data; 578 int i; 579 580 if (ring->txd != NULL) { 581 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 582 BUS_DMASYNC_POSTWRITE); 583 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 584 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 585 } 586 if (ring->desc_dmat != NULL) 587 bus_dma_tag_destroy(ring->desc_dmat); 588 589 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 590 if ((data = ring->data[i]) == NULL) 591 continue; /* nothing mapped in this slot */ 592 593 if (data->m != NULL) { 594 bus_dmamap_sync(sc->txwi_dmat, data->map, 595 BUS_DMASYNC_POSTWRITE); 596 bus_dmamap_unload(sc->txwi_dmat, data->map); 597 m_freem(data->m); 598 } 599 if (data->ni != NULL) 600 ieee80211_free_node(data->ni); 601 602 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 603 } 604} 605 606/* 607 * Allocate a pool of TX Wireless Information blocks. 608 */ 609int 610rt2860_alloc_tx_pool(struct rt2860_softc *sc) 611{ 612 caddr_t vaddr; 613 bus_addr_t paddr; 614 int i, size, error; 615 616 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 617 618 /* init data_pool early in case of failure.. */ 619 SLIST_INIT(&sc->data_pool); 620 621 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 622 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 623 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 624 if (error != 0) { 625 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 626 goto fail; 627 } 628 629 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 630 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 631 if (error != 0) { 632 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 633 goto fail; 634 } 635 636 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 637 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 638 if (error != 0) { 639 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 640 goto fail; 641 } 642 643 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 644 645 vaddr = sc->txwi_vaddr; 646 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 647 struct rt2860_tx_data *data = &sc->data[i]; 648 649 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 650 if (error != 0) { 651 device_printf(sc->sc_dev, "could not create DMA map\n"); 652 goto fail; 653 } 654 data->txwi = (struct rt2860_txwi *)vaddr; 655 data->paddr = paddr; 656 vaddr += RT2860_TXWI_DMASZ; 657 paddr += RT2860_TXWI_DMASZ; 658 659 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 660 } 661 662 return 0; 663 664fail: rt2860_free_tx_pool(sc); 665 return error; 666} 667 668void 669rt2860_free_tx_pool(struct rt2860_softc *sc) 670{ 671 if (sc->txwi_vaddr != NULL) { 672 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 673 BUS_DMASYNC_POSTWRITE); 674 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 675 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 676 } 677 if (sc->txwi_dmat != NULL) 678 bus_dma_tag_destroy(sc->txwi_dmat); 679 680 while (!SLIST_EMPTY(&sc->data_pool)) { 681 struct rt2860_tx_data *data; 682 data = SLIST_FIRST(&sc->data_pool); 683 bus_dmamap_destroy(sc->txwi_dmat, data->map); 684 SLIST_REMOVE_HEAD(&sc->data_pool, next); 685 } 686} 687 688int 689rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 690{ 691 bus_addr_t physaddr; 692 int i, size, error; 693 694 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 695 696 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 697 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 698 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 699 if (error != 0) { 700 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 701 goto fail; 702 } 703 704 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 705 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 706 if (error != 0) { 707 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 708 goto fail; 709 } 710 711 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 712 size, rt2860_dma_map_addr, &ring->paddr, 0); 713 if (error != 0) { 714 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 715 goto fail; 716 } 717 718 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 719 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 720 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 721 if (error != 0) { 722 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 723 goto fail; 724 } 725 726 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 727 struct rt2860_rx_data *data = &ring->data[i]; 728 struct rt2860_rxd *rxd = &ring->rxd[i]; 729 730 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 731 if (error != 0) { 732 device_printf(sc->sc_dev, "could not create DMA map\n"); 733 goto fail; 734 } 735 736 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 737 if (data->m == NULL) { 738 device_printf(sc->sc_dev, 739 "could not allocate rx mbuf\n"); 740 error = ENOMEM; 741 goto fail; 742 } 743 744 error = bus_dmamap_load(ring->data_dmat, data->map, 745 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 746 &physaddr, 0); 747 if (error != 0) { 748 device_printf(sc->sc_dev, 749 "could not load rx buf DMA map"); 750 goto fail; 751 } 752 753 rxd->sdp0 = htole32(physaddr); 754 rxd->sdl0 = htole16(MCLBYTES); 755 } 756 757 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 758 759 return 0; 760 761fail: rt2860_free_rx_ring(sc, ring); 762 return error; 763} 764 765void 766rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 767{ 768 int i; 769 770 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 771 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 772 773 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 774 775 ring->cur = 0; 776} 777 778void 779rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 780{ 781 int i; 782 783 if (ring->rxd != NULL) { 784 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 785 BUS_DMASYNC_POSTWRITE); 786 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 787 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 788 } 789 if (ring->desc_dmat != NULL) 790 bus_dma_tag_destroy(ring->desc_dmat); 791 792 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 793 struct rt2860_rx_data *data = &ring->data[i]; 794 795 if (data->m != NULL) { 796 bus_dmamap_sync(ring->data_dmat, data->map, 797 BUS_DMASYNC_POSTREAD); 798 bus_dmamap_unload(ring->data_dmat, data->map); 799 m_freem(data->m); 800 } 801 if (data->map != NULL) 802 bus_dmamap_destroy(ring->data_dmat, data->map); 803 } 804 if (ring->data_dmat != NULL) 805 bus_dma_tag_destroy(ring->data_dmat); 806} 807 808static void 809rt2860_updatestats(struct rt2860_softc *sc) 810{ 811 struct ieee80211com *ic = &sc->sc_ic; 812 813 /* 814 * In IBSS or HostAP modes (when the hardware sends beacons), the 815 * MAC can run into a livelock and start sending CTS-to-self frames 816 * like crazy if protection is enabled. Fortunately, we can detect 817 * when such a situation occurs and reset the MAC. 818 */ 819 if (ic->ic_curmode != IEEE80211_M_STA) { 820 /* check if we're in a livelock situation.. */ 821 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 822 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 823 /* ..and reset MAC/BBP for a while.. */ 824 DPRINTF(("CTS-to-self livelock detected\n")); 825 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 826 RAL_BARRIER_WRITE(sc); 827 DELAY(1); 828 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 829 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 830 } 831 } 832} 833 834static void 835rt2860_newassoc(struct ieee80211_node *ni, int isnew) 836{ 837 struct ieee80211com *ic = ni->ni_ic; 838 struct rt2860_softc *sc = ic->ic_softc; 839 uint8_t wcid; 840 841 wcid = IEEE80211_AID(ni->ni_associd); 842 if (isnew && ni->ni_associd != 0) { 843 sc->wcid2ni[wcid] = ni; 844 845 /* init WCID table entry */ 846 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 847 ni->ni_macaddr, IEEE80211_ADDR_LEN); 848 } 849 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 850 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 851} 852 853static void 854rt2860_node_free(struct ieee80211_node *ni) 855{ 856 struct ieee80211com *ic = ni->ni_ic; 857 struct rt2860_softc *sc = ic->ic_softc; 858 uint8_t wcid; 859 860 if (ni->ni_associd != 0) { 861 wcid = IEEE80211_AID(ni->ni_associd); 862 863 /* clear Rx WCID search table entry */ 864 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 865 } 866 sc->sc_node_free(ni); 867} 868 869#ifdef IEEE80211_HT 870static int 871rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 872 uint8_t tid) 873{ 874 struct rt2860_softc *sc = ic->ic_softc; 875 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 876 uint32_t tmp; 877 878 /* update BA session mask */ 879 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 880 tmp |= (1 << tid) << 16; 881 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 882 return 0; 883} 884 885static void 886rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 887 uint8_t tid) 888{ 889 struct rt2860_softc *sc = ic->ic_softc; 890 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 891 uint32_t tmp; 892 893 /* update BA session mask */ 894 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 895 tmp &= ~((1 << tid) << 16); 896 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 897} 898#endif 899 900static int 901rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 902{ 903 struct rt2860_vap *rvp = RT2860_VAP(vap); 904 struct ieee80211com *ic = vap->iv_ic; 905 struct rt2860_softc *sc = ic->ic_softc; 906 uint32_t tmp; 907 int error; 908 909 if (vap->iv_state == IEEE80211_S_RUN) { 910 /* turn link LED off */ 911 rt2860_set_leds(sc, RT2860_LED_RADIO); 912 } 913 914 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 915 /* abort TSF synchronization */ 916 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 917 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 918 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 919 RT2860_TBTT_TIMER_EN)); 920 } 921 922 rt2860_set_gp_timer(sc, 0); 923 924 error = rvp->ral_newstate(vap, nstate, arg); 925 if (error != 0) 926 return (error); 927 928 if (nstate == IEEE80211_S_RUN) { 929 struct ieee80211_node *ni = vap->iv_bss; 930 931 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 932 rt2860_enable_mrr(sc); 933 rt2860_set_txpreamble(sc); 934 rt2860_set_basicrates(sc, &ni->ni_rates); 935 rt2860_set_bssid(sc, ni->ni_bssid); 936 } 937 938 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 939 vap->iv_opmode == IEEE80211_M_IBSS || 940 vap->iv_opmode == IEEE80211_M_MBSS) { 941 error = rt2860_setup_beacon(sc, vap); 942 if (error != 0) 943 return error; 944 } 945 946 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 947 rt2860_enable_tsf_sync(sc); 948 rt2860_set_gp_timer(sc, 500); 949 } 950 951 /* turn link LED on */ 952 rt2860_set_leds(sc, RT2860_LED_RADIO | 953 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 954 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 955 } 956 return error; 957} 958 959/* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 960static uint16_t 961rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 962{ 963 uint32_t tmp; 964 uint16_t reg; 965 int ntries; 966 967 addr *= 2; 968 /*- 969 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 970 * DATA0: F E D C 971 * DATA1: B A 9 8 972 * DATA2: 7 6 5 4 973 * DATA3: 3 2 1 0 974 */ 975 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 976 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 977 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 978 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 979 for (ntries = 0; ntries < 500; ntries++) { 980 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 981 if (!(tmp & RT3070_EFSROM_KICK)) 982 break; 983 DELAY(2); 984 } 985 if (ntries == 500) 986 return 0xffff; 987 988 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 989 return 0xffff; /* address not found */ 990 991 /* determine to which 32-bit register our 16-bit word belongs */ 992 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 993 tmp = RAL_READ(sc, reg); 994 995 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 996} 997 998/* 999 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1000 * 93C66 or 93C86). 1001 */ 1002static uint16_t 1003rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1004{ 1005 uint32_t tmp; 1006 uint16_t val; 1007 int n; 1008 1009 /* clock C once before the first command */ 1010 RT2860_EEPROM_CTL(sc, 0); 1011 1012 RT2860_EEPROM_CTL(sc, RT2860_S); 1013 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1014 RT2860_EEPROM_CTL(sc, RT2860_S); 1015 1016 /* write start bit (1) */ 1017 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1018 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1019 1020 /* write READ opcode (10) */ 1021 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1023 RT2860_EEPROM_CTL(sc, RT2860_S); 1024 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1025 1026 /* write address (A5-A0 or A7-A0) */ 1027 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1028 for (; n >= 0; n--) { 1029 RT2860_EEPROM_CTL(sc, RT2860_S | 1030 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1031 RT2860_EEPROM_CTL(sc, RT2860_S | 1032 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1033 } 1034 1035 RT2860_EEPROM_CTL(sc, RT2860_S); 1036 1037 /* read data Q15-Q0 */ 1038 val = 0; 1039 for (n = 15; n >= 0; n--) { 1040 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1041 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1042 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1043 RT2860_EEPROM_CTL(sc, RT2860_S); 1044 } 1045 1046 RT2860_EEPROM_CTL(sc, 0); 1047 1048 /* clear Chip Select and clock C */ 1049 RT2860_EEPROM_CTL(sc, RT2860_S); 1050 RT2860_EEPROM_CTL(sc, 0); 1051 RT2860_EEPROM_CTL(sc, RT2860_C); 1052 1053 return val; 1054} 1055 1056static __inline uint16_t 1057rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1058{ 1059 /* either eFUSE ROM or EEPROM */ 1060 return sc->sc_srom_read(sc, addr); 1061} 1062 1063static void 1064rt2860_intr_coherent(struct rt2860_softc *sc) 1065{ 1066 uint32_t tmp; 1067 1068 /* DMA finds data coherent event when checking the DDONE bit */ 1069 1070 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1071 1072 /* restart DMA engine */ 1073 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1074 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1075 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1076 1077 (void)rt2860_txrx_enable(sc); 1078} 1079 1080static void 1081rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1082{ 1083 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 1084 struct ieee80211_node *ni; 1085 uint32_t stat; 1086 uint8_t wcid, mcs, pid; 1087 1088 /* drain Tx status FIFO (maxsize = 16) */ 1089 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 1090 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1091 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1092 1093 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1094 if (wcid > RT2860_WCID_MAX) 1095 continue; 1096 ni = sc->wcid2ni[wcid]; 1097 1098 /* if no ACK was requested, no feedback is available */ 1099 if (!(stat & RT2860_TXQ_ACKREQ) || ni == NULL) 1100 continue; 1101 1102 /* update per-STA AMRR stats */ 1103 if (stat & RT2860_TXQ_OK) { 1104 /* 1105 * Check if there were retries, ie if the Tx success 1106 * rate is different from the requested rate. Note 1107 * that it works only because we do not allow rate 1108 * fallback from OFDM to CCK. 1109 */ 1110 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1111 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1112 if (mcs + 1 != pid) 1113 txs->long_retries = 1; 1114 else 1115 txs->long_retries = 0; 1116 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 1117 ieee80211_ratectl_tx_complete(ni, txs); 1118 } else { 1119 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 1120 txs->long_retries = 1; /* XXX */ 1121 ieee80211_ratectl_tx_complete(ni, txs); 1122 if_inc_counter(ni->ni_vap->iv_ifp, 1123 IFCOUNTER_OERRORS, 1); 1124 } 1125 } 1126} 1127 1128static void 1129rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1130{ 1131 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1132 uint32_t hw; 1133 1134 rt2860_drain_stats_fifo(sc); 1135 1136 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1137 while (ring->next != hw) { 1138 struct rt2860_tx_data *data = ring->data[ring->next]; 1139 1140 if (data != NULL) { 1141 bus_dmamap_sync(sc->txwi_dmat, data->map, 1142 BUS_DMASYNC_POSTWRITE); 1143 bus_dmamap_unload(sc->txwi_dmat, data->map); 1144 ieee80211_tx_complete(data->ni, data->m, 0); 1145 data->ni = NULL; 1146 data->m = NULL; 1147 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1148 ring->data[ring->next] = NULL; 1149 } 1150 ring->queued--; 1151 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1152 } 1153 1154 sc->sc_tx_timer = 0; 1155 if (ring->queued < RT2860_TX_RING_COUNT) 1156 sc->qfullmsk &= ~(1 << qid); 1157 rt2860_start(sc); 1158} 1159 1160/* 1161 * Return the Rx chain with the highest RSSI for a given frame. 1162 */ 1163static __inline uint8_t 1164rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1165{ 1166 uint8_t rxchain = 0; 1167 1168 if (sc->nrxchains > 1) { 1169 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1170 rxchain = 1; 1171 if (sc->nrxchains > 2) 1172 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1173 rxchain = 2; 1174 } 1175 return rxchain; 1176} 1177 1178static void 1179rt2860_rx_intr(struct rt2860_softc *sc) 1180{ 1181 struct rt2860_rx_radiotap_header *tap; 1182 struct ieee80211com *ic = &sc->sc_ic; 1183 struct ieee80211_frame *wh; 1184 struct ieee80211_node *ni; 1185 struct mbuf *m, *m1; 1186 bus_addr_t physaddr; 1187 uint32_t hw; 1188 uint16_t phy; 1189 uint8_t ant; 1190 int8_t rssi, nf; 1191 int error; 1192 1193 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1194 while (sc->rxq.cur != hw) { 1195 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1196 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1197 struct rt2860_rxwi *rxwi; 1198 1199 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1200 BUS_DMASYNC_POSTREAD); 1201 1202 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1203 DPRINTF(("RXD DDONE bit not set!\n")); 1204 break; /* should not happen */ 1205 } 1206 1207 if (__predict_false(rxd->flags & 1208 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1209 counter_u64_add(ic->ic_ierrors, 1); 1210 goto skip; 1211 } 1212 1213#ifdef HW_CRYPTO 1214 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1215 /* report MIC failures to net80211 for TKIP */ 1216 ic->ic_stats.is_rx_locmicfail++; 1217 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1218 counter_u64_add(ic->ic_ierrors, 1); 1219 goto skip; 1220 } 1221#endif 1222 1223 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1224 if (__predict_false(m1 == NULL)) { 1225 counter_u64_add(ic->ic_ierrors, 1); 1226 goto skip; 1227 } 1228 1229 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1230 BUS_DMASYNC_POSTREAD); 1231 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1232 1233 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1234 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1235 &physaddr, 0); 1236 if (__predict_false(error != 0)) { 1237 m_freem(m1); 1238 1239 /* try to reload the old mbuf */ 1240 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1241 mtod(data->m, void *), MCLBYTES, 1242 rt2860_dma_map_addr, &physaddr, 0); 1243 if (__predict_false(error != 0)) { 1244 panic("%s: could not load old rx mbuf", 1245 device_get_name(sc->sc_dev)); 1246 } 1247 /* physical address may have changed */ 1248 rxd->sdp0 = htole32(physaddr); 1249 counter_u64_add(ic->ic_ierrors, 1); 1250 goto skip; 1251 } 1252 1253 /* 1254 * New mbuf successfully loaded, update Rx ring and continue 1255 * processing. 1256 */ 1257 m = data->m; 1258 data->m = m1; 1259 rxd->sdp0 = htole32(physaddr); 1260 1261 rxwi = mtod(m, struct rt2860_rxwi *); 1262 1263 /* finalize mbuf */ 1264 m->m_data = (caddr_t)(rxwi + 1); 1265 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1266 1267 wh = mtod(m, struct ieee80211_frame *); 1268#ifdef HW_CRYPTO 1269 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1270 /* frame is decrypted by hardware */ 1271 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1272 } 1273#endif 1274 1275 /* HW may insert 2 padding bytes after 802.11 header */ 1276 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1277 u_int hdrlen = ieee80211_hdrsize(wh); 1278 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1279 m->m_data += 2; 1280 wh = mtod(m, struct ieee80211_frame *); 1281 } 1282 1283 ant = rt2860_maxrssi_chain(sc, rxwi); 1284 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1285 nf = RT2860_NOISE_FLOOR; 1286 1287 if (ieee80211_radiotap_active(ic)) { 1288 tap = &sc->sc_rxtap; 1289 tap->wr_flags = 0; 1290 tap->wr_antenna = ant; 1291 tap->wr_antsignal = nf + rssi; 1292 tap->wr_antnoise = nf; 1293 /* in case it can't be found below */ 1294 tap->wr_rate = 2; 1295 phy = le16toh(rxwi->phy); 1296 switch (phy & RT2860_PHY_MODE) { 1297 case RT2860_PHY_CCK: 1298 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1299 case 0: tap->wr_rate = 2; break; 1300 case 1: tap->wr_rate = 4; break; 1301 case 2: tap->wr_rate = 11; break; 1302 case 3: tap->wr_rate = 22; break; 1303 } 1304 if (phy & RT2860_PHY_SHPRE) 1305 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1306 break; 1307 case RT2860_PHY_OFDM: 1308 switch (phy & RT2860_PHY_MCS) { 1309 case 0: tap->wr_rate = 12; break; 1310 case 1: tap->wr_rate = 18; break; 1311 case 2: tap->wr_rate = 24; break; 1312 case 3: tap->wr_rate = 36; break; 1313 case 4: tap->wr_rate = 48; break; 1314 case 5: tap->wr_rate = 72; break; 1315 case 6: tap->wr_rate = 96; break; 1316 case 7: tap->wr_rate = 108; break; 1317 } 1318 break; 1319 } 1320 } 1321 1322 RAL_UNLOCK(sc); 1323 wh = mtod(m, struct ieee80211_frame *); 1324 1325 /* send the frame to the 802.11 layer */ 1326 ni = ieee80211_find_rxnode(ic, 1327 (struct ieee80211_frame_min *)wh); 1328 if (ni != NULL) { 1329 (void)ieee80211_input(ni, m, rssi - nf, nf); 1330 ieee80211_free_node(ni); 1331 } else 1332 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1333 1334 RAL_LOCK(sc); 1335 1336skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1337 1338 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1339 BUS_DMASYNC_PREWRITE); 1340 1341 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1342 } 1343 1344 /* tell HW what we have processed */ 1345 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1346 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1347} 1348 1349static void 1350rt2860_tbtt_intr(struct rt2860_softc *sc) 1351{ 1352#if 0 1353 struct ieee80211com *ic = &sc->sc_ic; 1354 1355#ifndef IEEE80211_STA_ONLY 1356 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1357 /* one less beacon until next DTIM */ 1358 if (ic->ic_dtim_count == 0) 1359 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1360 else 1361 ic->ic_dtim_count--; 1362 1363 /* update dynamic parts of beacon */ 1364 rt2860_setup_beacon(sc); 1365 1366 /* flush buffered multicast frames */ 1367 if (ic->ic_dtim_count == 0) 1368 ieee80211_notify_dtim(ic); 1369 } 1370#endif 1371 /* check if protection mode has changed */ 1372 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1373 rt2860_updateprot(sc); 1374 sc->sc_ic_flags = ic->ic_flags; 1375 } 1376#endif 1377} 1378 1379static void 1380rt2860_gp_intr(struct rt2860_softc *sc) 1381{ 1382 struct ieee80211com *ic = &sc->sc_ic; 1383 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1384 1385 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1386 1387 if (vap->iv_state == IEEE80211_S_RUN) 1388 rt2860_updatestats(sc); 1389} 1390 1391void 1392rt2860_intr(void *arg) 1393{ 1394 struct rt2860_softc *sc = arg; 1395 uint32_t r; 1396 1397 RAL_LOCK(sc); 1398 1399#ifndef __HAIKU__ 1400 r = RAL_READ(sc, RT2860_INT_STATUS); 1401 if (__predict_false(r == 0xffffffff)) { 1402 RAL_UNLOCK(sc); 1403 return; /* device likely went away */ 1404 } 1405 if (r == 0) { 1406 RAL_UNLOCK(sc); 1407 return; /* not for us */ 1408 } 1409#else 1410 r = atomic_get((int32 *)&sc->sc_intr_status); 1411#endif 1412 1413 /* acknowledge interrupts */ 1414 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1415 1416 if (r & RT2860_TX_RX_COHERENT) 1417 rt2860_intr_coherent(sc); 1418 1419 if (r & RT2860_MAC_INT_2) /* TX status */ 1420 rt2860_drain_stats_fifo(sc); 1421 1422 if (r & RT2860_TX_DONE_INT5) 1423 rt2860_tx_intr(sc, 5); 1424 1425 if (r & RT2860_RX_DONE_INT) 1426 rt2860_rx_intr(sc); 1427 1428 if (r & RT2860_TX_DONE_INT4) 1429 rt2860_tx_intr(sc, 4); 1430 1431 if (r & RT2860_TX_DONE_INT3) 1432 rt2860_tx_intr(sc, 3); 1433 1434 if (r & RT2860_TX_DONE_INT2) 1435 rt2860_tx_intr(sc, 2); 1436 1437 if (r & RT2860_TX_DONE_INT1) 1438 rt2860_tx_intr(sc, 1); 1439 1440 if (r & RT2860_TX_DONE_INT0) 1441 rt2860_tx_intr(sc, 0); 1442 1443 if (r & RT2860_MAC_INT_0) /* TBTT */ 1444 rt2860_tbtt_intr(sc); 1445 1446 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1447 /* TBD wakeup */; 1448 1449 if (r & RT2860_MAC_INT_4) /* GP timer */ 1450 rt2860_gp_intr(sc); 1451 1452 RAL_UNLOCK(sc); 1453} 1454 1455static int 1456rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1457{ 1458 struct ieee80211com *ic = &sc->sc_ic; 1459 struct ieee80211vap *vap = ni->ni_vap; 1460 struct rt2860_tx_ring *ring; 1461 struct rt2860_tx_data *data; 1462 struct rt2860_txd *txd; 1463 struct rt2860_txwi *txwi; 1464 struct ieee80211_frame *wh; 1465 const struct ieee80211_txparam *tp = ni->ni_txparms; 1466 struct ieee80211_key *k; 1467 struct mbuf *m1; 1468 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1469 bus_dma_segment_t *seg; 1470 u_int hdrlen; 1471 uint16_t qos, dur; 1472 uint8_t type, qsel, mcs, pid, tid, qid; 1473 int i, nsegs, ntxds, pad, rate, ridx, error; 1474 1475 /* the data pool contains at least one element, pick the first */ 1476 data = SLIST_FIRST(&sc->data_pool); 1477 1478 wh = mtod(m, struct ieee80211_frame *); 1479 1480 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1481 k = ieee80211_crypto_encap(ni, m); 1482 if (k == NULL) { 1483 m_freem(m); 1484 return ENOBUFS; 1485 } 1486 1487 /* packet header may have moved, reset our local pointer */ 1488 wh = mtod(m, struct ieee80211_frame *); 1489 } 1490 1491 hdrlen = ieee80211_anyhdrsize(wh); 1492 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1493 1494 if (m->m_flags & M_EAPOL) { 1495 rate = tp->mgmtrate; 1496 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1497 rate = tp->mcastrate; 1498 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1499 rate = tp->ucastrate; 1500 } else { 1501 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1502 rate = ni->ni_txrate; 1503 } 1504 rate &= IEEE80211_RATE_VAL; 1505 1506 qid = M_WME_GETAC(m); 1507 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1508 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1509 tid = qos & IEEE80211_QOS_TID; 1510 } else { 1511 qos = 0; 1512 tid = 0; 1513 } 1514 ring = &sc->txq[qid]; 1515 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1516 1517 /* get MCS code from rate index */ 1518 mcs = rt2860_rates[ridx].mcs; 1519 1520 /* setup TX Wireless Information */ 1521 txwi = data->txwi; 1522 txwi->flags = 0; 1523 /* let HW generate seq numbers for non-QoS frames */ 1524 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1525 if (type == IEEE80211_FC0_TYPE_DATA) 1526 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1527 else 1528 txwi->wcid = 0xff; 1529 txwi->len = htole16(m->m_pkthdr.len); 1530 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1531 txwi->phy = htole16(RT2860_PHY_CCK); 1532 if (ridx != RT2860_RIDX_CCK1 && 1533 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1534 mcs |= RT2860_PHY_SHPRE; 1535 } else 1536 txwi->phy = htole16(RT2860_PHY_OFDM); 1537 txwi->phy |= htole16(mcs); 1538 1539 /* 1540 * We store the MCS code into the driver-private PacketID field. 1541 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1542 * that we know at which initial rate the frame was transmitted. 1543 * We add 1 to the MCS code because setting the PacketID field to 1544 * 0 means that we don't want feedback in TX_STAT_FIFO. 1545 */ 1546 pid = (mcs + 1) & 0xf; 1547 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1548 1549 /* check if RTS/CTS or CTS-to-self protection is required */ 1550 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1551 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1552 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1553 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1554 txwi->txop = RT2860_TX_TXOP_HT; 1555 else 1556 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1557 1558 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1559 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1560 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1561 txwi->xflags |= RT2860_TX_ACK; 1562 1563 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1564 dur = rt2860_rates[ridx].sp_ack_dur; 1565 else 1566 dur = rt2860_rates[ridx].lp_ack_dur; 1567 *(uint16_t *)wh->i_dur = htole16(dur); 1568 } 1569 /* ask MAC to insert timestamp into probe responses */ 1570 if ((wh->i_fc[0] & 1571 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1572 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1573 /* NOTE: beacons do not pass through tx_data() */ 1574 txwi->flags |= RT2860_TX_TS; 1575 1576 if (ieee80211_radiotap_active_vap(vap)) { 1577 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1578 1579 tap->wt_flags = 0; 1580 tap->wt_rate = rate; 1581 if (mcs & RT2860_PHY_SHPRE) 1582 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1583 1584 ieee80211_radiotap_tx(vap, m); 1585 } 1586 1587 pad = (hdrlen + 3) & ~3; 1588 1589 /* copy and trim 802.11 header */ 1590 memcpy(txwi + 1, wh, hdrlen); 1591 m_adj(m, hdrlen); 1592 1593 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1594 &nsegs, 0); 1595 if (__predict_false(error != 0 && error != EFBIG)) { 1596 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1597 error); 1598 m_freem(m); 1599 return error; 1600 } 1601 if (__predict_true(error == 0)) { 1602 /* determine how many TXDs are required */ 1603 ntxds = 1 + (nsegs / 2); 1604 1605 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1606 /* not enough free TXDs, force mbuf defrag */ 1607 bus_dmamap_unload(sc->txwi_dmat, data->map); 1608 error = EFBIG; 1609 } 1610 } 1611 if (__predict_false(error != 0)) { 1612 m1 = m_defrag(m, M_NOWAIT); 1613 if (m1 == NULL) { 1614 device_printf(sc->sc_dev, 1615 "could not defragment mbuf\n"); 1616 m_freem(m); 1617 return ENOBUFS; 1618 } 1619 m = m1; 1620 1621 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1622 segs, &nsegs, 0); 1623 if (__predict_false(error != 0)) { 1624 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1625 error); 1626 m_freem(m); 1627 return error; 1628 } 1629 1630 /* determine how many TXDs are now required */ 1631 ntxds = 1 + (nsegs / 2); 1632 1633 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1634 /* this is a hopeless case, drop the mbuf! */ 1635 bus_dmamap_unload(sc->txwi_dmat, data->map); 1636 m_freem(m); 1637 return ENOBUFS; 1638 } 1639 } 1640 1641 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1642 1643 /* first segment is TXWI + 802.11 header */ 1644 txd = &ring->txd[ring->cur]; 1645 txd->sdp0 = htole32(data->paddr); 1646 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1647 txd->flags = qsel; 1648 1649 /* setup payload segments */ 1650 seg = &segs[0]; 1651 for (i = nsegs; i >= 2; i -= 2) { 1652 txd->sdp1 = htole32(seg->ds_addr); 1653 txd->sdl1 = htole16(seg->ds_len); 1654 seg++; 1655 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1656 /* grab a new Tx descriptor */ 1657 txd = &ring->txd[ring->cur]; 1658 txd->sdp0 = htole32(seg->ds_addr); 1659 txd->sdl0 = htole16(seg->ds_len); 1660 txd->flags = qsel; 1661 seg++; 1662 } 1663 /* finalize last segment */ 1664 if (i > 0) { 1665 txd->sdp1 = htole32(seg->ds_addr); 1666 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1667 } else { 1668 txd->sdl0 |= htole16(RT2860_TX_LS0); 1669 txd->sdl1 = 0; 1670 } 1671 1672 /* remove from the free pool and link it into the SW Tx slot */ 1673 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1674 data->m = m; 1675 data->ni = ni; 1676 ring->data[ring->cur] = data; 1677 1678 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1679 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1680 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1681 1682 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1683 qid, txwi->wcid, nsegs, ridx)); 1684 1685 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1686 ring->queued += ntxds; 1687 if (ring->queued >= RT2860_TX_RING_COUNT) 1688 sc->qfullmsk |= 1 << qid; 1689 1690 /* kick Tx */ 1691 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1692 1693 return 0; 1694} 1695 1696static int 1697rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1698 const struct ieee80211_bpf_params *params) 1699{ 1700 struct ieee80211com *ic = ni->ni_ic; 1701 struct rt2860_softc *sc = ic->ic_softc; 1702 int error; 1703 1704 RAL_LOCK(sc); 1705 1706 /* prevent management frames from being sent if we're not ready */ 1707 if (!(sc->sc_flags & RT2860_RUNNING)) { 1708 RAL_UNLOCK(sc); 1709 m_freem(m); 1710 return ENETDOWN; 1711 } 1712 if (params == NULL) { 1713 /* 1714 * Legacy path; interpret frame contents to decide 1715 * precisely how to send the frame. 1716 */ 1717 error = rt2860_tx(sc, m, ni); 1718 } else { 1719 /* 1720 * Caller supplied explicit parameters to use in 1721 * sending the frame. 1722 */ 1723 error = rt2860_tx_raw(sc, m, ni, params); 1724 } 1725 sc->sc_tx_timer = 5; 1726 RAL_UNLOCK(sc); 1727 return error; 1728} 1729 1730static int 1731rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1732 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1733{ 1734 struct ieee80211com *ic = &sc->sc_ic; 1735 struct ieee80211vap *vap = ni->ni_vap; 1736 struct rt2860_tx_ring *ring; 1737 struct rt2860_tx_data *data; 1738 struct rt2860_txd *txd; 1739 struct rt2860_txwi *txwi; 1740 struct ieee80211_frame *wh; 1741 struct mbuf *m1; 1742 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1743 bus_dma_segment_t *seg; 1744 u_int hdrlen; 1745 uint16_t dur; 1746 uint8_t type, qsel, mcs, pid, tid, qid; 1747 int i, nsegs, ntxds, pad, rate, ridx, error; 1748 1749 /* the data pool contains at least one element, pick the first */ 1750 data = SLIST_FIRST(&sc->data_pool); 1751 1752 wh = mtod(m, struct ieee80211_frame *); 1753 hdrlen = ieee80211_hdrsize(wh); 1754 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1755 1756 /* Choose a TX rate index. */ 1757 rate = params->ibp_rate0; 1758 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1759 rate & IEEE80211_RATE_VAL); 1760 if (ridx == (uint8_t)-1) { 1761 /* XXX fall back to mcast/mgmt rate? */ 1762 m_freem(m); 1763 return EINVAL; 1764 } 1765 1766 qid = params->ibp_pri & 3; 1767 tid = 0; 1768 ring = &sc->txq[qid]; 1769 1770 /* get MCS code from rate index */ 1771 mcs = rt2860_rates[ridx].mcs; 1772 1773 /* setup TX Wireless Information */ 1774 txwi = data->txwi; 1775 txwi->flags = 0; 1776 /* let HW generate seq numbers for non-QoS frames */ 1777 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1778 txwi->wcid = 0xff; 1779 txwi->len = htole16(m->m_pkthdr.len); 1780 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1781 txwi->phy = htole16(RT2860_PHY_CCK); 1782 if (ridx != RT2860_RIDX_CCK1 && 1783 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1784 mcs |= RT2860_PHY_SHPRE; 1785 } else 1786 txwi->phy = htole16(RT2860_PHY_OFDM); 1787 txwi->phy |= htole16(mcs); 1788 1789 /* 1790 * We store the MCS code into the driver-private PacketID field. 1791 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1792 * that we know at which initial rate the frame was transmitted. 1793 * We add 1 to the MCS code because setting the PacketID field to 1794 * 0 means that we don't want feedback in TX_STAT_FIFO. 1795 */ 1796 pid = (mcs + 1) & 0xf; 1797 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1798 1799 /* check if RTS/CTS or CTS-to-self protection is required */ 1800 if (params->ibp_flags & IEEE80211_BPF_RTS || 1801 params->ibp_flags & IEEE80211_BPF_CTS) 1802 txwi->txop = RT2860_TX_TXOP_HT; 1803 else 1804 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1805 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1806 txwi->xflags |= RT2860_TX_ACK; 1807 1808 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1809 dur = rt2860_rates[ridx].sp_ack_dur; 1810 else 1811 dur = rt2860_rates[ridx].lp_ack_dur; 1812 *(uint16_t *)wh->i_dur = htole16(dur); 1813 } 1814 /* ask MAC to insert timestamp into probe responses */ 1815 if ((wh->i_fc[0] & 1816 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1817 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1818 /* NOTE: beacons do not pass through tx_data() */ 1819 txwi->flags |= RT2860_TX_TS; 1820 1821 if (ieee80211_radiotap_active_vap(vap)) { 1822 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1823 1824 tap->wt_flags = 0; 1825 tap->wt_rate = rate; 1826 if (mcs & RT2860_PHY_SHPRE) 1827 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1828 1829 ieee80211_radiotap_tx(vap, m); 1830 } 1831 1832 pad = (hdrlen + 3) & ~3; 1833 1834 /* copy and trim 802.11 header */ 1835 memcpy(txwi + 1, wh, hdrlen); 1836 m_adj(m, hdrlen); 1837 1838 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1839 &nsegs, 0); 1840 if (__predict_false(error != 0 && error != EFBIG)) { 1841 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1842 error); 1843 m_freem(m); 1844 return error; 1845 } 1846 if (__predict_true(error == 0)) { 1847 /* determine how many TXDs are required */ 1848 ntxds = 1 + (nsegs / 2); 1849 1850 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1851 /* not enough free TXDs, force mbuf defrag */ 1852 bus_dmamap_unload(sc->txwi_dmat, data->map); 1853 error = EFBIG; 1854 } 1855 } 1856 if (__predict_false(error != 0)) { 1857 m1 = m_defrag(m, M_NOWAIT); 1858 if (m1 == NULL) { 1859 device_printf(sc->sc_dev, 1860 "could not defragment mbuf\n"); 1861 m_freem(m); 1862 return ENOBUFS; 1863 } 1864 m = m1; 1865 1866 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1867 segs, &nsegs, 0); 1868 if (__predict_false(error != 0)) { 1869 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1870 error); 1871 m_freem(m); 1872 return error; 1873 } 1874 1875 /* determine how many TXDs are now required */ 1876 ntxds = 1 + (nsegs / 2); 1877 1878 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1879 /* this is a hopeless case, drop the mbuf! */ 1880 bus_dmamap_unload(sc->txwi_dmat, data->map); 1881 m_freem(m); 1882 return ENOBUFS; 1883 } 1884 } 1885 1886 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1887 1888 /* first segment is TXWI + 802.11 header */ 1889 txd = &ring->txd[ring->cur]; 1890 txd->sdp0 = htole32(data->paddr); 1891 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1892 txd->flags = qsel; 1893 1894 /* setup payload segments */ 1895 seg = &segs[0]; 1896 for (i = nsegs; i >= 2; i -= 2) { 1897 txd->sdp1 = htole32(seg->ds_addr); 1898 txd->sdl1 = htole16(seg->ds_len); 1899 seg++; 1900 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1901 /* grab a new Tx descriptor */ 1902 txd = &ring->txd[ring->cur]; 1903 txd->sdp0 = htole32(seg->ds_addr); 1904 txd->sdl0 = htole16(seg->ds_len); 1905 txd->flags = qsel; 1906 seg++; 1907 } 1908 /* finalize last segment */ 1909 if (i > 0) { 1910 txd->sdp1 = htole32(seg->ds_addr); 1911 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1912 } else { 1913 txd->sdl0 |= htole16(RT2860_TX_LS0); 1914 txd->sdl1 = 0; 1915 } 1916 1917 /* remove from the free pool and link it into the SW Tx slot */ 1918 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1919 data->m = m; 1920 data->ni = ni; 1921 ring->data[ring->cur] = data; 1922 1923 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1924 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1925 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1926 1927 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1928 qid, txwi->wcid, nsegs, ridx)); 1929 1930 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1931 ring->queued += ntxds; 1932 if (ring->queued >= RT2860_TX_RING_COUNT) 1933 sc->qfullmsk |= 1 << qid; 1934 1935 /* kick Tx */ 1936 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1937 1938 return 0; 1939} 1940 1941static int 1942rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1943{ 1944 struct rt2860_softc *sc = ic->ic_softc; 1945 int error; 1946 1947 RAL_LOCK(sc); 1948 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 1949 RAL_UNLOCK(sc); 1950 return (ENXIO); 1951 } 1952 error = mbufq_enqueue(&sc->sc_snd, m); 1953 if (error) { 1954 RAL_UNLOCK(sc); 1955 return (error); 1956 } 1957 rt2860_start(sc); 1958 RAL_UNLOCK(sc); 1959 1960 return (0); 1961} 1962 1963static void 1964rt2860_start(struct rt2860_softc *sc) 1965{ 1966 struct ieee80211_node *ni; 1967 struct mbuf *m; 1968 1969 RAL_LOCK_ASSERT(sc); 1970 1971 if ((sc->sc_flags & RT2860_RUNNING) == 0) 1972 return; 1973 1974 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1975 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1976 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1977 if (rt2860_tx(sc, m, ni) != 0) { 1978 if_inc_counter(ni->ni_vap->iv_ifp, 1979 IFCOUNTER_OERRORS, 1); 1980 ieee80211_free_node(ni); 1981 continue; 1982 } 1983 sc->sc_tx_timer = 5; 1984 } 1985} 1986 1987static void 1988rt2860_watchdog(void *arg) 1989{ 1990 struct rt2860_softc *sc = arg; 1991 1992 RAL_LOCK_ASSERT(sc); 1993 1994 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 1995 1996 if (sc->sc_invalid) /* card ejected */ 1997 return; 1998 1999 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 2000 device_printf(sc->sc_dev, "device timeout\n"); 2001 rt2860_stop_locked(sc); 2002 rt2860_init_locked(sc); 2003 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2004 return; 2005 } 2006 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2007} 2008 2009static void 2010rt2860_parent(struct ieee80211com *ic) 2011{ 2012 struct rt2860_softc *sc = ic->ic_softc; 2013 int startall = 0; 2014 2015 RAL_LOCK(sc); 2016 if (ic->ic_nrunning> 0) { 2017 if (!(sc->sc_flags & RT2860_RUNNING)) { 2018 rt2860_init_locked(sc); 2019 startall = 1; 2020 } else 2021 rt2860_update_promisc(ic); 2022 } else if (sc->sc_flags & RT2860_RUNNING) 2023 rt2860_stop_locked(sc); 2024 RAL_UNLOCK(sc); 2025 if (startall) 2026 ieee80211_start_all(ic); 2027} 2028 2029/* 2030 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2031 * We access the BBP through the 8051 microcontroller unit which means that 2032 * the microcode must be loaded first. 2033 */ 2034void 2035rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2036{ 2037 int ntries; 2038 2039 for (ntries = 0; ntries < 100; ntries++) { 2040 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2041 break; 2042 DELAY(1); 2043 } 2044 if (ntries == 100) { 2045 device_printf(sc->sc_dev, 2046 "could not write to BBP through MCU\n"); 2047 return; 2048 } 2049 2050 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2051 RT2860_BBP_CSR_KICK | reg << 8 | val); 2052 RAL_BARRIER_WRITE(sc); 2053 2054 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2055 DELAY(1000); 2056} 2057 2058uint8_t 2059rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2060{ 2061 uint32_t val; 2062 int ntries; 2063 2064 for (ntries = 0; ntries < 100; ntries++) { 2065 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2066 break; 2067 DELAY(1); 2068 } 2069 if (ntries == 100) { 2070 device_printf(sc->sc_dev, 2071 "could not read from BBP through MCU\n"); 2072 return 0; 2073 } 2074 2075 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2076 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2077 RAL_BARRIER_WRITE(sc); 2078 2079 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2080 DELAY(1000); 2081 2082 for (ntries = 0; ntries < 100; ntries++) { 2083 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2084 if (!(val & RT2860_BBP_CSR_KICK)) 2085 return val & 0xff; 2086 DELAY(1); 2087 } 2088 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2089 2090 return 0; 2091} 2092 2093/* 2094 * Write to one of the 4 programmable 24-bit RF registers. 2095 */ 2096static void 2097rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2098{ 2099 uint32_t tmp; 2100 int ntries; 2101 2102 for (ntries = 0; ntries < 100; ntries++) { 2103 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2104 break; 2105 DELAY(1); 2106 } 2107 if (ntries == 100) { 2108 device_printf(sc->sc_dev, "could not write to RF\n"); 2109 return; 2110 } 2111 2112 /* RF registers are 24-bit on the RT2860 */ 2113 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2114 (val & 0x3fffff) << 2 | (reg & 3); 2115 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2116} 2117 2118static uint8_t 2119rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2120{ 2121 uint32_t tmp; 2122 int ntries; 2123 2124 for (ntries = 0; ntries < 100; ntries++) { 2125 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2126 break; 2127 DELAY(1); 2128 } 2129 if (ntries == 100) { 2130 device_printf(sc->sc_dev, "could not read RF register\n"); 2131 return 0xff; 2132 } 2133 tmp = RT3070_RF_KICK | reg << 8; 2134 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2135 2136 for (ntries = 0; ntries < 100; ntries++) { 2137 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2138 if (!(tmp & RT3070_RF_KICK)) 2139 break; 2140 DELAY(1); 2141 } 2142 if (ntries == 100) { 2143 device_printf(sc->sc_dev, "could not read RF register\n"); 2144 return 0xff; 2145 } 2146 return tmp & 0xff; 2147} 2148 2149void 2150rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2151{ 2152 uint32_t tmp; 2153 int ntries; 2154 2155 for (ntries = 0; ntries < 10; ntries++) { 2156 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2157 break; 2158 DELAY(10); 2159 } 2160 if (ntries == 10) { 2161 device_printf(sc->sc_dev, "could not write to RF\n"); 2162 return; 2163 } 2164 2165 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2166 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2167} 2168 2169/* 2170 * Send a command to the 8051 microcontroller unit. 2171 */ 2172int 2173rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2174{ 2175 int slot, ntries; 2176 uint32_t tmp; 2177 uint8_t cid; 2178 2179 for (ntries = 0; ntries < 100; ntries++) { 2180 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2181 break; 2182 DELAY(2); 2183 } 2184 if (ntries == 100) 2185 return EIO; 2186 2187 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2188 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2189 RAL_BARRIER_WRITE(sc); 2190 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2191 2192 if (!wait) 2193 return 0; 2194 /* wait for the command to complete */ 2195 for (ntries = 0; ntries < 200; ntries++) { 2196 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2197 /* find the command slot */ 2198 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2199 if ((tmp & 0xff) == cid) 2200 break; 2201 if (slot < 4) 2202 break; 2203 DELAY(100); 2204 } 2205 if (ntries == 200) { 2206 /* clear command and status */ 2207 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2208 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2209 return ETIMEDOUT; 2210 } 2211 /* get command status (1 means success) */ 2212 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2213 tmp = (tmp >> (slot * 8)) & 0xff; 2214 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2215 cmd, slot, tmp)); 2216 /* clear command and status */ 2217 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2218 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2219 return (tmp == 1) ? 0 : EIO; 2220} 2221 2222static void 2223rt2860_enable_mrr(struct rt2860_softc *sc) 2224{ 2225#define CCK(mcs) (mcs) 2226#define OFDM(mcs) (1U << 3 | (mcs)) 2227 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2228 OFDM(6) << 28 | /* 54->48 */ 2229 OFDM(5) << 24 | /* 48->36 */ 2230 OFDM(4) << 20 | /* 36->24 */ 2231 OFDM(3) << 16 | /* 24->18 */ 2232 OFDM(2) << 12 | /* 18->12 */ 2233 OFDM(1) << 8 | /* 12-> 9 */ 2234 OFDM(0) << 4 | /* 9-> 6 */ 2235 OFDM(0)); /* 6-> 6 */ 2236 2237 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2238 CCK(2) << 12 | /* 11->5.5 */ 2239 CCK(1) << 8 | /* 5.5-> 2 */ 2240 CCK(0) << 4 | /* 2-> 1 */ 2241 CCK(0)); /* 1-> 1 */ 2242#undef OFDM 2243#undef CCK 2244} 2245 2246static void 2247rt2860_set_txpreamble(struct rt2860_softc *sc) 2248{ 2249 struct ieee80211com *ic = &sc->sc_ic; 2250 uint32_t tmp; 2251 2252 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2253 tmp &= ~RT2860_CCK_SHORT_EN; 2254 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2255 tmp |= RT2860_CCK_SHORT_EN; 2256 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2257} 2258 2259void 2260rt2860_set_basicrates(struct rt2860_softc *sc, 2261 const struct ieee80211_rateset *rs) 2262{ 2263 struct ieee80211com *ic = &sc->sc_ic; 2264 uint32_t mask = 0; 2265 uint8_t rate; 2266 int i; 2267 2268 for (i = 0; i < rs->rs_nrates; i++) { 2269 rate = rs->rs_rates[i]; 2270 2271 if (!(rate & IEEE80211_RATE_BASIC)) 2272 continue; 2273 2274 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2275 IEEE80211_RV(rate)); 2276 } 2277 2278 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2279} 2280 2281static void 2282rt2860_scan_start(struct ieee80211com *ic) 2283{ 2284 struct rt2860_softc *sc = ic->ic_softc; 2285 uint32_t tmp; 2286 2287 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2288 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2289 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2290 RT2860_TBTT_TIMER_EN)); 2291 rt2860_set_gp_timer(sc, 0); 2292} 2293 2294static void 2295rt2860_scan_end(struct ieee80211com *ic) 2296{ 2297 struct rt2860_softc *sc = ic->ic_softc; 2298 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2299 2300 if (vap->iv_state == IEEE80211_S_RUN) { 2301 rt2860_enable_tsf_sync(sc); 2302 rt2860_set_gp_timer(sc, 500); 2303 } 2304} 2305 2306static void 2307rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, 2308 struct ieee80211_channel chans[]) 2309{ 2310 struct rt2860_softc *sc = ic->ic_softc; 2311 uint8_t bands[IEEE80211_MODE_BYTES]; 2312 2313 memset(bands, 0, sizeof(bands)); 2314 setbit(bands, IEEE80211_MODE_11B); 2315 setbit(bands, IEEE80211_MODE_11G); 2316 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2317 2318 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 2319 setbit(bands, IEEE80211_MODE_11A); 2320 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2321 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0); 2322 } 2323} 2324 2325static void 2326rt2860_set_channel(struct ieee80211com *ic) 2327{ 2328 struct rt2860_softc *sc = ic->ic_softc; 2329 2330 RAL_LOCK(sc); 2331 rt2860_switch_chan(sc, ic->ic_curchan); 2332 RAL_UNLOCK(sc); 2333} 2334 2335static void 2336rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2337{ 2338 uint32_t tmp; 2339 uint8_t agc; 2340 2341 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2342 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2343 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2344 rt2860_mcu_bbp_write(sc, 86, 0x00); 2345 2346 if (group == 0) { 2347 if (sc->ext_2ghz_lna) { 2348 rt2860_mcu_bbp_write(sc, 82, 0x62); 2349 rt2860_mcu_bbp_write(sc, 75, 0x46); 2350 } else { 2351 rt2860_mcu_bbp_write(sc, 82, 0x84); 2352 rt2860_mcu_bbp_write(sc, 75, 0x50); 2353 } 2354 } else { 2355 if (sc->ext_5ghz_lna) { 2356 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2357 rt2860_mcu_bbp_write(sc, 75, 0x46); 2358 } else { 2359 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2360 rt2860_mcu_bbp_write(sc, 75, 0x50); 2361 } 2362 } 2363 2364 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2365 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2366 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2367 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2368 2369 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2370 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2371 if (sc->nrxchains > 1) 2372 tmp |= RT2860_LNA_PE1_EN; 2373 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2374 tmp |= RT3593_LNA_PE2_EN; 2375 if (group == 0) { /* 2GHz */ 2376 tmp |= RT2860_PA_PE_G0_EN; 2377 if (sc->ntxchains > 1) 2378 tmp |= RT2860_PA_PE_G1_EN; 2379 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2380 tmp |= RT3593_PA_PE_G2_EN; 2381 } else { /* 5GHz */ 2382 tmp |= RT2860_PA_PE_A0_EN; 2383 if (sc->ntxchains > 1) 2384 tmp |= RT2860_PA_PE_A1_EN; 2385 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2386 tmp |= RT3593_PA_PE_A2_EN; 2387 } 2388 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2389 2390 if (sc->mac_ver == 0x3593) { 2391 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2392 if (sc->sc_flags & RT2860_PCIE) { 2393 tmp &= ~0x01010000; 2394 if (group == 0) 2395 tmp |= 0x00010000; 2396 } else { 2397 tmp &= ~0x00008080; 2398 if (group == 0) 2399 tmp |= 0x00000080; 2400 } 2401 tmp = (tmp & ~0x00001000) | 0x00000010; 2402 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2403 } 2404 2405 /* set initial AGC value */ 2406 if (group == 0) { /* 2GHz band */ 2407 if (sc->mac_ver >= 0x3071) 2408 agc = 0x1c + sc->lna[0] * 2; 2409 else 2410 agc = 0x2e + sc->lna[0]; 2411 } else { /* 5GHz band */ 2412 agc = 0x32 + (sc->lna[group] * 5) / 3; 2413 } 2414 rt2860_mcu_bbp_write(sc, 66, agc); 2415 2416 DELAY(1000); 2417} 2418 2419static void 2420rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2421{ 2422 const struct rfprog *rfprog = rt2860_rf2850; 2423 uint32_t r2, r3, r4; 2424 int8_t txpow1, txpow2; 2425 u_int i; 2426 2427 /* find the settings for this channel (we know it exists) */ 2428 for (i = 0; rfprog[i].chan != chan; i++); 2429 2430 r2 = rfprog[i].r2; 2431 if (sc->ntxchains == 1) 2432 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2433 if (sc->nrxchains == 1) 2434 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2435 else if (sc->nrxchains == 2) 2436 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2437 2438 /* use Tx power values from EEPROM */ 2439 txpow1 = sc->txpow1[i]; 2440 txpow2 = sc->txpow2[i]; 2441 if (chan > 14) { 2442 if (txpow1 >= 0) 2443 txpow1 = txpow1 << 1 | 1; 2444 else 2445 txpow1 = (7 + txpow1) << 1; 2446 if (txpow2 >= 0) 2447 txpow2 = txpow2 << 1 | 1; 2448 else 2449 txpow2 = (7 + txpow2) << 1; 2450 } 2451 r3 = rfprog[i].r3 | txpow1 << 7; 2452 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2453 2454 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2455 rt2860_rf_write(sc, RT2860_RF2, r2); 2456 rt2860_rf_write(sc, RT2860_RF3, r3); 2457 rt2860_rf_write(sc, RT2860_RF4, r4); 2458 2459 DELAY(200); 2460 2461 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2462 rt2860_rf_write(sc, RT2860_RF2, r2); 2463 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2464 rt2860_rf_write(sc, RT2860_RF4, r4); 2465 2466 DELAY(200); 2467 2468 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2469 rt2860_rf_write(sc, RT2860_RF2, r2); 2470 rt2860_rf_write(sc, RT2860_RF3, r3); 2471 rt2860_rf_write(sc, RT2860_RF4, r4); 2472} 2473 2474static void 2475rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2476{ 2477 int8_t txpow1, txpow2; 2478 uint8_t rf; 2479 int i; 2480 2481 /* RT3090 is 2GHz only */ 2482 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2483 2484 /* find the settings for this channel (we know it exists) */ 2485 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2486 2487 /* use Tx power values from EEPROM */ 2488 txpow1 = sc->txpow1[i]; 2489 txpow2 = sc->txpow2[i]; 2490 2491 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2492 rf = rt3090_rf_read(sc, 3); 2493 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2494 rt3090_rf_write(sc, 3, rf); 2495 rf = rt3090_rf_read(sc, 6); 2496 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2497 rt3090_rf_write(sc, 6, rf); 2498 2499 /* set Tx0 power */ 2500 rf = rt3090_rf_read(sc, 12); 2501 rf = (rf & ~0x1f) | txpow1; 2502 rt3090_rf_write(sc, 12, rf); 2503 2504 /* set Tx1 power */ 2505 rf = rt3090_rf_read(sc, 13); 2506 rf = (rf & ~0x1f) | txpow2; 2507 rt3090_rf_write(sc, 13, rf); 2508 2509 rf = rt3090_rf_read(sc, 1); 2510 rf &= ~0xfc; 2511 if (sc->ntxchains == 1) 2512 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2513 else if (sc->ntxchains == 2) 2514 rf |= RT3070_TX2_PD; 2515 if (sc->nrxchains == 1) 2516 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2517 else if (sc->nrxchains == 2) 2518 rf |= RT3070_RX2_PD; 2519 rt3090_rf_write(sc, 1, rf); 2520 2521 /* set RF offset */ 2522 rf = rt3090_rf_read(sc, 23); 2523 rf = (rf & ~0x7f) | sc->freq; 2524 rt3090_rf_write(sc, 23, rf); 2525 2526 /* program RF filter */ 2527 rf = rt3090_rf_read(sc, 24); /* Tx */ 2528 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2529 rt3090_rf_write(sc, 24, rf); 2530 rf = rt3090_rf_read(sc, 31); /* Rx */ 2531 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2532 rt3090_rf_write(sc, 31, rf); 2533 2534 /* enable RF tuning */ 2535 rf = rt3090_rf_read(sc, 7); 2536 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2537} 2538 2539static void 2540rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2541{ 2542 uint8_t h20mhz, rf, tmp; 2543 int8_t txpow1, txpow2; 2544 int i; 2545 2546 /* RT5390 is 2GHz only */ 2547 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2548 2549 /* find the settings for this channel (we know it exists) */ 2550 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2551 2552 /* use Tx power values from EEPROM */ 2553 txpow1 = sc->txpow1[i]; 2554 txpow2 = sc->txpow2[i]; 2555 2556 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2557 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2558 rf = rt3090_rf_read(sc, 11); 2559 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2560 rt3090_rf_write(sc, 11, rf); 2561 2562 rf = rt3090_rf_read(sc, 49); 2563 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2564 /* the valid range of the RF R49 is 0x00~0x27 */ 2565 if ((rf & 0x3f) > 0x27) 2566 rf = (rf & ~0x3f) | 0x27; 2567 rt3090_rf_write(sc, 49, rf); 2568 if (sc->mac_ver == 0x5392) { 2569 rf = rt3090_rf_read(sc, 50); 2570 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2571 /* the valid range of the RF R50 is 0x00~0x27 */ 2572 if ((rf & 0x3f) > 0x27) 2573 rf = (rf & ~0x3f) | 0x27; 2574 rt3090_rf_write(sc, 50, rf); 2575 } 2576 2577 rf = rt3090_rf_read(sc, 1); 2578 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2579 if (sc->mac_ver == 0x5392) 2580 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2581 rt3090_rf_write(sc, 1, rf); 2582 2583 rf = rt3090_rf_read(sc, 2); 2584 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2585 DELAY(1000); 2586 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2587 2588 rf = rt3090_rf_read(sc, 17); 2589 tmp = rf; 2590 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2591 rf = MIN(rf, 0x5f); 2592 if (tmp != rf) 2593 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2594 2595 if (sc->mac_ver == 0x5390) { 2596 if (chan <= 4) 2597 rf = 0x73; 2598 else if (chan >= 5 && chan <= 6) 2599 rf = 0x63; 2600 else if (chan >= 7 && chan <= 10) 2601 rf = 0x53; 2602 else 2603 rf = 43; 2604 rt3090_rf_write(sc, 55, rf); 2605 2606 if (chan == 1) 2607 rf = 0x0c; 2608 else if (chan == 2) 2609 rf = 0x0b; 2610 else if (chan == 3) 2611 rf = 0x0a; 2612 else if (chan >= 4 && chan <= 6) 2613 rf = 0x09; 2614 else if (chan >= 7 && chan <= 12) 2615 rf = 0x08; 2616 else if (chan == 13) 2617 rf = 0x07; 2618 else 2619 rf = 0x06; 2620 rt3090_rf_write(sc, 59, rf); 2621 } 2622 2623 /* Tx/Rx h20M */ 2624 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2625 rf = rt3090_rf_read(sc, 30); 2626 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2627 rt3090_rf_write(sc, 30, rf); 2628 2629 /* Rx BB filter VCM */ 2630 rf = rt3090_rf_read(sc, 30); 2631 rf = (rf & ~0x18) | 0x10; 2632 rt3090_rf_write(sc, 30, rf); 2633 2634 /* Initiate VCO calibration. */ 2635 rf = rt3090_rf_read(sc, 3); 2636 rf |= RT3593_VCOCAL; 2637 rt3090_rf_write(sc, 3, rf); 2638} 2639 2640static int 2641rt3090_rf_init(struct rt2860_softc *sc) 2642{ 2643 uint32_t tmp; 2644 uint8_t rf, bbp; 2645 int i; 2646 2647 rf = rt3090_rf_read(sc, 30); 2648 /* toggle RF R30 bit 7 */ 2649 rt3090_rf_write(sc, 30, rf | 0x80); 2650 DELAY(1000); 2651 rt3090_rf_write(sc, 30, rf & ~0x80); 2652 2653 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2654 tmp &= ~0x1f000000; 2655 if (sc->patch_dac && sc->mac_rev < 0x0211) 2656 tmp |= 0x0d000000; /* 1.35V */ 2657 else 2658 tmp |= 0x01000000; /* 1.2V */ 2659 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2660 2661 /* patch LNA_PE_G1 */ 2662 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2663 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2664 2665 /* initialize RF registers to default value */ 2666 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2667 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2668 rt3090_def_rf[i].val); 2669 } 2670 2671 /* select 20MHz bandwidth */ 2672 rt3090_rf_write(sc, 31, 0x14); 2673 2674 rf = rt3090_rf_read(sc, 6); 2675 rt3090_rf_write(sc, 6, rf | 0x40); 2676 2677 if (sc->mac_ver != 0x3593) { 2678 /* calibrate filter for 20MHz bandwidth */ 2679 sc->rf24_20mhz = 0x1f; /* default value */ 2680 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2681 2682 /* select 40MHz bandwidth */ 2683 bbp = rt2860_mcu_bbp_read(sc, 4); 2684 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2685 rf = rt3090_rf_read(sc, 31); 2686 rt3090_rf_write(sc, 31, rf | 0x20); 2687 2688 /* calibrate filter for 40MHz bandwidth */ 2689 sc->rf24_40mhz = 0x2f; /* default value */ 2690 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2691 2692 /* go back to 20MHz bandwidth */ 2693 bbp = rt2860_mcu_bbp_read(sc, 4); 2694 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2695 } 2696 if (sc->mac_rev < 0x0211) 2697 rt3090_rf_write(sc, 27, 0x03); 2698 2699 tmp = RAL_READ(sc, RT3070_OPT_14); 2700 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2701 2702 if (sc->rf_rev == RT3070_RF_3020) 2703 rt3090_set_rx_antenna(sc, 0); 2704 2705 bbp = rt2860_mcu_bbp_read(sc, 138); 2706 if (sc->mac_ver == 0x3593) { 2707 if (sc->ntxchains == 1) 2708 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2709 else if (sc->ntxchains == 2) 2710 bbp |= 0x40; /* turn off DAC2 */ 2711 if (sc->nrxchains == 1) 2712 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2713 else if (sc->nrxchains == 2) 2714 bbp &= ~0x04; /* turn off ADC2 */ 2715 } else { 2716 if (sc->ntxchains == 1) 2717 bbp |= 0x20; /* turn off DAC1 */ 2718 if (sc->nrxchains == 1) 2719 bbp &= ~0x02; /* turn off ADC1 */ 2720 } 2721 rt2860_mcu_bbp_write(sc, 138, bbp); 2722 2723 rf = rt3090_rf_read(sc, 1); 2724 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2725 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2726 rt3090_rf_write(sc, 1, rf); 2727 2728 rf = rt3090_rf_read(sc, 15); 2729 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2730 2731 rf = rt3090_rf_read(sc, 17); 2732 rf &= ~RT3070_TX_LO1; 2733 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2734 rf |= 0x20; /* fix for long range Rx issue */ 2735 if (sc->txmixgain_2ghz >= 2) 2736 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2737 rt3090_rf_write(sc, 17, rf); 2738 2739 rf = rt3090_rf_read(sc, 20); 2740 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2741 2742 rf = rt3090_rf_read(sc, 21); 2743 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2744 2745 return (0); 2746} 2747 2748static void 2749rt5390_rf_init(struct rt2860_softc *sc) 2750{ 2751 uint8_t rf, bbp; 2752 int i; 2753 2754 rf = rt3090_rf_read(sc, 2); 2755 /* Toggle RF R2 bit 7. */ 2756 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2757 DELAY(1000); 2758 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2759 2760 /* Initialize RF registers to default value. */ 2761 if (sc->mac_ver == 0x5392) { 2762 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2763 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2764 rt5392_def_rf[i].val); 2765 } 2766 } else { 2767 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2768 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2769 rt5390_def_rf[i].val); 2770 } 2771 } 2772 2773 sc->rf24_20mhz = 0x1f; 2774 sc->rf24_40mhz = 0x2f; 2775 2776 if (sc->mac_rev < 0x0211) 2777 rt3090_rf_write(sc, 27, 0x03); 2778 2779 /* Set led open drain enable. */ 2780 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2781 2782 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2783 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2784 2785 if (sc->mac_ver == 0x5390) 2786 rt3090_set_rx_antenna(sc, 0); 2787 2788 /* Patch RSSI inaccurate issue. */ 2789 rt2860_mcu_bbp_write(sc, 79, 0x13); 2790 rt2860_mcu_bbp_write(sc, 80, 0x05); 2791 rt2860_mcu_bbp_write(sc, 81, 0x33); 2792 2793 /* Enable DC filter. */ 2794 if (sc->mac_rev >= 0x0211) 2795 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2796 2797 bbp = rt2860_mcu_bbp_read(sc, 138); 2798 if (sc->ntxchains == 1) 2799 bbp |= 0x20; /* Turn off DAC1. */ 2800 if (sc->nrxchains == 1) 2801 bbp &= ~0x02; /* Turn off ADC1. */ 2802 rt2860_mcu_bbp_write(sc, 138, bbp); 2803 2804 /* Enable RX LO1 and LO2. */ 2805 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2806 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2807 2808 /* Avoid data lost and CRC error. */ 2809 rt2860_mcu_bbp_write(sc, 4, 2810 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2811 2812 rf = rt3090_rf_read(sc, 30); 2813 rf = (rf & ~0x18) | 0x10; 2814 rt3090_rf_write(sc, 30, rf); 2815} 2816 2817static void 2818rt3090_rf_wakeup(struct rt2860_softc *sc) 2819{ 2820 uint32_t tmp; 2821 uint8_t rf; 2822 2823 if (sc->mac_ver == 0x3593) { 2824 /* enable VCO */ 2825 rf = rt3090_rf_read(sc, 1); 2826 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2827 2828 /* initiate VCO calibration */ 2829 rf = rt3090_rf_read(sc, 3); 2830 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2831 2832 /* enable VCO bias current control */ 2833 rf = rt3090_rf_read(sc, 6); 2834 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2835 2836 /* initiate res calibration */ 2837 rf = rt3090_rf_read(sc, 2); 2838 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2839 2840 /* set reference current control to 0.33 mA */ 2841 rf = rt3090_rf_read(sc, 22); 2842 rf &= ~RT3593_CP_IC_MASK; 2843 rf |= 1 << RT3593_CP_IC_SHIFT; 2844 rt3090_rf_write(sc, 22, rf); 2845 2846 /* enable RX CTB */ 2847 rf = rt3090_rf_read(sc, 46); 2848 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2849 2850 rf = rt3090_rf_read(sc, 20); 2851 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2852 rt3090_rf_write(sc, 20, rf); 2853 } else { 2854 /* enable RF block */ 2855 rf = rt3090_rf_read(sc, 1); 2856 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2857 2858 /* enable VCO bias current control */ 2859 rf = rt3090_rf_read(sc, 7); 2860 rt3090_rf_write(sc, 7, rf | 0x30); 2861 2862 rf = rt3090_rf_read(sc, 9); 2863 rt3090_rf_write(sc, 9, rf | 0x0e); 2864 2865 /* enable RX CTB */ 2866 rf = rt3090_rf_read(sc, 21); 2867 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2868 2869 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2870 rf = rt3090_rf_read(sc, 27); 2871 rf &= ~0x77; 2872 if (sc->mac_rev < 0x0211) 2873 rf |= 0x03; 2874 rt3090_rf_write(sc, 27, rf); 2875 } 2876 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2877 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2878 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2879 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2880 } 2881} 2882 2883static void 2884rt5390_rf_wakeup(struct rt2860_softc *sc) 2885{ 2886 uint32_t tmp; 2887 uint8_t rf; 2888 2889 rf = rt3090_rf_read(sc, 1); 2890 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2891 RT3070_TX0_PD; 2892 if (sc->mac_ver == 0x5392) 2893 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2894 rt3090_rf_write(sc, 1, rf); 2895 2896 rf = rt3090_rf_read(sc, 6); 2897 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2898 if (sc->mac_ver == 0x5390) 2899 rf &= ~RT3593_VCO_IC; 2900 rt3090_rf_write(sc, 6, rf); 2901 2902 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2903 2904 rf = rt3090_rf_read(sc, 22); 2905 rf = (rf & ~0xe0) | 0x20; 2906 rt3090_rf_write(sc, 22, rf); 2907 2908 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2909 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2910 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2911 2912 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2913 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2914 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2915 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2916 } 2917} 2918 2919static int 2920rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2921 uint8_t *val) 2922{ 2923 uint8_t rf22, rf24; 2924 uint8_t bbp55_pb, bbp55_sb, delta; 2925 int ntries; 2926 2927 /* program filter */ 2928 rf24 = rt3090_rf_read(sc, 24); 2929 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2930 rt3090_rf_write(sc, 24, rf24); 2931 2932 /* enable baseband loopback mode */ 2933 rf22 = rt3090_rf_read(sc, 22); 2934 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2935 2936 /* set power and frequency of passband test tone */ 2937 rt2860_mcu_bbp_write(sc, 24, 0x00); 2938 for (ntries = 0; ntries < 100; ntries++) { 2939 /* transmit test tone */ 2940 rt2860_mcu_bbp_write(sc, 25, 0x90); 2941 DELAY(1000); 2942 /* read received power */ 2943 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2944 if (bbp55_pb != 0) 2945 break; 2946 } 2947 if (ntries == 100) 2948 return (ETIMEDOUT); 2949 2950 /* set power and frequency of stopband test tone */ 2951 rt2860_mcu_bbp_write(sc, 24, 0x06); 2952 for (ntries = 0; ntries < 100; ntries++) { 2953 /* transmit test tone */ 2954 rt2860_mcu_bbp_write(sc, 25, 0x90); 2955 DELAY(1000); 2956 /* read received power */ 2957 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2958 2959 delta = bbp55_pb - bbp55_sb; 2960 if (delta > target) 2961 break; 2962 2963 /* reprogram filter */ 2964 rf24++; 2965 rt3090_rf_write(sc, 24, rf24); 2966 } 2967 if (ntries < 100) { 2968 if (rf24 != init) 2969 rf24--; /* backtrack */ 2970 *val = rf24; 2971 rt3090_rf_write(sc, 24, rf24); 2972 } 2973 2974 /* restore initial state */ 2975 rt2860_mcu_bbp_write(sc, 24, 0x00); 2976 2977 /* disable baseband loopback mode */ 2978 rf22 = rt3090_rf_read(sc, 22); 2979 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2980 2981 return (0); 2982} 2983 2984static void 2985rt3090_rf_setup(struct rt2860_softc *sc) 2986{ 2987 uint8_t bbp; 2988 int i; 2989 2990 if (sc->mac_rev >= 0x0211) { 2991 /* enable DC filter */ 2992 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2993 2994 /* improve power consumption */ 2995 bbp = rt2860_mcu_bbp_read(sc, 31); 2996 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2997 } 2998 2999 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 3000 if (sc->mac_rev < 0x0211) { 3001 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 3002 sc->patch_dac ? 0x2c : 0x0f); 3003 } else 3004 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 3005 3006 /* initialize RF registers from ROM */ 3007 if (sc->mac_ver < 0x5390) { 3008 for (i = 0; i < 10; i++) { 3009 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 3010 continue; 3011 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3012 } 3013 } 3014} 3015 3016static void 3017rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3018{ 3019 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3020 which | (sc->leds & 0x7f), 0); 3021} 3022 3023/* 3024 * Hardware has a general-purpose programmable timer interrupt that can 3025 * periodically raise MAC_INT_4. 3026 */ 3027static void 3028rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3029{ 3030 uint32_t tmp; 3031 3032 /* disable GP timer before reprogramming it */ 3033 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3034 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3035 3036 if (ms == 0) 3037 return; 3038 3039 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3040 ms *= 16; /* Unit: 64us */ 3041 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3042 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3043 3044 /* enable GP timer */ 3045 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3046 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3047} 3048 3049static void 3050rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3051{ 3052 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3053 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3054 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3055 bssid[4] | bssid[5] << 8); 3056} 3057 3058static void 3059rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3060{ 3061 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3062 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3063 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3064 addr[4] | addr[5] << 8 | 0xff << 16); 3065} 3066 3067static void 3068rt2860_updateslot(struct ieee80211com *ic) 3069{ 3070 struct rt2860_softc *sc = ic->ic_softc; 3071 uint32_t tmp; 3072 3073 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3074 tmp &= ~0xff; 3075 tmp |= IEEE80211_GET_SLOTTIME(ic); 3076 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3077} 3078 3079static void 3080rt2860_updateprot(struct rt2860_softc *sc) 3081{ 3082 struct ieee80211com *ic = &sc->sc_ic; 3083 uint32_t tmp; 3084 3085 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3086 /* setup protection frame rate (MCS code) */ 3087 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3088 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3089 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3090 3091 /* CCK frames don't require protection */ 3092 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3093 3094 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3095 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3096 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3097 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3098 tmp |= RT2860_PROT_CTRL_CTS; 3099 } 3100 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3101} 3102 3103static void 3104rt2860_update_promisc(struct ieee80211com *ic) 3105{ 3106 struct rt2860_softc *sc = ic->ic_softc; 3107 uint32_t tmp; 3108 3109 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3110 tmp &= ~RT2860_DROP_NOT_MYBSS; 3111 if (ic->ic_promisc == 0) 3112 tmp |= RT2860_DROP_NOT_MYBSS; 3113 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3114} 3115 3116static int 3117rt2860_updateedca(struct ieee80211com *ic) 3118{ 3119 struct rt2860_softc *sc = ic->ic_softc; 3120 struct chanAccParams chp; 3121 const struct wmeParams *wmep; 3122 int aci; 3123 3124 ieee80211_wme_ic_getparams(ic, &chp); 3125 3126 wmep = chp.cap_wmeParams; 3127 3128 /* update MAC TX configuration registers */ 3129 for (aci = 0; aci < WME_NUM_AC; aci++) { 3130 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3131 wmep[aci].wmep_logcwmax << 16 | 3132 wmep[aci].wmep_logcwmin << 12 | 3133 wmep[aci].wmep_aifsn << 8 | 3134 wmep[aci].wmep_txopLimit); 3135 } 3136 3137 /* update SCH/DMA registers too */ 3138 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3139 wmep[WME_AC_VO].wmep_aifsn << 12 | 3140 wmep[WME_AC_VI].wmep_aifsn << 8 | 3141 wmep[WME_AC_BK].wmep_aifsn << 4 | 3142 wmep[WME_AC_BE].wmep_aifsn); 3143 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3144 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3145 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3146 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3147 wmep[WME_AC_BE].wmep_logcwmin); 3148 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3149 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3150 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3151 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3152 wmep[WME_AC_BE].wmep_logcwmax); 3153 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3154 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3155 wmep[WME_AC_BE].wmep_txopLimit); 3156 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3157 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3158 wmep[WME_AC_VI].wmep_txopLimit); 3159 3160 return 0; 3161} 3162 3163#ifdef HW_CRYPTO 3164static int 3165rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3166 struct ieee80211_key *k) 3167{ 3168 struct rt2860_softc *sc = ic->ic_softc; 3169 bus_size_t base; 3170 uint32_t attr; 3171 uint8_t mode, wcid, iv[8]; 3172 3173 /* defer setting of WEP keys until interface is brought up */ 3174 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3175 (IFF_UP | IFF_RUNNING)) 3176 return 0; 3177 3178 /* map net80211 cipher to RT2860 security mode */ 3179 switch (k->k_cipher) { 3180 case IEEE80211_CIPHER_WEP40: 3181 mode = RT2860_MODE_WEP40; 3182 break; 3183 case IEEE80211_CIPHER_WEP104: 3184 mode = RT2860_MODE_WEP104; 3185 break; 3186 case IEEE80211_CIPHER_TKIP: 3187 mode = RT2860_MODE_TKIP; 3188 break; 3189 case IEEE80211_CIPHER_CCMP: 3190 mode = RT2860_MODE_AES_CCMP; 3191 break; 3192 default: 3193 return EINVAL; 3194 } 3195 3196 if (k->k_flags & IEEE80211_KEY_GROUP) { 3197 wcid = 0; /* NB: update WCID0 for group keys */ 3198 base = RT2860_SKEY(0, k->k_id); 3199 } else { 3200 wcid = ((struct rt2860_node *)ni)->wcid; 3201 base = RT2860_PKEY(wcid); 3202 } 3203 3204 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3205 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3206#ifndef IEEE80211_STA_ONLY 3207 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3208 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3209 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3210 } else 3211#endif 3212 { 3213 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3214 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3215 } 3216 } else 3217 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3218 3219 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3220 (k->k_flags & IEEE80211_KEY_TX)) { 3221 /* set initial packet number in IV+EIV */ 3222 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3223 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3224 uint32_t val = arc4random(); 3225 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3226 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3227 val += 0x000100; 3228 iv[0] = val; 3229 iv[1] = val >> 8; 3230 iv[2] = val >> 16; 3231 iv[3] = k->k_id << 6; 3232 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3233 } else { 3234 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3235 iv[0] = k->k_tsc >> 8; 3236 iv[1] = (iv[0] | 0x20) & 0x7f; 3237 iv[2] = k->k_tsc; 3238 } else /* CCMP */ { 3239 iv[0] = k->k_tsc; 3240 iv[1] = k->k_tsc >> 8; 3241 iv[2] = 0; 3242 } 3243 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3244 iv[4] = k->k_tsc >> 16; 3245 iv[5] = k->k_tsc >> 24; 3246 iv[6] = k->k_tsc >> 32; 3247 iv[7] = k->k_tsc >> 40; 3248 } 3249 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3250 } 3251 3252 if (k->k_flags & IEEE80211_KEY_GROUP) { 3253 /* install group key */ 3254 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3255 attr &= ~(0xf << (k->k_id * 4)); 3256 attr |= mode << (k->k_id * 4); 3257 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3258 } else { 3259 /* install pairwise key */ 3260 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3261 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3262 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3263 } 3264 return 0; 3265} 3266 3267static void 3268rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3269 struct ieee80211_key *k) 3270{ 3271 struct rt2860_softc *sc = ic->ic_softc; 3272 uint32_t attr; 3273 uint8_t wcid; 3274 3275 if (k->k_flags & IEEE80211_KEY_GROUP) { 3276 /* remove group key */ 3277 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3278 attr &= ~(0xf << (k->k_id * 4)); 3279 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3280 3281 } else { 3282 /* remove pairwise key */ 3283 wcid = ((struct rt2860_node *)ni)->wcid; 3284 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3285 attr &= ~0xf; 3286 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3287 } 3288} 3289#endif 3290 3291static int8_t 3292rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3293{ 3294 struct ieee80211com *ic = &sc->sc_ic; 3295 struct ieee80211_channel *c = ic->ic_curchan; 3296 int delta; 3297 3298 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3299 u_int chan = ieee80211_chan2ieee(ic, c); 3300 delta = sc->rssi_5ghz[rxchain]; 3301 3302 /* determine channel group */ 3303 if (chan <= 64) 3304 delta -= sc->lna[1]; 3305 else if (chan <= 128) 3306 delta -= sc->lna[2]; 3307 else 3308 delta -= sc->lna[3]; 3309 } else 3310 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3311 3312 return -12 - delta - rssi; 3313} 3314 3315/* 3316 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3317 * Used to adjust per-rate Tx power registers. 3318 */ 3319static __inline uint32_t 3320b4inc(uint32_t b32, int8_t delta) 3321{ 3322 int8_t i, b4; 3323 3324 for (i = 0; i < 8; i++) { 3325 b4 = b32 & 0xf; 3326 b4 += delta; 3327 if (b4 < 0) 3328 b4 = 0; 3329 else if (b4 > 0xf) 3330 b4 = 0xf; 3331 b32 = b32 >> 4 | (uint32_t)b4 << 28; 3332 } 3333 return b32; 3334} 3335 3336static const char * 3337rt2860_get_rf(uint16_t rev) 3338{ 3339 switch (rev) { 3340 case RT2860_RF_2820: return "RT2820"; 3341 case RT2860_RF_2850: return "RT2850"; 3342 case RT2860_RF_2720: return "RT2720"; 3343 case RT2860_RF_2750: return "RT2750"; 3344 case RT3070_RF_3020: return "RT3020"; 3345 case RT3070_RF_2020: return "RT2020"; 3346 case RT3070_RF_3021: return "RT3021"; 3347 case RT3070_RF_3022: return "RT3022"; 3348 case RT3070_RF_3052: return "RT3052"; 3349 case RT3070_RF_3320: return "RT3320"; 3350 case RT3070_RF_3053: return "RT3053"; 3351 case RT5390_RF_5360: return "RT5360"; 3352 case RT5390_RF_5390: return "RT5390"; 3353 default: return "unknown"; 3354 } 3355} 3356 3357static int 3358rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3359{ 3360 int8_t delta_2ghz, delta_5ghz; 3361 uint32_t tmp; 3362 uint16_t val; 3363 int ridx, ant, i; 3364 3365 /* check whether the ROM is eFUSE ROM or EEPROM */ 3366 sc->sc_srom_read = rt2860_eeprom_read_2; 3367 if (sc->mac_ver >= 0x3071) { 3368 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3369 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3370 if (tmp & RT3070_SEL_EFUSE) 3371 sc->sc_srom_read = rt3090_efuse_read_2; 3372 } 3373 3374#ifdef RAL_DEBUG 3375 /* read EEPROM version */ 3376 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3377 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3378#endif 3379 3380 /* read MAC address */ 3381 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3382 macaddr[0] = val & 0xff; 3383 macaddr[1] = val >> 8; 3384 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3385 macaddr[2] = val & 0xff; 3386 macaddr[3] = val >> 8; 3387 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3388 macaddr[4] = val & 0xff; 3389 macaddr[5] = val >> 8; 3390 3391#ifdef RAL_DEBUG 3392 /* read country code */ 3393 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3394 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3395#endif 3396 3397 /* read vendor BBP settings */ 3398 for (i = 0; i < 8; i++) { 3399 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3400 sc->bbp[i].val = val & 0xff; 3401 sc->bbp[i].reg = val >> 8; 3402 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3403 } 3404 if (sc->mac_ver >= 0x3071) { 3405 /* read vendor RF settings */ 3406 for (i = 0; i < 10; i++) { 3407 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3408 sc->rf[i].val = val & 0xff; 3409 sc->rf[i].reg = val >> 8; 3410 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3411 sc->rf[i].val)); 3412 } 3413 } 3414 3415 /* read RF frequency offset from EEPROM */ 3416 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3417 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3418 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3419 if ((val >> 8) != 0xff) { 3420 /* read LEDs operating mode */ 3421 sc->leds = val >> 8; 3422 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3423 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3424 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3425 } else { 3426 /* broken EEPROM, use default settings */ 3427 sc->leds = 0x01; 3428 sc->led[0] = 0x5555; 3429 sc->led[1] = 0x2221; 3430 sc->led[2] = 0xa9f8; 3431 } 3432 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3433 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3434 3435 /* read RF information */ 3436 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3437 if (sc->mac_ver >= 0x5390) 3438 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3439 else 3440 sc->rf_rev = (val >> 8) & 0xf; 3441 sc->ntxchains = (val >> 4) & 0xf; 3442 sc->nrxchains = val & 0xf; 3443 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3444 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3445 3446 /* check if RF supports automatic Tx access gain control */ 3447 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3448 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3449 /* check if driver should patch the DAC issue */ 3450 if ((val >> 8) != 0xff) 3451 sc->patch_dac = (val >> 15) & 1; 3452 if ((val & 0xff) != 0xff) { 3453 sc->ext_5ghz_lna = (val >> 3) & 1; 3454 sc->ext_2ghz_lna = (val >> 2) & 1; 3455 /* check if RF supports automatic Tx access gain control */ 3456 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3457 /* check if we have a hardware radio switch */ 3458 sc->rfswitch = val & 1; 3459 } 3460 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3461 /* read PCIe power save level */ 3462 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3463 if ((val & 0xff) != 0xff) { 3464 sc->pslevel = val & 0x3; 3465 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3466 if ((val & 0xff80) != 0x9280) 3467 sc->pslevel = MIN(sc->pslevel, 1); 3468 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3469 } 3470 } 3471 3472 /* read power settings for 2GHz channels */ 3473 for (i = 0; i < 14; i += 2) { 3474 val = rt2860_srom_read(sc, 3475 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3476 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3477 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3478 3479 if (sc->mac_ver != 0x5390) { 3480 val = rt2860_srom_read(sc, 3481 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3482 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3483 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3484 } 3485 } 3486 /* fix broken Tx power entries */ 3487 for (i = 0; i < 14; i++) { 3488 if (sc->txpow1[i] < 0 || 3489 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3490 sc->txpow1[i] = 5; 3491 if (sc->mac_ver != 0x5390) { 3492 if (sc->txpow2[i] < 0 || 3493 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3494 sc->txpow2[i] = 5; 3495 } 3496 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3497 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3498 } 3499 /* read power settings for 5GHz channels */ 3500 for (i = 0; i < 40; i += 2) { 3501 val = rt2860_srom_read(sc, 3502 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3503 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3504 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3505 3506 val = rt2860_srom_read(sc, 3507 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3508 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3509 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3510 } 3511 /* fix broken Tx power entries */ 3512 for (i = 0; i < 40; i++) { 3513 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3514 sc->txpow1[14 + i] = 5; 3515 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3516 sc->txpow2[14 + i] = 5; 3517 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3518 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3519 sc->txpow2[14 + i])); 3520 } 3521 3522 /* read Tx power compensation for each Tx rate */ 3523 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3524 delta_2ghz = delta_5ghz = 0; 3525 if ((val & 0xff) != 0xff && (val & 0x80)) { 3526 delta_2ghz = val & 0xf; 3527 if (!(val & 0x40)) /* negative number */ 3528 delta_2ghz = -delta_2ghz; 3529 } 3530 val >>= 8; 3531 if ((val & 0xff) != 0xff && (val & 0x80)) { 3532 delta_5ghz = val & 0xf; 3533 if (!(val & 0x40)) /* negative number */ 3534 delta_5ghz = -delta_5ghz; 3535 } 3536 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3537 delta_2ghz, delta_5ghz)); 3538 3539 for (ridx = 0; ridx < 5; ridx++) { 3540 uint32_t reg; 3541 3542 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3543 reg = val; 3544 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3545 reg |= (uint32_t)val << 16; 3546 3547 sc->txpow20mhz[ridx] = reg; 3548 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3549 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3550 3551 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3552 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3553 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3554 } 3555 3556 /* read factory-calibrated samples for temperature compensation */ 3557 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3558 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3559 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3560 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3561 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3562 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3563 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3564 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3565 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3566 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3567 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3568 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3569 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3570 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3571 sc->step_2ghz = val >> 8; 3572 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3573 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3574 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3575 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3576 sc->tssi_2ghz[8], sc->step_2ghz)); 3577 /* check that ref value is correct, otherwise disable calibration */ 3578 if (sc->tssi_2ghz[4] == 0xff) 3579 sc->calib_2ghz = 0; 3580 3581 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3582 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3583 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3584 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3585 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3586 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3587 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3588 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3589 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3590 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3591 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3592 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3593 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3594 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3595 sc->step_5ghz = val >> 8; 3596 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3597 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3598 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3599 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3600 sc->tssi_5ghz[8], sc->step_5ghz)); 3601 /* check that ref value is correct, otherwise disable calibration */ 3602 if (sc->tssi_5ghz[4] == 0xff) 3603 sc->calib_5ghz = 0; 3604 3605 /* read RSSI offsets and LNA gains from EEPROM */ 3606 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3607 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3608 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3609 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3610 if (sc->mac_ver >= 0x3071) { 3611 /* 3612 * On RT3090 chips (limited to 2 Rx chains), this ROM 3613 * field contains the Tx mixer gain for the 2GHz band. 3614 */ 3615 if ((val & 0xff) != 0xff) 3616 sc->txmixgain_2ghz = val & 0x7; 3617 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3618 } else 3619 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3620 sc->lna[2] = val >> 8; /* channel group 2 */ 3621 3622 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3623 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3624 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3625 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3626 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3627 sc->lna[3] = val >> 8; /* channel group 3 */ 3628 3629 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3630 if (sc->mac_ver >= 0x3071) 3631 sc->lna[0] = RT3090_DEF_LNA; 3632 else /* channel group 0 */ 3633 sc->lna[0] = val & 0xff; 3634 sc->lna[1] = val >> 8; /* channel group 1 */ 3635 3636 /* fix broken 5GHz LNA entries */ 3637 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3638 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3639 sc->lna[2] = sc->lna[1]; 3640 } 3641 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3642 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3643 sc->lna[3] = sc->lna[1]; 3644 } 3645 3646 /* fix broken RSSI offset entries */ 3647 for (ant = 0; ant < 3; ant++) { 3648 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3649 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3650 ant + 1, sc->rssi_2ghz[ant])); 3651 sc->rssi_2ghz[ant] = 0; 3652 } 3653 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3654 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3655 ant + 1, sc->rssi_5ghz[ant])); 3656 sc->rssi_5ghz[ant] = 0; 3657 } 3658 } 3659 3660 return 0; 3661} 3662 3663static int 3664rt2860_bbp_init(struct rt2860_softc *sc) 3665{ 3666 int i, ntries; 3667 3668 /* wait for BBP to wake up */ 3669 for (ntries = 0; ntries < 20; ntries++) { 3670 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3671 if (bbp0 != 0 && bbp0 != 0xff) 3672 break; 3673 } 3674 if (ntries == 20) { 3675 device_printf(sc->sc_dev, 3676 "timeout waiting for BBP to wake up\n"); 3677 return (ETIMEDOUT); 3678 } 3679 3680 /* initialize BBP registers to default values */ 3681 if (sc->mac_ver >= 0x5390) 3682 rt5390_bbp_init(sc); 3683 else { 3684 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3685 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3686 rt2860_def_bbp[i].val); 3687 } 3688 } 3689 3690 /* fix BBP84 for RT2860E */ 3691 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3692 rt2860_mcu_bbp_write(sc, 84, 0x19); 3693 3694 if (sc->mac_ver >= 0x3071) { 3695 rt2860_mcu_bbp_write(sc, 79, 0x13); 3696 rt2860_mcu_bbp_write(sc, 80, 0x05); 3697 rt2860_mcu_bbp_write(sc, 81, 0x33); 3698 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3699 rt2860_mcu_bbp_write(sc, 69, 0x16); 3700 rt2860_mcu_bbp_write(sc, 73, 0x12); 3701 } 3702 3703 return 0; 3704} 3705 3706static void 3707rt5390_bbp_init(struct rt2860_softc *sc) 3708{ 3709 uint8_t bbp; 3710 int i; 3711 3712 /* Apply maximum likelihood detection for 2 stream case. */ 3713 if (sc->nrxchains > 1) { 3714 bbp = rt2860_mcu_bbp_read(sc, 105); 3715 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3716 } 3717 3718 /* Avoid data lost and CRC error. */ 3719 bbp = rt2860_mcu_bbp_read(sc, 4); 3720 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3721 3722 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3723 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3724 rt5390_def_bbp[i].val); 3725 } 3726 3727 if (sc->mac_ver == 0x5392) { 3728 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3729 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3730 rt2860_mcu_bbp_write(sc, 98, 0x12); 3731 rt2860_mcu_bbp_write(sc, 106, 0x05); 3732 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3733 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3734 } 3735 3736 bbp = rt2860_mcu_bbp_read(sc, 152); 3737 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3738 3739 /* Disable hardware antenna diversity. */ 3740 if (sc->mac_ver == 0x5390) 3741 rt2860_mcu_bbp_write(sc, 154, 0); 3742} 3743 3744static int 3745rt2860_txrx_enable(struct rt2860_softc *sc) 3746{ 3747 struct ieee80211com *ic = &sc->sc_ic; 3748 uint32_t tmp; 3749 int ntries; 3750 3751 /* enable Tx/Rx DMA engine */ 3752 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3753 RAL_BARRIER_READ_WRITE(sc); 3754 for (ntries = 0; ntries < 200; ntries++) { 3755 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3756 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3757 break; 3758 DELAY(1000); 3759 } 3760 if (ntries == 200) { 3761 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3762 return ETIMEDOUT; 3763 } 3764 3765 DELAY(50); 3766 3767 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3768 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3769 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3770 3771 /* set Rx filter */ 3772 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3773 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3774 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3775 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3776 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3777 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3778 if (ic->ic_opmode == IEEE80211_M_STA) 3779 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3780 } 3781 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3782 3783 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3784 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3785 3786 return 0; 3787} 3788 3789static void 3790rt2860_init(void *arg) 3791{ 3792 struct rt2860_softc *sc = arg; 3793 struct ieee80211com *ic = &sc->sc_ic; 3794 3795 RAL_LOCK(sc); 3796 rt2860_init_locked(sc); 3797 RAL_UNLOCK(sc); 3798 3799 if (sc->sc_flags & RT2860_RUNNING) 3800 ieee80211_start_all(ic); 3801} 3802 3803static void 3804rt2860_init_locked(struct rt2860_softc *sc) 3805{ 3806 struct ieee80211com *ic = &sc->sc_ic; 3807 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3808 uint32_t tmp; 3809 uint8_t bbp1, bbp3; 3810 int i, qid, ridx, ntries, error; 3811 3812 RAL_LOCK_ASSERT(sc); 3813 3814 if (sc->rfswitch) { 3815 /* hardware has a radio switch on GPIO pin 2 */ 3816 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3817 device_printf(sc->sc_dev, 3818 "radio is disabled by hardware switch\n"); 3819#ifdef notyet 3820 rt2860_stop_locked(sc); 3821 return; 3822#endif 3823 } 3824 } 3825 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3826 3827 /* disable DMA */ 3828 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3829 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3830 RT2860_TX_DMA_EN); 3831 tmp |= RT2860_TX_WB_DDONE; 3832 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3833 3834 /* reset DMA indexes */ 3835 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3836 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3837 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3838 3839 /* PBF hardware reset */ 3840 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3841 RAL_BARRIER_WRITE(sc); 3842 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3843 3844 if ((error = rt2860_load_microcode(sc)) != 0) { 3845 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3846 rt2860_stop_locked(sc); 3847 return; 3848 } 3849 3850 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3851 3852 /* init Tx power for all Tx rates (from EEPROM) */ 3853 for (ridx = 0; ridx < 5; ridx++) { 3854 if (sc->txpow20mhz[ridx] == 0xffffffff) 3855 continue; 3856 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3857 } 3858 3859 for (ntries = 0; ntries < 100; ntries++) { 3860 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3861 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3862 break; 3863 DELAY(1000); 3864 } 3865 if (ntries == 100) { 3866 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3867 rt2860_stop_locked(sc); 3868 return; 3869 } 3870 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3871 RT2860_TX_DMA_EN); 3872 tmp |= RT2860_TX_WB_DDONE; 3873 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3874 3875 /* reset Rx ring and all 6 Tx rings */ 3876 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3877 3878 /* PBF hardware reset */ 3879 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3880 RAL_BARRIER_WRITE(sc); 3881 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3882 3883 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3884 3885 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3886 RAL_BARRIER_WRITE(sc); 3887 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3888 3889 for (i = 0; i < nitems(rt2860_def_mac); i++) 3890 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3891 if (sc->mac_ver >= 0x5390) 3892 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3893 else if (sc->mac_ver >= 0x3071) { 3894 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3895 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3896 4 << RT2860_DLY_PAPE_EN_SHIFT); 3897 } 3898 3899 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3900 sc->sc_flags |= RT2860_PCIE; 3901 /* PCIe has different clock cycle count than PCI */ 3902 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3903 tmp = (tmp & ~0xff) | 0x7d; 3904 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3905 } 3906 3907 /* wait while MAC is busy */ 3908 for (ntries = 0; ntries < 100; ntries++) { 3909 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3910 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3911 break; 3912 DELAY(1000); 3913 } 3914 if (ntries == 100) { 3915 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3916 rt2860_stop_locked(sc); 3917 return; 3918 } 3919 3920 /* clear Host to MCU mailbox */ 3921 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3922 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3923 3924 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3925 DELAY(1000); 3926 3927 if ((error = rt2860_bbp_init(sc)) != 0) { 3928 rt2860_stop_locked(sc); 3929 return; 3930 } 3931 3932 /* clear RX WCID search table */ 3933 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3934 /* clear pairwise key table */ 3935 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3936 /* clear IV/EIV table */ 3937 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3938 /* clear WCID attribute table */ 3939 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3940 /* clear shared key table */ 3941 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3942 /* clear shared key mode */ 3943 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3944 3945 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3946 for (qid = 0; qid < 6; qid++) { 3947 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3948 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3949 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3950 } 3951 3952 /* init Rx ring */ 3953 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3954 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3955 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3956 3957 /* setup maximum buffer sizes */ 3958 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3959 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3960 3961 for (ntries = 0; ntries < 100; ntries++) { 3962 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3963 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3964 break; 3965 DELAY(1000); 3966 } 3967 if (ntries == 100) { 3968 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3969 rt2860_stop_locked(sc); 3970 return; 3971 } 3972 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3973 RT2860_TX_DMA_EN); 3974 tmp |= RT2860_TX_WB_DDONE; 3975 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3976 3977 /* disable interrupts mitigation */ 3978 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3979 3980 /* write vendor-specific BBP values (from EEPROM) */ 3981 for (i = 0; i < 8; i++) { 3982 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3983 continue; 3984 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3985 } 3986 3987 /* select Main antenna for 1T1R devices */ 3988 if (sc->rf_rev == RT3070_RF_2020 || 3989 sc->rf_rev == RT3070_RF_3020 || 3990 sc->rf_rev == RT3070_RF_3320 || 3991 sc->mac_ver == 0x5390) 3992 rt3090_set_rx_antenna(sc, 0); 3993 3994 /* send LEDs operating mode to microcontroller */ 3995 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3996 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3997 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3998 3999 if (sc->mac_ver >= 0x5390) 4000 rt5390_rf_init(sc); 4001 else if (sc->mac_ver >= 0x3071) { 4002 if ((error = rt3090_rf_init(sc)) != 0) { 4003 rt2860_stop_locked(sc); 4004 return; 4005 } 4006 } 4007 4008 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 4009 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 4010 4011 if (sc->mac_ver >= 0x5390) 4012 rt5390_rf_wakeup(sc); 4013 else if (sc->mac_ver >= 0x3071) 4014 rt3090_rf_wakeup(sc); 4015 4016 /* disable non-existing Rx chains */ 4017 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4018 bbp3 &= ~(1 << 3 | 1 << 4); 4019 if (sc->nrxchains == 2) 4020 bbp3 |= 1 << 3; 4021 else if (sc->nrxchains == 3) 4022 bbp3 |= 1 << 4; 4023 rt2860_mcu_bbp_write(sc, 3, bbp3); 4024 4025 /* disable non-existing Tx chains */ 4026 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4027 if (sc->ntxchains == 1) 4028 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4029 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4030 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4031 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4032 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4033 rt2860_mcu_bbp_write(sc, 1, bbp1); 4034 4035 if (sc->mac_ver >= 0x3071) 4036 rt3090_rf_setup(sc); 4037 4038 /* select default channel */ 4039 rt2860_switch_chan(sc, ic->ic_curchan); 4040 4041 /* reset RF from MCU */ 4042 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4043 4044 /* set RTS threshold */ 4045 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4046 tmp &= ~0xffff00; 4047 tmp |= IEEE80211_RTS_DEFAULT << 8; 4048 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4049 4050 /* setup initial protection mode */ 4051 rt2860_updateprot(sc); 4052 4053 /* turn radio LED on */ 4054 rt2860_set_leds(sc, RT2860_LED_RADIO); 4055 4056 /* enable Tx/Rx DMA engine */ 4057 if ((error = rt2860_txrx_enable(sc)) != 0) { 4058 rt2860_stop_locked(sc); 4059 return; 4060 } 4061 4062 /* clear pending interrupts */ 4063 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4064 /* enable interrupts */ 4065 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4066 4067 if (sc->sc_flags & RT2860_ADVANCED_PS) 4068 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4069 4070 sc->sc_flags |= RT2860_RUNNING; 4071 4072 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4073} 4074 4075static void 4076rt2860_stop(void *arg) 4077{ 4078 struct rt2860_softc *sc = arg; 4079 4080 RAL_LOCK(sc); 4081 rt2860_stop_locked(sc); 4082 RAL_UNLOCK(sc); 4083} 4084 4085static void 4086rt2860_stop_locked(struct rt2860_softc *sc) 4087{ 4088 uint32_t tmp; 4089 int qid; 4090 4091 if (sc->sc_flags & RT2860_RUNNING) 4092 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4093 4094 callout_stop(&sc->watchdog_ch); 4095 sc->sc_tx_timer = 0; 4096 sc->sc_flags &= ~RT2860_RUNNING; 4097 4098 /* disable interrupts */ 4099 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4100 4101 /* disable GP timer */ 4102 rt2860_set_gp_timer(sc, 0); 4103 4104 /* disable Rx */ 4105 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4106 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4107 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4108 4109 /* reset adapter */ 4110 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4111 RAL_BARRIER_WRITE(sc); 4112 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4113 4114 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4115 sc->qfullmsk = 0; 4116 for (qid = 0; qid < 6; qid++) 4117 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4118 rt2860_reset_rx_ring(sc, &sc->rxq); 4119} 4120 4121int 4122rt2860_load_microcode(struct rt2860_softc *sc) 4123{ 4124 const struct firmware *fp; 4125 int ntries, error; 4126 4127 RAL_LOCK_ASSERT(sc); 4128 4129 RAL_UNLOCK(sc); 4130 fp = firmware_get("rt2860fw"); 4131 RAL_LOCK(sc); 4132 if (fp == NULL) { 4133 device_printf(sc->sc_dev, 4134 "unable to receive rt2860fw firmware image\n"); 4135 return EINVAL; 4136 } 4137 4138 /* set "host program ram write selection" bit */ 4139 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4140 /* write microcode image */ 4141 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4142 /* kick microcontroller unit */ 4143 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4144 RAL_BARRIER_WRITE(sc); 4145 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4146 4147 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4148 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4149 4150 /* wait until microcontroller is ready */ 4151 RAL_BARRIER_READ_WRITE(sc); 4152 for (ntries = 0; ntries < 1000; ntries++) { 4153 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4154 break; 4155 DELAY(1000); 4156 } 4157 if (ntries == 1000) { 4158 device_printf(sc->sc_dev, 4159 "timeout waiting for MCU to initialize\n"); 4160 error = ETIMEDOUT; 4161 } else 4162 error = 0; 4163 4164 firmware_put(fp, FIRMWARE_UNLOAD); 4165 return error; 4166} 4167 4168/* 4169 * This function is called periodically to adjust Tx power based on 4170 * temperature variation. 4171 */ 4172#ifdef NOT_YET 4173static void 4174rt2860_calib(struct rt2860_softc *sc) 4175{ 4176 struct ieee80211com *ic = &sc->sc_ic; 4177 const uint8_t *tssi; 4178 uint8_t step, bbp49; 4179 int8_t ridx, d; 4180 4181 /* read current temperature */ 4182 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4183 4184 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4185 tssi = &sc->tssi_2ghz[4]; 4186 step = sc->step_2ghz; 4187 } else { 4188 tssi = &sc->tssi_5ghz[4]; 4189 step = sc->step_5ghz; 4190 } 4191 4192 if (bbp49 < tssi[0]) { /* lower than reference */ 4193 /* use higher Tx power than default */ 4194 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4195 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4196 /* use lower Tx power than default */ 4197 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4198 } else { 4199 /* use default Tx power */ 4200 d = 0; 4201 } 4202 d *= step; 4203 4204 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4205 4206 /* write adjusted Tx power values for each Tx rate */ 4207 for (ridx = 0; ridx < 5; ridx++) { 4208 if (sc->txpow20mhz[ridx] == 0xffffffff) 4209 continue; 4210 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4211 b4inc(sc->txpow20mhz[ridx], d)); 4212 } 4213} 4214#endif 4215 4216static void 4217rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4218{ 4219 uint32_t tmp; 4220 4221 if (aux) { 4222 if (sc->mac_ver == 0x5390) { 4223 rt2860_mcu_bbp_write(sc, 152, 4224 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4225 } else { 4226 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4227 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4228 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4229 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4230 } 4231 } else { 4232 if (sc->mac_ver == 0x5390) { 4233 rt2860_mcu_bbp_write(sc, 152, 4234 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4235 } else { 4236 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4237 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4238 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4239 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4240 } 4241 } 4242} 4243 4244static void 4245rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4246{ 4247 struct ieee80211com *ic = &sc->sc_ic; 4248 u_int chan, group; 4249 4250 chan = ieee80211_chan2ieee(ic, c); 4251 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4252 return; 4253 4254 if (sc->mac_ver >= 0x5390) 4255 rt5390_set_chan(sc, chan); 4256 else if (sc->mac_ver >= 0x3071) 4257 rt3090_set_chan(sc, chan); 4258 else 4259 rt2860_set_chan(sc, chan); 4260 4261 /* determine channel group */ 4262 if (chan <= 14) 4263 group = 0; 4264 else if (chan <= 64) 4265 group = 1; 4266 else if (chan <= 128) 4267 group = 2; 4268 else 4269 group = 3; 4270 4271 /* XXX necessary only when group has changed! */ 4272 if (sc->mac_ver < 0x5390) 4273 rt2860_select_chan_group(sc, group); 4274 4275 DELAY(1000); 4276} 4277 4278static int 4279rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4280{ 4281 struct ieee80211com *ic = vap->iv_ic; 4282 struct rt2860_txwi txwi; 4283 struct mbuf *m; 4284 int ridx; 4285 4286 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4287 return ENOBUFS; 4288 4289 memset(&txwi, 0, sizeof txwi); 4290 txwi.wcid = 0xff; 4291 txwi.len = htole16(m->m_pkthdr.len); 4292 /* send beacons at the lowest available rate */ 4293 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4294 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4295 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4296 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4297 txwi.phy |= htole16(RT2860_PHY_OFDM); 4298 txwi.txop = RT2860_TX_TXOP_HT; 4299 txwi.flags = RT2860_TX_TS; 4300 txwi.xflags = RT2860_TX_NSEQ; 4301 4302 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4303 (uint8_t *)&txwi, sizeof txwi); 4304 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4305 mtod(m, uint8_t *), m->m_pkthdr.len); 4306 4307 m_freem(m); 4308 4309 return 0; 4310} 4311 4312static void 4313rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4314{ 4315 struct ieee80211com *ic = &sc->sc_ic; 4316 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4317 uint32_t tmp; 4318 4319 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4320 4321 tmp &= ~0x1fffff; 4322 tmp |= vap->iv_bss->ni_intval * 16; 4323 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4324 if (vap->iv_opmode == IEEE80211_M_STA) { 4325 /* 4326 * Local TSF is always updated with remote TSF on beacon 4327 * reception. 4328 */ 4329 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4330 } 4331 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4332 vap->iv_opmode == IEEE80211_M_MBSS) { 4333 tmp |= RT2860_BCN_TX_EN; 4334 /* 4335 * Local TSF is updated with remote TSF on beacon reception 4336 * only if the remote TSF is greater than local TSF. 4337 */ 4338 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4339 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4340 tmp |= RT2860_BCN_TX_EN; 4341 /* SYNC with nobody */ 4342 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4343 } 4344 4345 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4346} 4347