1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2010 Atheros Communications Inc. 5 * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: releng/12.0/sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c 326255 2017-11-27 14:52:40Z pfg $ 29 */ 30#include "opt_ah.h" 31 32#include "ah.h" 33#include "ah_desc.h" 34#include "ah_internal.h" 35#include "ah_eeprom_v4k.h" 36 37#include "ar9002/ar9280.h" 38#include "ar9002/ar9285.h" 39#include "ar5416/ar5416reg.h" 40#include "ar5416/ar5416phy.h" 41#include "ar9002/ar9285phy.h" 42#include "ar9002/ar9285_phy.h" 43 44#include "ar9002/ar9285_diversity.h" 45 46/* 47 * Set the antenna switch to control RX antenna diversity. 48 * 49 * If a fixed configuration is used, the LNA and div bias 50 * settings are fixed and the antenna diversity scanning routine 51 * is disabled. 52 * 53 * If a variable configuration is used, a default is programmed 54 * in and sampling commences per RXed packet. 55 * 56 * Since this is called from ar9285SetBoardValues() to setup 57 * diversity, it means that after a reset or scan, any current 58 * software diversity combining settings will be lost and won't 59 * re-appear until after the first successful sample run. 60 * Please keep this in mind if you're seeing weird performance 61 * that happens to relate to scan/diversity timing. 62 */ 63HAL_BOOL 64ar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 65{ 66 int regVal; 67 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 68 const MODAL_EEP4K_HEADER *pModal = &ee->ee_base.modalHeader; 69 uint8_t ant_div_control1, ant_div_control2; 70 71 if (pModal->version < 3) { 72 HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: not supported\n", 73 __func__); 74 return AH_FALSE; /* Can't do diversity */ 75 } 76 77 /* Store settings */ 78 AH5212(ah)->ah_antControl = settings; 79 AH5212(ah)->ah_diversity = (settings == HAL_ANT_VARIABLE); 80 81 /* XXX don't fiddle if the PHY is in sleep mode or ! chan */ 82 83 /* Begin setting the relevant registers */ 84 85 ant_div_control1 = pModal->antdiv_ctl1; 86 ant_div_control2 = pModal->antdiv_ctl2; 87 88 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 89 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 90 91 /* enable antenna diversity only if diversityControl == HAL_ANT_VARIABLE */ 92 if (settings == HAL_ANT_VARIABLE) 93 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); 94 95 if (settings == HAL_ANT_VARIABLE) { 96 HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_VARIABLE\n", 97 __func__); 98 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); 99 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 100 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); 101 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 102 } else { 103 if (settings == HAL_ANT_FIXED_A) { 104 /* Diversity disabled, RX = LNA1 */ 105 HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_FIXED_A\n", 106 __func__); 107 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); 108 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 109 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_ALT_GAINTB); 110 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 111 } 112 else if (settings == HAL_ANT_FIXED_B) { 113 /* Diversity disabled, RX = LNA2 */ 114 HALDEBUG(ah, HAL_DEBUG_DIVERSITY, "%s: HAL_ANT_FIXED_B\n", 115 __func__); 116 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_ALT_LNACONF); 117 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 118 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_1, AR_PHY_9285_ANT_DIV_ALT_GAINTB); 119 regVal |= SM(AR_PHY_9285_ANT_DIV_GAINTB_0, AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 120 } 121 } 122 123 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 124 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 125 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 126 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 127 if (settings == HAL_ANT_VARIABLE) 128 regVal |= SM((ant_div_control1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 129 130 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 131 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 132 133 /* 134 * If Diversity combining is available and the diversity setting 135 * is to allow variable diversity, enable it by default. 136 * 137 * This will be eventually overridden by the software antenna 138 * diversity logic. 139 * 140 * Note that yes, this following section overrides the above 141 * settings for the LNA configuration and fast-bias. 142 */ 143 if (ar9285_check_div_comb(ah) && AH5212(ah)->ah_diversity == AH_TRUE) { 144 // If support DivComb, set MAIN to LNA1 and ALT to LNA2 at the first beginning 145 HALDEBUG(ah, HAL_DEBUG_DIVERSITY, 146 "%s: Enable initial settings for combined diversity\n", 147 __func__); 148 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 149 regVal &= (~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | AR_PHY_9285_ANT_DIV_ALT_LNACONF)); 150 regVal |= (HAL_ANT_DIV_COMB_LNA1 << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S); 151 regVal |= (HAL_ANT_DIV_COMB_LNA2 << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S); 152 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS)); 153 regVal |= (0 << AR_PHY_9285_FAST_DIV_BIAS_S); 154 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 155 } 156 157 return AH_TRUE; 158} 159