1/*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD: releng/12.0/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 326695 2017-12-08 15:57:29Z pfg $ 20 */ 21#include "opt_ah.h" 22 23#include "ah.h" 24#include "ah_internal.h" 25#include "ah_devid.h" 26 27#include "ar5212/ar5212.h" 28#include "ar5212/ar5212reg.h" 29#include "ar5212/ar5212phy.h" 30 31#define AH_5212_COMMON 32#include "ar5212/ar5212.ini" 33 34static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 35 HAL_BOOL power_off); 36static void ar5212DisablePCIE(struct ath_hal *ah); 37 38static const struct ath_hal_private ar5212hal = {{ 39 .ah_magic = AR5212_MAGIC, 40 41 .ah_getRateTable = ar5212GetRateTable, 42 .ah_detach = ar5212Detach, 43 44 /* Reset Functions */ 45 .ah_reset = ar5212Reset, 46 .ah_phyDisable = ar5212PhyDisable, 47 .ah_disable = ar5212Disable, 48 .ah_configPCIE = ar5212ConfigPCIE, 49 .ah_disablePCIE = ar5212DisablePCIE, 50 .ah_setPCUConfig = ar5212SetPCUConfig, 51 .ah_perCalibration = ar5212PerCalibration, 52 .ah_perCalibrationN = ar5212PerCalibrationN, 53 .ah_resetCalValid = ar5212ResetCalValid, 54 .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 55 .ah_getChanNoise = ath_hal_getChanNoise, 56 57 /* Transmit functions */ 58 .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 59 .ah_setupTxQueue = ar5212SetupTxQueue, 60 .ah_setTxQueueProps = ar5212SetTxQueueProps, 61 .ah_getTxQueueProps = ar5212GetTxQueueProps, 62 .ah_releaseTxQueue = ar5212ReleaseTxQueue, 63 .ah_resetTxQueue = ar5212ResetTxQueue, 64 .ah_getTxDP = ar5212GetTxDP, 65 .ah_setTxDP = ar5212SetTxDP, 66 .ah_numTxPending = ar5212NumTxPending, 67 .ah_startTxDma = ar5212StartTxDma, 68 .ah_stopTxDma = ar5212StopTxDma, 69 .ah_setupTxDesc = ar5212SetupTxDesc, 70 .ah_setupXTxDesc = ar5212SetupXTxDesc, 71 .ah_fillTxDesc = ar5212FillTxDesc, 72 .ah_procTxDesc = ar5212ProcTxDesc, 73 .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 74 .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 75 .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 76 .ah_setTxDescLink = ar5212SetTxDescLink, 77 .ah_getTxDescLink = ar5212GetTxDescLink, 78 .ah_getTxDescLinkPtr = ar5212GetTxDescLinkPtr, 79 80 /* RX Functions */ 81 .ah_getRxDP = ar5212GetRxDP, 82 .ah_setRxDP = ar5212SetRxDP, 83 .ah_enableReceive = ar5212EnableReceive, 84 .ah_stopDmaReceive = ar5212StopDmaReceive, 85 .ah_startPcuReceive = ar5212StartPcuReceive, 86 .ah_stopPcuReceive = ar5212StopPcuReceive, 87 .ah_setMulticastFilter = ar5212SetMulticastFilter, 88 .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 89 .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 90 .ah_getRxFilter = ar5212GetRxFilter, 91 .ah_setRxFilter = ar5212SetRxFilter, 92 .ah_setupRxDesc = ar5212SetupRxDesc, 93 .ah_procRxDesc = ar5212ProcRxDesc, 94 .ah_rxMonitor = ar5212RxMonitor, 95 .ah_aniPoll = ar5212AniPoll, 96 .ah_procMibEvent = ar5212ProcessMibIntr, 97 98 /* Misc Functions */ 99 .ah_getCapability = ar5212GetCapability, 100 .ah_setCapability = ar5212SetCapability, 101 .ah_getDiagState = ar5212GetDiagState, 102 .ah_getMacAddress = ar5212GetMacAddress, 103 .ah_setMacAddress = ar5212SetMacAddress, 104 .ah_getBssIdMask = ar5212GetBssIdMask, 105 .ah_setBssIdMask = ar5212SetBssIdMask, 106 .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 107 .ah_setLedState = ar5212SetLedState, 108 .ah_writeAssocid = ar5212WriteAssocid, 109 .ah_gpioCfgInput = ar5212GpioCfgInput, 110 .ah_gpioCfgOutput = ar5212GpioCfgOutput, 111 .ah_gpioGet = ar5212GpioGet, 112 .ah_gpioSet = ar5212GpioSet, 113 .ah_gpioSetIntr = ar5212GpioSetIntr, 114 .ah_getTsf32 = ar5212GetTsf32, 115 .ah_getTsf64 = ar5212GetTsf64, 116 .ah_setTsf64 = ar5212SetTsf64, 117 .ah_resetTsf = ar5212ResetTsf, 118 .ah_detectCardPresent = ar5212DetectCardPresent, 119 .ah_updateMibCounters = ar5212UpdateMibCounters, 120 .ah_getRfGain = ar5212GetRfgain, 121 .ah_getDefAntenna = ar5212GetDefAntenna, 122 .ah_setDefAntenna = ar5212SetDefAntenna, 123 .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 124 .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 125 .ah_setSifsTime = ar5212SetSifsTime, 126 .ah_getSifsTime = ar5212GetSifsTime, 127 .ah_setSlotTime = ar5212SetSlotTime, 128 .ah_getSlotTime = ar5212GetSlotTime, 129 .ah_setAckTimeout = ar5212SetAckTimeout, 130 .ah_getAckTimeout = ar5212GetAckTimeout, 131 .ah_setAckCTSRate = ar5212SetAckCTSRate, 132 .ah_getAckCTSRate = ar5212GetAckCTSRate, 133 .ah_setCTSTimeout = ar5212SetCTSTimeout, 134 .ah_getCTSTimeout = ar5212GetCTSTimeout, 135 .ah_setDecompMask = ar5212SetDecompMask, 136 .ah_setCoverageClass = ar5212SetCoverageClass, 137 .ah_setQuiet = ar5212SetQuiet, 138 .ah_getMibCycleCounts = ar5212GetMibCycleCounts, 139 .ah_setChainMasks = ar5212SetChainMasks, 140 141 /* DFS Functions */ 142 .ah_enableDfs = ar5212EnableDfs, 143 .ah_getDfsThresh = ar5212GetDfsThresh, 144 .ah_getDfsDefaultThresh = ar5212GetDfsDefaultThresh, 145 .ah_procRadarEvent = ar5212ProcessRadarEvent, 146 .ah_isFastClockEnabled = ar5212IsFastClockEnabled, 147 .ah_get11nExtBusy = ar5212Get11nExtBusy, 148 149 /* Key Cache Functions */ 150 .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 151 .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 152 .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 153 .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 154 .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 155 156 /* Power Management Functions */ 157 .ah_setPowerMode = ar5212SetPowerMode, 158 .ah_getPowerMode = ar5212GetPowerMode, 159 160 /* Beacon Functions */ 161 .ah_setBeaconTimers = ar5212SetBeaconTimers, 162 .ah_beaconInit = ar5212BeaconInit, 163 .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 164 .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 165 .ah_getNextTBTT = ar5212GetNextTBTT, 166 167 /* Interrupt Functions */ 168 .ah_isInterruptPending = ar5212IsInterruptPending, 169 .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 170 .ah_getInterrupts = ar5212GetInterrupts, 171 .ah_setInterrupts = ar5212SetInterrupts }, 172 173 .ah_getChannelEdges = ar5212GetChannelEdges, 174 .ah_getWirelessModes = ar5212GetWirelessModes, 175 .ah_eepromRead = ar5212EepromRead, 176#ifdef AH_SUPPORT_WRITE_EEPROM 177 .ah_eepromWrite = ar5212EepromWrite, 178#endif 179 .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 180}; 181 182uint32_t 183ar5212GetRadioRev(struct ath_hal *ah) 184{ 185 uint32_t val; 186 int i; 187 188 /* Read Radio Chip Rev Extract */ 189 OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 190 for (i = 0; i < 8; i++) 191 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 192 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 193 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 194 return ath_hal_reverseBits(val, 8); 195} 196 197static void 198ar5212AniSetup(struct ath_hal *ah) 199{ 200 static const struct ar5212AniParams aniparams = { 201 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 202 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 203 .coarseHigh = { -14, -14, -14, -14, -12 }, 204 .coarseLow = { -64, -64, -64, -64, -70 }, 205 .firpwr = { -78, -78, -78, -78, -80 }, 206 .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 207 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 208 .maxFirstepLevel = 2, /* levels 0..2 */ 209 .firstep = { 0, 4, 8 }, 210 .ofdmTrigHigh = 500, 211 .ofdmTrigLow = 200, 212 .cckTrigHigh = 200, 213 .cckTrigLow = 100, 214 .rssiThrHigh = 40, 215 .rssiThrLow = 7, 216 .period = 100, 217 }; 218 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 219 struct ar5212AniParams tmp; 220 OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 221 tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 222 ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 223 } else 224 ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 225 226 /* Set overridable ANI methods */ 227 AH5212(ah)->ah_aniControl = ar5212AniControl; 228} 229 230/* 231 * Attach for an AR5212 part. 232 */ 233void 234ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 235 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 236{ 237#define N(a) (sizeof(a)/sizeof(a[0])) 238 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 239 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 240 struct ath_hal *ah; 241 242 ah = &ahp->ah_priv.h; 243 /* set initial values */ 244 OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 245 ah->ah_sc = sc; 246 ah->ah_st = st; 247 ah->ah_sh = sh; 248 249 ah->ah_devid = devid; /* NB: for alq */ 250 AH_PRIVATE(ah)->ah_devid = devid; 251 AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 252 253 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 254 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 255 256 ahp->ah_antControl = HAL_ANT_VARIABLE; 257 ahp->ah_diversity = AH_TRUE; 258 ahp->ah_bIQCalibration = AH_FALSE; 259 /* 260 * Enable MIC handling. 261 */ 262 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 263 ahp->ah_rssiThr = INIT_RSSI_THR; 264 ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 265 ahp->ah_phyPowerOn = AH_FALSE; 266 ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 267 | SM(MAX_RATE_POWER, AR_TPC_CTS) 268 | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 269 ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 270 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 271 ahp->ah_slottime = (u_int) -1; 272 ahp->ah_acktimeout = (u_int) -1; 273 ahp->ah_ctstimeout = (u_int) -1; 274 ahp->ah_sifstime = (u_int) -1; 275 ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD; 276 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD; 277 278 OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 279#undef N 280} 281 282/* 283 * Validate MAC version and revision. 284 */ 285static HAL_BOOL 286ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 287{ 288#define N(a) (sizeof(a)/sizeof(a[0])) 289 static const struct { 290 uint8_t version; 291 uint8_t revMin, revMax; 292 } macs[] = { 293 { AR_SREV_VERSION_VENICE, 294 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 295 { AR_SREV_VERSION_GRIFFIN, 296 AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 297 { AR_SREV_5413, 298 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 299 { AR_SREV_5424, 300 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 301 { AR_SREV_2425, 302 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 303 { AR_SREV_2417, 304 AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 305 }; 306 int i; 307 308 for (i = 0; i < N(macs); i++) 309 if (macs[i].version == macVersion && 310 macs[i].revMin <= macRev && macRev <= macs[i].revMax) 311 return AH_TRUE; 312 return AH_FALSE; 313#undef N 314} 315 316/* 317 * Attach for an AR5212 part. 318 */ 319static struct ath_hal * 320ar5212Attach(uint16_t devid, HAL_SOFTC sc, 321 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 322 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status) 323{ 324#define AH_EEPROM_PROTECT(ah) \ 325 (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 326 struct ath_hal_5212 *ahp; 327 struct ath_hal *ah; 328 struct ath_hal_rf *rf; 329 uint32_t val; 330 uint16_t eeval; 331 HAL_STATUS ecode; 332 333 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 334 __func__, sc, (void*) st, (void*) sh); 335 336 /* NB: memory is returned zero'd */ 337 ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 338 if (ahp == AH_NULL) { 339 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 340 "%s: cannot allocate memory for state block\n", __func__); 341 *status = HAL_ENOMEM; 342 return AH_NULL; 343 } 344 ar5212InitState(ahp, devid, sc, st, sh, status); 345 ah = &ahp->ah_priv.h; 346 347 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 348 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 349 __func__); 350 ecode = HAL_EIO; 351 goto bad; 352 } 353 /* Read Revisions from Chips before taking out of reset */ 354 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 355 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 356 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 357 AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 358 359 if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 360 HALDEBUG(ah, HAL_DEBUG_ANY, 361 "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 362 __func__, AH_PRIVATE(ah)->ah_macVersion, 363 AH_PRIVATE(ah)->ah_macRev); 364 ecode = HAL_ENOTSUPP; 365 goto bad; 366 } 367 368 /* setup common ini data; rf backends handle remainder */ 369 HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 370 HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 371 372 if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 373 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 374 ecode = HAL_EIO; 375 goto bad; 376 } 377 378 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 379 380 if (AH_PRIVATE(ah)->ah_ispcie) { 381 /* XXX: build flag to disable this? */ 382 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 383 } 384 385 if (!ar5212ChipTest(ah)) { 386 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 387 __func__); 388 ecode = HAL_ESELFTEST; 389 goto bad; 390 } 391 392 /* Enable PCI core retry fix in software for Hainan and up */ 393 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 394 OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 395 396 /* 397 * Set correct Baseband to analog shift 398 * setting to access analog chips. 399 */ 400 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 401 402 /* Read Radio Chip Rev Extract */ 403 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 404 405 rf = ath_hal_rfprobe(ah, &ecode); 406 if (rf == AH_NULL) 407 goto bad; 408 409 /* NB: silently accept anything in release code per Atheros */ 410 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 411 case AR_RAD5111_SREV_MAJOR: 412 case AR_RAD5112_SREV_MAJOR: 413 case AR_RAD2112_SREV_MAJOR: 414 case AR_RAD2111_SREV_MAJOR: 415 case AR_RAD2413_SREV_MAJOR: 416 case AR_RAD5413_SREV_MAJOR: 417 case AR_RAD5424_SREV_MAJOR: 418 break; 419 default: 420 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 421 /* 422 * When RF_Silent is used, the 423 * analog chip is reset. So when the system boots 424 * up with the radio switch off we cannot determine 425 * the RF chip rev. To workaround this check the 426 * mac+phy revs and if Hainan, set the radio rev 427 * to Derby. 428 */ 429 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 430 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 431 AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 432 AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 433 break; 434 } 435 if (IS_2413(ah)) { /* Griffin */ 436 AH_PRIVATE(ah)->ah_analog5GhzRev = 437 AR_RAD2413_SREV_MAJOR | 0x1; 438 break; 439 } 440 if (IS_5413(ah)) { /* Eagle */ 441 AH_PRIVATE(ah)->ah_analog5GhzRev = 442 AR_RAD5413_SREV_MAJOR | 0x2; 443 break; 444 } 445 if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 446 AH_PRIVATE(ah)->ah_analog5GhzRev = 447 AR_RAD5424_SREV_MAJOR | 0x2; 448 break; 449 } 450 } 451#ifdef AH_DEBUG 452 HALDEBUG(ah, HAL_DEBUG_ANY, 453 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 454 "this driver\n", 455 __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 456 ecode = HAL_ENOTSUPP; 457 goto bad; 458#endif 459 } 460 if (IS_RAD5112_REV1(ah)) { 461 HALDEBUG(ah, HAL_DEBUG_ANY, 462 "%s: 5112 Rev 1 is not supported by this " 463 "driver (analog5GhzRev 0x%x)\n", __func__, 464 AH_PRIVATE(ah)->ah_analog5GhzRev); 465 ecode = HAL_ENOTSUPP; 466 goto bad; 467 } 468 469 val = OS_REG_READ(ah, AR_PCICFG); 470 val = MS(val, AR_PCICFG_EEPROM_SIZE); 471 if (val == 0) { 472 if (!AH_PRIVATE(ah)->ah_ispcie) { 473 HALDEBUG(ah, HAL_DEBUG_ANY, 474 "%s: unsupported EEPROM size %u (0x%x) found\n", 475 __func__, val, val); 476 ecode = HAL_EESIZE; 477 goto bad; 478 } 479 /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 480 } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 481 if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 482 HALDEBUG(ah, HAL_DEBUG_ANY, 483 "%s: unsupported EEPROM size %u (0x%x) found\n", 484 __func__, val, val); 485 ecode = HAL_EESIZE; 486 goto bad; 487 } 488 HALDEBUG(ah, HAL_DEBUG_ANY, 489 "%s: EEPROM size = %d. Must be %d (16k).\n", 490 __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 491 ecode = HAL_EESIZE; 492 goto bad; 493 } 494 ecode = ath_hal_legacyEepromAttach(ah); 495 if (ecode != HAL_OK) { 496 goto bad; 497 } 498 ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 499 500 /* 501 * If Bmode and AR5212, verify 2.4 analog exists 502 */ 503 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 504 (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 505 /* 506 * Set correct Baseband to analog shift 507 * setting to access analog chips. 508 */ 509 OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 510 OS_DELAY(2000); 511 AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 512 513 /* Set baseband for 5GHz chip */ 514 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 515 OS_DELAY(2000); 516 if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 517 HALDEBUG(ah, HAL_DEBUG_ANY, 518 "%s: 2G Radio Chip Rev 0x%02X is not " 519 "supported by this driver\n", __func__, 520 AH_PRIVATE(ah)->ah_analog2GhzRev); 521 ecode = HAL_ENOTSUPP; 522 goto bad; 523 } 524 } 525 526 ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 527 if (ecode != HAL_OK) { 528 HALDEBUG(ah, HAL_DEBUG_ANY, 529 "%s: cannot read regulatory domain from EEPROM\n", 530 __func__); 531 goto bad; 532 } 533 AH_PRIVATE(ah)->ah_currentRD = eeval; 534 /* XXX record serial number */ 535 536 /* 537 * Got everything we need now to setup the capabilities. 538 */ 539 if (!ar5212FillCapabilityInfo(ah)) { 540 HALDEBUG(ah, HAL_DEBUG_ANY, 541 "%s: failed ar5212FillCapabilityInfo\n", __func__); 542 ecode = HAL_EEREAD; 543 goto bad; 544 } 545 546 if (!rf->attach(ah, &ecode)) { 547 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 548 __func__, ecode); 549 goto bad; 550 } 551 /* 552 * Set noise floor adjust method; we arrange a 553 * direct call instead of thunking. 554 */ 555 AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 556 557 /* Initialize gain ladder thermal calibration structure */ 558 ar5212InitializeGainValues(ah); 559 560 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 561 if (ecode != HAL_OK) { 562 HALDEBUG(ah, HAL_DEBUG_ANY, 563 "%s: error getting mac address from EEPROM\n", __func__); 564 goto bad; 565 } 566 567 ar5212AniSetup(ah); 568 /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 569 ar5212InitNfCalHistBuffer(ah); 570 571 /* XXX EAR stuff goes here */ 572 573 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 574 575 return ah; 576 577bad: 578 if (ahp) 579 ar5212Detach((struct ath_hal *) ahp); 580 if (status) 581 *status = ecode; 582 return AH_NULL; 583#undef AH_EEPROM_PROTECT 584} 585 586void 587ar5212Detach(struct ath_hal *ah) 588{ 589 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 590 591 HALASSERT(ah != AH_NULL); 592 HALASSERT(ah->ah_magic == AR5212_MAGIC); 593 594 ar5212AniDetach(ah); 595 ar5212RfDetach(ah); 596 ar5212Disable(ah); 597 ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 598 599 ath_hal_eepromDetach(ah); 600 ath_hal_free(ah); 601} 602 603HAL_BOOL 604ar5212ChipTest(struct ath_hal *ah) 605{ 606 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 607 uint32_t regHold[2]; 608 uint32_t patternData[4] = 609 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 610 int i, j; 611 612 /* Test PHY & MAC registers */ 613 for (i = 0; i < 2; i++) { 614 uint32_t addr = regAddr[i]; 615 uint32_t wrData, rdData; 616 617 regHold[i] = OS_REG_READ(ah, addr); 618 for (j = 0; j < 0x100; j++) { 619 wrData = (j << 16) | j; 620 OS_REG_WRITE(ah, addr, wrData); 621 rdData = OS_REG_READ(ah, addr); 622 if (rdData != wrData) { 623 HALDEBUG(ah, HAL_DEBUG_ANY, 624"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 625 __func__, addr, wrData, rdData); 626 return AH_FALSE; 627 } 628 } 629 for (j = 0; j < 4; j++) { 630 wrData = patternData[j]; 631 OS_REG_WRITE(ah, addr, wrData); 632 rdData = OS_REG_READ(ah, addr); 633 if (wrData != rdData) { 634 HALDEBUG(ah, HAL_DEBUG_ANY, 635"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 636 __func__, addr, wrData, rdData); 637 return AH_FALSE; 638 } 639 } 640 OS_REG_WRITE(ah, regAddr[i], regHold[i]); 641 } 642 OS_DELAY(100); 643 return AH_TRUE; 644} 645 646/* 647 * Store the channel edges for the requested operational mode 648 */ 649HAL_BOOL 650ar5212GetChannelEdges(struct ath_hal *ah, 651 uint16_t flags, uint16_t *low, uint16_t *high) 652{ 653 if (flags & IEEE80211_CHAN_5GHZ) { 654 *low = 4915; 655 *high = 6100; 656 return AH_TRUE; 657 } 658 if ((flags & IEEE80211_CHAN_2GHZ) && 659 (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 660 ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 661 *low = 2312; 662 *high = 2732; 663 return AH_TRUE; 664 } 665 return AH_FALSE; 666} 667 668/* 669 * Disable PLL when in L0s as well as receiver clock when in L1. 670 * This power saving option must be enabled through the Serdes. 671 * 672 * Programming the Serdes must go through the same 288 bit serial shift 673 * register as the other analog registers. Hence the 9 writes. 674 * 675 * XXX Clean up the magic numbers. 676 */ 677static void 678ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 679{ 680 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 681 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 682 683 /* RX shut off when elecidle is asserted */ 684 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 685 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 686 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 687 688 /* Shut off PLL and CLKREQ active in L1 */ 689 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 690 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 691 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 692 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 693 694 /* Load the new settings */ 695 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 696} 697 698static void 699ar5212DisablePCIE(struct ath_hal *ah) 700{ 701 /* NB: fill in for 9100 */ 702} 703 704/* 705 * Fill all software cached or static hardware state information. 706 * Return failure if capabilities are to come from EEPROM and 707 * cannot be read. 708 */ 709HAL_BOOL 710ar5212FillCapabilityInfo(struct ath_hal *ah) 711{ 712#define AR_KEYTABLE_SIZE 128 713#define IS_GRIFFIN_LITE(ah) \ 714 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 715 AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 716#define IS_COBRA(ah) \ 717 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 718#define IS_2112(ah) \ 719 ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 720 721 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 722 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 723 uint16_t capField, val; 724 725 /* Read the capability EEPROM location */ 726 if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 727 HALDEBUG(ah, HAL_DEBUG_ANY, 728 "%s: unable to read caps from eeprom\n", __func__); 729 return AH_FALSE; 730 } 731 if (IS_2112(ah)) 732 ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 733 if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 734 /* 735 * For griffin-lite cards with unprogrammed capabilities. 736 */ 737 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 738 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 739 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 740 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 741 HALDEBUG(ah, HAL_DEBUG_ATTACH, 742 "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 743 __func__, capField); 744 } 745 746 /* Modify reg domain on newer cards that need to work with older sw */ 747 if (ahpriv->ah_opmode != HAL_M_HOSTAP && 748 ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 749 if (ahpriv->ah_currentRD == 0x64 || 750 ahpriv->ah_currentRD == 0x65) 751 ahpriv->ah_currentRD += 5; 752 else if (ahpriv->ah_currentRD == 0x41) 753 ahpriv->ah_currentRD = 0x43; 754 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 755 __func__, ahpriv->ah_currentRD); 756 } 757 758 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 759 AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 760 HALDEBUG(ah, HAL_DEBUG_ATTACH, 761 "%s: enable Bmode and disable turbo for Swan/Nala\n", 762 __func__); 763 ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 764 ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 765 ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 766 ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 767 ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 768 } 769 770 /* Construct wireless mode from EEPROM */ 771 pCap->halWirelessModes = 0; 772 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 773 pCap->halWirelessModes |= HAL_MODE_11A; 774 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 775 pCap->halWirelessModes |= HAL_MODE_TURBO; 776 } 777 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 778 pCap->halWirelessModes |= HAL_MODE_11B; 779 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 780 ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 781 pCap->halWirelessModes |= HAL_MODE_11G; 782 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 783 pCap->halWirelessModes |= HAL_MODE_108G; 784 } 785 786 pCap->halLow2GhzChan = 2312; 787 /* XXX 2417 too? */ 788 if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 789 pCap->halHigh2GhzChan = 2500; 790 else 791 pCap->halHigh2GhzChan = 2732; 792 793 /* 794 * For AR5111 version < 4, the lowest centre frequency supported is 795 * 5130MHz. For AR5111 version 4, the 4.9GHz channels are supported 796 * but only in 10MHz increments. 797 * 798 * In addition, the programming method is wrong - it uses the IEEE 799 * channel number to calculate the frequency, rather than the 800 * channel centre. Since half/quarter rates re-use some of the 801 * 5GHz channel IEEE numbers, this will result in a badly programmed 802 * synth. 803 * 804 * Until the relevant support is written, just limit lower frequency 805 * support for AR5111 so things aren't incorrectly programmed. 806 * 807 * XXX It's also possible this code doesn't correctly limit the 808 * centre frequencies of potential channels; this is very important 809 * for half/quarter rate! 810 */ 811 if (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR) { 812 pCap->halLow5GhzChan = 5120; /* XXX lowest centre = 5130MHz */ 813 } else { 814 pCap->halLow5GhzChan = 4915; 815 } 816 pCap->halHigh5GhzChan = 6100; 817 818 pCap->halCipherCkipSupport = AH_FALSE; 819 pCap->halCipherTkipSupport = AH_TRUE; 820 pCap->halCipherAesCcmSupport = 821 (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 822 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 823 ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 824 (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 825 826 pCap->halMicCkipSupport = AH_FALSE; 827 pCap->halMicTkipSupport = AH_TRUE; 828 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 829 /* 830 * Starting with Griffin TX+RX mic keys can be combined 831 * in one key cache slot. 832 */ 833 if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 834 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 835 else 836 pCap->halTkipMicTxRxKeySupport = AH_FALSE; 837 pCap->halChanSpreadSupport = AH_TRUE; 838 pCap->halSleepAfterBeaconBroken = AH_TRUE; 839 840 if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 841 pCap->halCompressSupport = 842 ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 843 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 844 pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 845 pCap->halFastFramesSupport = 846 ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 847 (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 848 pCap->halChapTuningSupport = AH_TRUE; 849 pCap->halTurboPrimeSupport = AH_TRUE; 850 } 851 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 852 853 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 854 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 855 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 856 pCap->halVEOLSupport = AH_TRUE; 857 pCap->halBssIdMaskSupport = AH_TRUE; 858 pCap->halMcastKeySrchSupport = AH_TRUE; 859 if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 860 ahpriv->ah_macRev == 8) || 861 ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 862 pCap->halTsfAddSupport = AH_TRUE; 863 864 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 865 pCap->halTotalQueues = val; 866 else 867 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 868 869 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 870 pCap->halKeyCacheSize = val; 871 else 872 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 873 874 pCap->halChanHalfRate = AH_TRUE; 875 pCap->halChanQuarterRate = AH_TRUE; 876 877 /* 878 * RSSI uses the combined field; some 11n NICs may use 879 * the control chain RSSI. 880 */ 881 pCap->halUseCombinedRadarRssi = AH_TRUE; 882 883 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 884 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 885 /* NB: enabled by default */ 886 ahpriv->ah_rfkillEnabled = AH_TRUE; 887 pCap->halRfSilentSupport = AH_TRUE; 888 } 889 890 /* NB: this is a guess, no one seems to know the answer */ 891 ahpriv->ah_rxornIsFatal = 892 (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 893 894 /* enable features that first appeared in Hainan */ 895 if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 896 AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 897 AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 898 /* h/w phy counters */ 899 pCap->halHwPhyCounterSupport = AH_TRUE; 900 /* bssid match disable */ 901 pCap->halBssidMatchSupport = AH_TRUE; 902 } 903 904 pCap->halRxTstampPrecision = 15; 905 pCap->halTxTstampPrecision = 16; 906 pCap->halIntrMask = HAL_INT_COMMON 907 | HAL_INT_RX 908 | HAL_INT_TX 909 | HAL_INT_FATAL 910 | HAL_INT_BNR 911 | HAL_INT_BMISC 912 ; 913 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 914 pCap->halIntrMask &= ~HAL_INT_TBTT; 915 916 pCap->hal4kbSplitTransSupport = AH_TRUE; 917 pCap->halHasRxSelfLinkedTail = AH_TRUE; 918 919 return AH_TRUE; 920#undef IS_COBRA 921#undef IS_GRIFFIN_LITE 922#undef AR_KEYTABLE_SIZE 923} 924 925static const char* 926ar5212Probe(uint16_t vendorid, uint16_t devid) 927{ 928 if (vendorid == ATHEROS_VENDOR_ID || 929 vendorid == ATHEROS_3COM_VENDOR_ID || 930 vendorid == ATHEROS_3COM2_VENDOR_ID) { 931 switch (devid) { 932 case AR5212_FPGA: 933 return "Atheros 5212 (FPGA)"; 934 case AR5212_DEVID: 935 case AR5212_DEVID_IBM: 936 case AR5212_DEFAULT: 937 return "Atheros 5212"; 938 case AR5212_AR2413: 939 return "Atheros 2413"; 940 case AR5212_AR2417: 941 return "Atheros 2417"; 942 case AR5212_AR5413: 943 return "Atheros 5413"; 944 case AR5212_AR5424: 945 return "Atheros 5424/2424"; 946 } 947 } 948 return AH_NULL; 949} 950AH_CHIP(AR5212, ar5212Probe, ar5212Attach); 951