1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17/* 18 * READ THIS NOTICE! 19 * 20 * Values defined in this file may only be changed under exceptional circumstances. 21 * 22 * Please ask Fiona Cain before making any changes. 23 */ 24 25#ifndef __ar9300template_wasp_2_h__ 26#define __ar9300template_wasp_2_h__ 27static ar9300_eeprom_t ar9300_template_wasp_2= 28{ 29 30 2, // eepromVersion; 31 32 ar9300_eeprom_template_wasp_2, // templateVersion; 33 34 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; 35 36 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 37 38 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 39 40 //static OSPREY_BASE_EEP_HEADER baseEepHeader= 41 42 { 43 {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 44 0x33, // txrxMask; //4 bits tx and 4 bits rx 45 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 3}, // opCapFlags; 46 0, // rfSilent; 47 0, // blueToothOptions; 48 0, // deviceCap; 49 4, // deviceType; // takes lower byte in eeprom location 50 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 51 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 52 0x0c, //featureEnable; //bit0 - enable tx temp comp 53 //bit1 - enable tx volt comp 54 //bit2 - enable fastClock - default to 1 55 //bit3 - enable doubling - default to 1 56 //bit4 - enable internal regulator - default to 0 57 0, //miscConfiguration: bit0 - turn down drivestrength 58 3, // eepromWriteEnableGpio 59 0, // wlanDisableGpio 60 8, // wlanLedGpio 61 0xff, // rxBandSelectGpio 62 0, // txrxgain 63 0, // swreg 64 }, 65 66 67 //static OSPREY_MODAL_EEP_HEADER modalHeader2G= 68 { 69 70 0x220, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) 71 0x88888, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 72 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 73 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 74 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 75 36, // tempSlope; 76 0, // voltSlope; 77 {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 78 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 79 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 80 0, // quick drop 81 0, // xpaBiasLvl; // 1 82 0x0e, // txFrameToDataStart; // 1 83 0x0e, // txFrameToPaOn; // 1 84 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 85 0, // antennaGain; // 1 86 0x2c, // switchSettling; // 1 87 -30, // adcDesiredSize; // 1 88 0, // txEndToXpaOff; // 1 89 0x2, // txEndToRxOn; // 1 90 0xe, // txFrameToXpaOn; // 1 91 28, // thresh62; // 1 92 0x0c80C080, // papdRateMaskHt20 // 4 93 0x0080C080, // papdRateMaskHt40 94 0, // switchcomspdt; // 2 95 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 96 0, // rf_gain_cap 97 0, // tx_gain_cap 98 {0,0,0,0,0} //futureModal[5]; 99 }, 100 101 { 102 0, // ant_div_control 103 {0,0}, // base_ext1 104 0, // misc_enable 105 {0,0,0,0,0,0,0,0}, // temp slop extension 106 0, // quick drop low 107 0, // quick drop high 108 }, 109 110 //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]= 111 { 112 FREQ2FBIN(2412, 1), 113 FREQ2FBIN(2437, 1), 114 FREQ2FBIN(2472, 1) 115 }, 116 117 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 118 119 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 120 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 121 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 122 }, 123 124 //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 125 126 { 127 FREQ2FBIN(2412, 1), 128 FREQ2FBIN(2484, 1) 129 }, 130 131 //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS] 132 { 133 FREQ2FBIN(2412, 1), 134 FREQ2FBIN(2437, 1), 135 FREQ2FBIN(2472, 1) 136 }, 137 138 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS] 139 { 140 FREQ2FBIN(2412, 1), 141 FREQ2FBIN(2437, 1), 142 FREQ2FBIN(2472, 1) 143 }, 144 145 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS] 146 { 147 FREQ2FBIN(2412, 1), 148 FREQ2FBIN(2437, 1), 149 FREQ2FBIN(2472, 1) 150 }, 151 152 //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 153 { 154 //1L-5L,5S,11L,11S 155 {{36,36,36,36}}, 156 {{36,36,36,36}} 157 }, 158 159 //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]= 160 { 161 //6-24,36,48,54 162 {{32,32,28,24}}, 163 {{32,32,28,24}}, 164 {{32,32,28,24}}, 165 }, 166 167 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]= 168 { 169 //0_8_16,1-3_9-11_17-19, 170 // 4,5,6,7,12,13,14,15,20,21,22,23 171 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 172 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 173 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 174 }, 175 176 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]= 177 { 178 //0_8_16,1-3_9-11_17-19, 179 // 4,5,6,7,12,13,14,15,20,21,22,23 180 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 181 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 182 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}}, 183 }, 184 185//static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]= 186 187 { 188 189 0x11, 190 0x12, 191 0x15, 192 0x17, 193 0x41, 194 0x42, 195 0x45, 196 0x47, 197 0x31, 198 0x32, 199 0x35, 200 0x37 201 202 }, 203 204//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 205 206 { 207 {FREQ2FBIN(2412, 1), 208 FREQ2FBIN(2417, 1), 209 FREQ2FBIN(2457, 1), 210 FREQ2FBIN(2462, 1)}, 211 212 {FREQ2FBIN(2412, 1), 213 FREQ2FBIN(2417, 1), 214 FREQ2FBIN(2462, 1), 215 0xFF}, 216 217 {FREQ2FBIN(2412, 1), 218 FREQ2FBIN(2417, 1), 219 FREQ2FBIN(2462, 1), 220 0xFF}, 221 222 {FREQ2FBIN(2422, 1), 223 FREQ2FBIN(2427, 1), 224 FREQ2FBIN(2447, 1), 225 FREQ2FBIN(2452, 1)}, 226 227 {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 228 /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 229 /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 230 /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)}, 231 232 {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 233 /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 234 /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 235 0}, 236 237 {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 238 /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 239 FREQ2FBIN(2472, 1), 240 0}, 241 242 {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), 243 /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), 244 /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), 245 /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}, 246 247 {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 248 /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 249 /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 250 0}, 251 252 {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 253 /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 254 /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 255 0}, 256 257 {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 258 /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 259 /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 260 0}, 261 262 {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), 263 /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), 264 /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), 265 /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)} 266 }, 267 268 269//OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G]; 270 271#if AH_BYTE_ORDER == AH_BIG_ENDIAN 272 { 273 274 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 275 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 276 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 277 278 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, 279 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 280 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 281 282 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 283 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 284 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 285 286 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 287 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 288 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 289 290 }, 291#else 292 { 293 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 294 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 295 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 296 297 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, 298 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 299 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 300 301 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 302 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 303 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 304 305 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 306 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 307 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 308 }, 309#endif 310 311//static OSPREY_MODAL_EEP_HEADER modalHeader5G= 312 313 { 314 315 0x440, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) 316 0x11111, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 317 {0x000,0x000,0x000}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 318 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 319 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 320 68, // tempSlope; 321 0, // voltSlope; 322 {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 323 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 324 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 325 0, // quick drop 326 0, // xpaBiasLvl; // 1 327 0x0e, // txFrameToDataStart; // 1 328 0x0e, // txFrameToPaOn; // 1 329 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 330 0, // antennaGain; // 1 331 0x2d, // switchSettling; // 1 332 -30, // adcDesiredSize; // 1 333 0, // txEndToXpaOff; // 1 334 0x2, // txEndToRxOn; // 1 335 0xe, // txFrameToXpaOn; // 1 336 28, // thresh62; // 1 337 0x0cf0e0e0, // papdRateMaskHt20 // 4 338 0x6cf0e0e0, // papdRateMaskHt40 // 4 339 0, // switchcomspdt; // 2 340 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 341 0, // rf_gain_cap 342 0, // tx_gain_cap 343 {0,0,0,0,0} //futureModal[5]; 344 }, 345 346 { // base_ext2 347 0, 348 0, 349 {0,0,0}, 350 {0,0,0}, 351 {0,0,0}, 352 {0,0,0} 353 }, 354 355//static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]= 356 { 357 //pPiers[0] = 358 FREQ2FBIN(5180, 0), 359 //pPiers[1] = 360 FREQ2FBIN(5220, 0), 361 //pPiers[2] = 362 FREQ2FBIN(5320, 0), 363 //pPiers[3] = 364 FREQ2FBIN(5400, 0), 365 //pPiers[4] = 366 FREQ2FBIN(5500, 0), 367 //pPiers[5] = 368 FREQ2FBIN(5600, 0), 369 //pPiers[6] = 370 FREQ2FBIN(5725, 0), 371 //pPiers[7] = 372 FREQ2FBIN(5825, 0) 373 }, 374 375//static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 376 377 { 378 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 379 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 380 {{0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}, {0,0,0,0,0}}, 381 382 }, 383 384//static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]= 385 386 { 387 FREQ2FBIN(5180, 0), 388 FREQ2FBIN(5220, 0), 389 FREQ2FBIN(5320, 0), 390 FREQ2FBIN(5400, 0), 391 FREQ2FBIN(5500, 0), 392 FREQ2FBIN(5600, 0), 393 FREQ2FBIN(5725, 0), 394 FREQ2FBIN(5825, 0) 395 }, 396 397//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= 398 399 { 400 FREQ2FBIN(5180, 0), 401 FREQ2FBIN(5240, 0), 402 FREQ2FBIN(5320, 0), 403 FREQ2FBIN(5500, 0), 404 FREQ2FBIN(5700, 0), 405 FREQ2FBIN(5745, 0), 406 FREQ2FBIN(5725, 0), 407 FREQ2FBIN(5825, 0) 408 }, 409 410//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= 411 412 { 413 FREQ2FBIN(5180, 0), 414 FREQ2FBIN(5240, 0), 415 FREQ2FBIN(5320, 0), 416 FREQ2FBIN(5500, 0), 417 FREQ2FBIN(5700, 0), 418 FREQ2FBIN(5745, 0), 419 FREQ2FBIN(5725, 0), 420 FREQ2FBIN(5825, 0) 421 }, 422 423 424//static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]= 425 426 427 { 428 //6-24,36,48,54 429 {{20,20,20,10}}, 430 {{20,20,20,10}}, 431 {{20,20,20,10}}, 432 {{20,20,20,10}}, 433 {{20,20,20,10}}, 434 {{20,20,20,10}}, 435 {{20,20,20,10}}, 436 {{20,20,20,10}}, 437 }, 438 439//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= 440 441 { 442 //0_8_16,1-3_9-11_17-19, 443 // 4,5,6,7,12,13,14,15,20,21,22,23 444 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 445 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 446 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 447 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 448 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 449 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 450 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 451 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 452 }, 453 454//static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= 455 { 456 //0_8_16,1-3_9-11_17-19, 457 // 4,5,6,7,12,13,14,15,20,21,22,23 458 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 459 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 460 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 461 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 462 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 463 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 464 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 465 {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}}, 466 }, 467 468//static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]= 469 470 { 471 //pCtlIndex[0] = 472 0x10, 473 //pCtlIndex[1] = 474 0x16, 475 //pCtlIndex[2] = 476 0x18, 477 //pCtlIndex[3] = 478 0x40, 479 //pCtlIndex[4] = 480 0x46, 481 //pCtlIndex[5] = 482 0x48, 483 //pCtlIndex[6] = 484 0x30, 485 //pCtlIndex[7] = 486 0x36, 487 //pCtlIndex[8] = 488 0x38 489 }, 490 491// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 492 493 { 494 {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 495 /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 496 /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), 497 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), 498 /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0), 499 /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 500 /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), 501 /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, 502 503 {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 504 /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 505 /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), 506 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), 507 /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0), 508 /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 509 /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), 510 /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, 511 512 {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), 513 /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), 514 /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), 515 /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0), 516 /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0), 517 /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0), 518 /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0), 519 /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)}, 520 521 {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 522 /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), 523 /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0), 524 /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0), 525 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), 526 /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 527 /* Data[3].ctlEdges[6].bChannel*/0xFF, 528 /* Data[3].ctlEdges[7].bChannel*/0xFF}, 529 530 {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 531 /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 532 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0), 533 /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0), 534 /* Data[4].ctlEdges[4].bChannel*/0xFF, 535 /* Data[4].ctlEdges[5].bChannel*/0xFF, 536 /* Data[4].ctlEdges[6].bChannel*/0xFF, 537 /* Data[4].ctlEdges[7].bChannel*/0xFF}, 538 539 {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), 540 /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0), 541 /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0), 542 /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), 543 /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0), 544 /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), 545 /* Data[5].ctlEdges[6].bChannel*/0xFF, 546 /* Data[5].ctlEdges[7].bChannel*/0xFF}, 547 548 {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 549 /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), 550 /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0), 551 /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0), 552 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), 553 /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0), 554 /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0), 555 /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)}, 556 557 {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 558 /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 559 /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0), 560 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), 561 /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0), 562 /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 563 /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), 564 /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, 565 566 {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), 567 /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), 568 /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), 569 /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), 570 /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0), 571 /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), 572 /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0), 573 /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)} 574 }, 575 576//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 577 578#if AH_BYTE_ORDER == AH_BIG_ENDIAN 579 { 580 {{{1, 60}, 581 {1, 60}, 582 {1, 60}, 583 {1, 60}, 584 {1, 60}, 585 {1, 60}, 586 {1, 60}, 587 {0, 60}}}, 588 589 {{{1, 60}, 590 {1, 60}, 591 {1, 60}, 592 {1, 60}, 593 {1, 60}, 594 {1, 60}, 595 {1, 60}, 596 {0, 60}}}, 597 598 {{{0, 60}, 599 {1, 60}, 600 {0, 60}, 601 {1, 60}, 602 {1, 60}, 603 {1, 60}, 604 {1, 60}, 605 {1, 60}}}, 606 607 {{{0, 60}, 608 {1, 60}, 609 {1, 60}, 610 {0, 60}, 611 {1, 60}, 612 {0, 60}, 613 {0, 60}, 614 {0, 60}}}, 615 616 {{{1, 60}, 617 {1, 60}, 618 {1, 60}, 619 {0, 60}, 620 {0, 60}, 621 {0, 60}, 622 {0, 60}, 623 {0, 60}}}, 624 625 {{{1, 60}, 626 {1, 60}, 627 {1, 60}, 628 {1, 60}, 629 {1, 60}, 630 {0, 60}, 631 {0, 60}, 632 {0, 60}}}, 633 634 {{{1, 60}, 635 {1, 60}, 636 {1, 60}, 637 {1, 60}, 638 {1, 60}, 639 {1, 60}, 640 {1, 60}, 641 {1, 60}}}, 642 643 {{{1, 60}, 644 {1, 60}, 645 {0, 60}, 646 {1, 60}, 647 {1, 60}, 648 {1, 60}, 649 {1, 60}, 650 {0, 60}}}, 651 652 {{{1, 60}, 653 {0, 60}, 654 {1, 60}, 655 {1, 60}, 656 {1, 60}, 657 {1, 60}, 658 {0, 60}, 659 {1, 60}}}, 660 } 661#else 662 { 663 {{{60, 1}, 664 {60, 1}, 665 {60, 1}, 666 {60, 1}, 667 {60, 1}, 668 {60, 1}, 669 {60, 1}, 670 {60, 0}}}, 671 672 {{{60, 1}, 673 {60, 1}, 674 {60, 1}, 675 {60, 1}, 676 {60, 1}, 677 {60, 1}, 678 {60, 1}, 679 {60, 0}}}, 680 681 {{{60, 0}, 682 {60, 1}, 683 {60, 0}, 684 {60, 1}, 685 {60, 1}, 686 {60, 1}, 687 {60, 1}, 688 {60, 1}}}, 689 690 {{{60, 0}, 691 {60, 1}, 692 {60, 1}, 693 {60, 0}, 694 {60, 1}, 695 {60, 0}, 696 {60, 0}, 697 {60, 0}}}, 698 699 {{{60, 1}, 700 {60, 1}, 701 {60, 1}, 702 {60, 0}, 703 {60, 0}, 704 {60, 0}, 705 {60, 0}, 706 {60, 0}}}, 707 708 {{{60, 1}, 709 {60, 1}, 710 {60, 1}, 711 {60, 1}, 712 {60, 1}, 713 {60, 0}, 714 {60, 0}, 715 {60, 0}}}, 716 717 {{{60, 1}, 718 {60, 1}, 719 {60, 1}, 720 {60, 1}, 721 {60, 1}, 722 {60, 1}, 723 {60, 1}, 724 {60, 1}}}, 725 726 {{{60, 1}, 727 {60, 1}, 728 {60, 0}, 729 {60, 1}, 730 {60, 1}, 731 {60, 1}, 732 {60, 1}, 733 {60, 0}}}, 734 735 {{{60, 1}, 736 {60, 0}, 737 {60, 1}, 738 {60, 1}, 739 {60, 1}, 740 {60, 1}, 741 {60, 0}, 742 {60, 1}}}, 743 } 744#endif 745}; 746 747#endif 748