1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17/* 18 * READ THIS NOTICE! 19 * 20 * Values defined in this file may only be changed under exceptional circumstances. 21 * 22 * Please ask Fiona Cain before making any changes. 23 */ 24 25 26#ifndef __ar9300templateHB116_h__ 27#define __ar9300templateHB116_h__ 28 29static ar9300_eeprom_t ar9300_template_hb116= 30{ 31 32 2, // eeprom_version; 33 34 ar9300_eeprom_template_hb116, // template_version; 35 36 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; 37 38 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 39 40 {"hb116-041-f0000"}, 41// {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 42 43 //static OSPREY_BASE_EEP_HEADER base_eep_header= 44 45 { 46 {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 47 0x33, // txrx_mask; //4 bits tx and 4 bits rx 48 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; 49 0, // rf_silent; 50 0, // blue_tooth_options; 51 0, // device_cap; 52 5, // device_type; // takes lower byte in eeprom location 53 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 54 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 55 0x0d, //feature_enable; //bit0 - enable tx temp comp 56 //bit1 - enable tx volt comp 57 //bit2 - enable fastClock - default to 1 58 //bit3 - enable doubling - default to 1 59 //bit4 - enable internal regulator - default to 0 60 //bit5 - enable paprd -- default to 0 61 0, //misc_configuration: bit0 - turn down drivestrength 62 6, // eeprom_write_enable_gpio 63 0, // wlan_disable_gpio 64 8, // wlan_led_gpio 65 0xff, // rx_band_select_gpio 66 0x10, // txrxgain 67 0, // swreg 68 }, 69 70 71 //static OSPREY_MODAL_EEP_HEADER modal_header_2g= 72 { 73 74 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 75 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 76 {0x10,0x10,0x10}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 77 {0x1f,0x1f,0x1f}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 78 {0x12,0x12,0x12}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 79 25, // temp_slope; 80 0, // voltSlope; 81 {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 82 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 83 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 84 0, // quick drop 85 0, // xpa_bias_lvl; // 1 86 0x0e, // tx_frame_to_data_start; // 1 87 0x0e, // tx_frame_to_pa_on; // 1 88 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 89 0, // antenna_gain; // 1 90 0x2c, // switchSettling; // 1 91 -30, // adcDesiredSize; // 1 92 0, // txEndToXpaOff; // 1 93 0x2, // txEndToRxOn; // 1 94 0xe, // tx_frame_to_xpa_on; // 1 95 28, // thresh62; // 1 96 0x0c80C080, // paprd_rate_mask_ht20 // 4 97 0x0080C080, // paprd_rate_mask_ht40 98 0, // switchcomspdt; // 2 99 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 100 0, // rf_gain_cap 101 0, // tx_gain_cap 102 {0,0,0,0,0} //futureModal[5]; 103 }, 104 105 { 106 0, // ant_div_control 107 {0,0}, // base_ext1 108 0, // misc_enable 109 {0,0,0,0,0,0,0,0}, // temp slop extension 110 0, // quick drop low 111 0, // quick drop high 112 }, 113 114 //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= 115 { 116 FREQ2FBIN(2412, 1), 117 FREQ2FBIN(2437, 1), 118 FREQ2FBIN(2462, 1) 119 }, 120 121 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 122 123 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 124 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 125 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 126 }, 127 128 //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 129 130 { 131 FREQ2FBIN(2412, 1), 132 FREQ2FBIN(2472, 1) 133 }, 134 135 //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] 136 { 137 FREQ2FBIN(2412, 1), 138 FREQ2FBIN(2437, 1), 139 FREQ2FBIN(2472, 1) 140 }, 141 142 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] 143 { 144 FREQ2FBIN(2412, 1), 145 FREQ2FBIN(2437, 1), 146 FREQ2FBIN(2472, 1) 147 }, 148 149 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] 150 { 151 FREQ2FBIN(2412, 1), 152 FREQ2FBIN(2437, 1), 153 FREQ2FBIN(2472, 1) 154 }, 155 156 //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 157 { 158 //1L-5L,5S,11L,11S 159 {{34,34,34,34}}, 160 {{34,34,34,34}} 161 }, 162 163 //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= 164 { 165 //6-24,36,48,54 166 {{34,34,32,32}}, 167 {{34,34,32,32}}, 168 {{34,34,32,32}}, 169 }, 170 171 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= 172 { 173 //0_8_16,1-3_9-11_17-19, 174 // 4,5,6,7,12,13,14,15,20,21,22,23 175 {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, 176 {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, 177 {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, 178 }, 179 180 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= 181 { 182 //0_8_16,1-3_9-11_17-19, 183 // 4,5,6,7,12,13,14,15,20,21,22,23 184 {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, 185 {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, 186 {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, 187 }, 188 189//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= 190 191 { 192 193 0x11, 194 0x12, 195 0x15, 196 0x17, 197 0x41, 198 0x42, 199 0x45, 200 0x47, 201 0x31, 202 0x32, 203 0x35, 204 0x37 205 206 }, 207 208//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 209 210 { 211 {FREQ2FBIN(2412, 1), 212 FREQ2FBIN(2417, 1), 213 FREQ2FBIN(2457, 1), 214 FREQ2FBIN(2462, 1)}, 215 216 {FREQ2FBIN(2412, 1), 217 FREQ2FBIN(2417, 1), 218 FREQ2FBIN(2462, 1), 219 0xFF}, 220 221 {FREQ2FBIN(2412, 1), 222 FREQ2FBIN(2417, 1), 223 FREQ2FBIN(2462, 1), 224 0xFF}, 225 226 {FREQ2FBIN(2422, 1), 227 FREQ2FBIN(2427, 1), 228 FREQ2FBIN(2447, 1), 229 FREQ2FBIN(2452, 1)}, 230 231 {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 232 /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 233 /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 234 /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, 235 236 {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 237 /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 238 /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 239 0}, 240 241 {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 242 /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 243 FREQ2FBIN(2472, 1), 244 0}, 245 246 {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 247 /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 248 /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 249 /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, 250 251 {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 252 /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 253 /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 254 0}, 255 256 {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 257 /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 258 /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 259 0}, 260 261 {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 262 /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 263 /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 264 0}, 265 266 {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 267 /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 268 /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 269 /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} 270 }, 271 272 273//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 274 275#if AH_BYTE_ORDER == AH_BIG_ENDIAN 276 { 277 278 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 279 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 280 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 281 282 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, 283 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 284 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 285 286 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 287 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 288 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 289 290 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 291 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 292 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 293 294 }, 295#else 296 { 297 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 298 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 299 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 300 301 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, 302 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 303 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 304 305 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 306 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 307 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 308 309 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 310 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 311 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 312 }, 313#endif 314 315//static OSPREY_MODAL_EEP_HEADER modal_header_5g= 316 317 { 318 319 0x220, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 320 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 321 {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 322 {0x19,0x19,0x19}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 323 {0x14,0x14,0x14}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 324 70, // temp_slope; 325 0, // voltSlope; 326 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 327 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 328 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 329 0, // quick drop 330 0, // xpa_bias_lvl; // 1 331 0x0e, // tx_frame_to_data_start; // 1 332 0x0e, // tx_frame_to_pa_on; // 1 333 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 334 0, // antenna_gain; // 1 335 0x2d, // switchSettling; // 1 336 -30, // adcDesiredSize; // 1 337 0, // txEndToXpaOff; // 1 338 0x2, // txEndToRxOn; // 1 339 0xe, // tx_frame_to_xpa_on; // 1 340 28, // thresh62; // 1 341 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 342 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 343 0, // switchcomspdt; // 2 344 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 345 0, // rf_gain_cap 346 0, // tx_gain_cap 347 {0,0,0,0,0} //futureModal[5]; 348 }, 349 350 { // base_ext2 351 35, // temp_slope_low 352 50, // temp_slope_high 353 {0,0,0}, 354 {0,0,0}, 355 {0,0,0}, 356 {0,0,0} 357 }, 358 359//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= 360 { 361 //pPiers[0] = 362 FREQ2FBIN(5160, 0), 363 //pPiers[1] = 364 FREQ2FBIN(5220, 0), 365 //pPiers[2] = 366 FREQ2FBIN(5320, 0), 367 //pPiers[3] = 368 FREQ2FBIN(5400, 0), 369 //pPiers[4] = 370 FREQ2FBIN(5500, 0), 371 //pPiers[5] = 372 FREQ2FBIN(5600, 0), 373 //pPiers[6] = 374 FREQ2FBIN(5700, 0), 375 //pPiers[7] = 376 FREQ2FBIN(5785, 0), 377 }, 378 379//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 380 381 { 382 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 383 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 384 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 385 386 }, 387 388//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 389 390 { 391 FREQ2FBIN(5180, 0), 392 FREQ2FBIN(5240, 0), 393 FREQ2FBIN(5320, 0), 394 FREQ2FBIN(5400, 0), 395 FREQ2FBIN(5500, 0), 396 FREQ2FBIN(5600, 0), 397 FREQ2FBIN(5700, 0), 398 FREQ2FBIN(5825, 0) 399 }, 400 401//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 402 403 { 404 FREQ2FBIN(5180, 0), 405 FREQ2FBIN(5240, 0), 406 FREQ2FBIN(5320, 0), 407 FREQ2FBIN(5400, 0), 408 FREQ2FBIN(5500, 0), 409 FREQ2FBIN(5700, 0), 410 FREQ2FBIN(5745, 0), 411 FREQ2FBIN(5825, 0) 412 }, 413 414//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 415 416 { 417 FREQ2FBIN(5180, 0), 418 FREQ2FBIN(5240, 0), 419 FREQ2FBIN(5320, 0), 420 FREQ2FBIN(5400, 0), 421 FREQ2FBIN(5500, 0), 422 FREQ2FBIN(5700, 0), 423 FREQ2FBIN(5745, 0), 424 FREQ2FBIN(5825, 0) 425 }, 426 427 428//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 429 430 431 { 432 //6-24,36,48,54 433 {{30,30,28,24}}, 434 {{30,30,28,24}}, 435 {{30,30,28,24}}, 436 {{30,30,28,24}}, 437 {{30,30,28,24}}, 438 {{30,30,28,24}}, 439 {{30,30,28,24}}, 440 {{30,30,28,24}}, 441 }, 442 443//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 444 445 { 446 //0_8_16,1-3_9-11_17-19, 447 // 4,5,6,7,12,13,14,15,20,21,22,23 448 {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}}, 449 {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}}, 450 {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}}, 451 {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}}, 452 {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}}, 453 {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}}, 454 {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}}, 455 {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}}, 456 }, 457 458//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 459 { 460 //0_8_16,1-3_9-11_17-19, 461 // 4,5,6,7,12,13,14,15,20,21,22,23 462 {{28,28,28,26,22,18,28,26,22,18,0,0,0,0}}, 463 {{28,28,28,26,22,18,28,26,22,18,0,0,0,0}}, 464 {{28,28,28,24,20,16,28,24,20,16,0,0,0,0}}, 465 {{28,28,28,24,20,16,28,24,20,16,0,0,0,0}}, 466 {{28,28,28,22,18,14,28,22,18,14,0,0,0,0}}, 467 {{28,28,28,22,18,14,28,22,18,14,0,0,0,0}}, 468 {{28,28,28,20,16,12,28,20,16,12,0,0,0,0}}, 469 {{28,28,28,20,16,12,28,20,16,12,0,0,0,0}}, 470 }, 471 472//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= 473 474 { 475 //pCtlIndex[0] = 476 0x10, 477 //pCtlIndex[1] = 478 0x16, 479 //pCtlIndex[2] = 480 0x18, 481 //pCtlIndex[3] = 482 0x40, 483 //pCtlIndex[4] = 484 0x46, 485 //pCtlIndex[5] = 486 0x48, 487 //pCtlIndex[6] = 488 0x30, 489 //pCtlIndex[7] = 490 0x36, 491 //pCtlIndex[8] = 492 0x38 493 }, 494 495// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 496 497 { 498 {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 499 /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 500 /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 501 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 502 /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), 503 /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 504 /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 505 /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 506 507 {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 508 /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 509 /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 510 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 511 /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), 512 /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 513 /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 514 /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 515 516 {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 517 /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 518 /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 519 /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), 520 /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), 521 /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), 522 /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), 523 /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, 524 525 {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 526 /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 527 /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), 528 /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), 529 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 530 /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 531 /* Data[3].ctl_edges[6].bChannel*/0xFF, 532 /* Data[3].ctl_edges[7].bChannel*/0xFF}, 533 534 {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 535 /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 536 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), 537 /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), 538 /* Data[4].ctl_edges[4].bChannel*/0xFF, 539 /* Data[4].ctl_edges[5].bChannel*/0xFF, 540 /* Data[4].ctl_edges[6].bChannel*/0xFF, 541 /* Data[4].ctl_edges[7].bChannel*/0xFF}, 542 543 {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 544 /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), 545 /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), 546 /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 547 /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), 548 /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 549 /* Data[5].ctl_edges[6].bChannel*/0xFF, 550 /* Data[5].ctl_edges[7].bChannel*/0xFF}, 551 552 {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 553 /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 554 /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), 555 /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), 556 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 557 /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), 558 /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), 559 /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, 560 561 {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 562 /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 563 /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), 564 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 565 /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), 566 /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 567 /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 568 /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 569 570 {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 571 /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 572 /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 573 /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 574 /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), 575 /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 576 /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), 577 /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} 578 }, 579 580//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 581 582#if AH_BYTE_ORDER == AH_BIG_ENDIAN 583 { 584 {{{1, 60}, 585 {1, 60}, 586 {1, 60}, 587 {1, 60}, 588 {1, 60}, 589 {1, 60}, 590 {1, 60}, 591 {0, 60}}}, 592 593 {{{1, 60}, 594 {1, 60}, 595 {1, 60}, 596 {1, 60}, 597 {1, 60}, 598 {1, 60}, 599 {1, 60}, 600 {0, 60}}}, 601 602 {{{0, 60}, 603 {1, 60}, 604 {0, 60}, 605 {1, 60}, 606 {1, 60}, 607 {1, 60}, 608 {1, 60}, 609 {1, 60}}}, 610 611 {{{0, 60}, 612 {1, 60}, 613 {1, 60}, 614 {0, 60}, 615 {1, 60}, 616 {0, 60}, 617 {0, 60}, 618 {0, 60}}}, 619 620 {{{1, 60}, 621 {1, 60}, 622 {1, 60}, 623 {0, 60}, 624 {0, 60}, 625 {0, 60}, 626 {0, 60}, 627 {0, 60}}}, 628 629 {{{1, 60}, 630 {1, 60}, 631 {1, 60}, 632 {1, 60}, 633 {1, 60}, 634 {0, 60}, 635 {0, 60}, 636 {0, 60}}}, 637 638 {{{1, 60}, 639 {1, 60}, 640 {1, 60}, 641 {1, 60}, 642 {1, 60}, 643 {1, 60}, 644 {1, 60}, 645 {1, 60}}}, 646 647 {{{1, 60}, 648 {1, 60}, 649 {0, 60}, 650 {1, 60}, 651 {1, 60}, 652 {1, 60}, 653 {1, 60}, 654 {0, 60}}}, 655 656 {{{1, 60}, 657 {0, 60}, 658 {1, 60}, 659 {1, 60}, 660 {1, 60}, 661 {1, 60}, 662 {0, 60}, 663 {1, 60}}}, 664 } 665#else 666 { 667 {{{60, 1}, 668 {60, 1}, 669 {60, 1}, 670 {60, 1}, 671 {60, 1}, 672 {60, 1}, 673 {60, 1}, 674 {60, 0}}}, 675 676 {{{60, 1}, 677 {60, 1}, 678 {60, 1}, 679 {60, 1}, 680 {60, 1}, 681 {60, 1}, 682 {60, 1}, 683 {60, 0}}}, 684 685 {{{60, 0}, 686 {60, 1}, 687 {60, 0}, 688 {60, 1}, 689 {60, 1}, 690 {60, 1}, 691 {60, 1}, 692 {60, 1}}}, 693 694 {{{60, 0}, 695 {60, 1}, 696 {60, 1}, 697 {60, 0}, 698 {60, 1}, 699 {60, 0}, 700 {60, 0}, 701 {60, 0}}}, 702 703 {{{60, 1}, 704 {60, 1}, 705 {60, 1}, 706 {60, 0}, 707 {60, 0}, 708 {60, 0}, 709 {60, 0}, 710 {60, 0}}}, 711 712 {{{60, 1}, 713 {60, 1}, 714 {60, 1}, 715 {60, 1}, 716 {60, 1}, 717 {60, 0}, 718 {60, 0}, 719 {60, 0}}}, 720 721 {{{60, 1}, 722 {60, 1}, 723 {60, 1}, 724 {60, 1}, 725 {60, 1}, 726 {60, 1}, 727 {60, 1}, 728 {60, 1}}}, 729 730 {{{60, 1}, 731 {60, 1}, 732 {60, 0}, 733 {60, 1}, 734 {60, 1}, 735 {60, 1}, 736 {60, 1}, 737 {60, 0}}}, 738 739 {{{60, 1}, 740 {60, 0}, 741 {60, 1}, 742 {60, 1}, 743 {60, 1}, 744 {60, 1}, 745 {60, 0}, 746 {60, 1}}}, 747 } 748#endif 749}; 750 751#endif 752