1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16/* 17 * Copyright (c) 2002-2005 Atheros Communications, Inc. 18 * All Rights Reserved. 19 * 20 * Copyright (c) 2011 Qualcomm Atheros, Inc. 21 * All Rights Reserved. 22 * Qualcomm Atheros Confidential and Proprietary. 23 * 24 */ 25 26#ifndef _ATH_AR9300PHY_H_ 27#define _ATH_AR9300PHY_H_ 28 29#include "osprey_reg_map.h" 30 31/* 32 * BB PHY register map 33 */ 34#define AR_PHY_BASE offsetof(struct bb_reg_map, bb_chn_reg_map) /* base address of phy regs */ 35#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 36 37/* 38 * Channel Register Map 39 */ 40#define AR_CHAN_BASE offsetof(struct bb_reg_map, bb_chn_reg_map) 41#define AR_CHAN_OFFSET(_x) (AR_CHAN_BASE + offsetof(struct chn_reg_map, _x)) 42 43#define AR_PHY_TIMING1 AR_CHAN_OFFSET(BB_timing_controls_1) 44#define AR_PHY_TIMING2 AR_CHAN_OFFSET(BB_timing_controls_2) 45#define AR_PHY_TIMING3 AR_CHAN_OFFSET(BB_timing_controls_3) 46#define AR_PHY_TIMING4 AR_CHAN_OFFSET(BB_timing_control_4) 47#define AR_PHY_TIMING5 AR_CHAN_OFFSET(BB_timing_control_5) 48#define AR_PHY_TIMING6 AR_CHAN_OFFSET(BB_timing_control_6) 49#define AR_PHY_TIMING11 AR_CHAN_OFFSET(BB_timing_control_11) 50#define AR_PHY_SPUR_REG AR_CHAN_OFFSET(BB_spur_mask_controls) 51#define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_OFFSET(BB_rx_iq_corr_b0) 52#define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_OFFSET(BB_txiqcal_control_3) 53 54/* BB_timing_control_11 */ 55#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 56#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 57 58#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF 59#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 60 61#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000 62#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30 63 64#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000 65#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31 66 67/* BB_spur_mask_controls */ 68#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000 69#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26 70 71#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ 72#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17 73#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF 74#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 75#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100 76#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8 77#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000 78#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 79 80/* BB_rx_iq_corr_b0 */ 81#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000 82#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29 83/* BB_txiqcal_control_3 */ 84#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000 85#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31 86 87#if 0 88/* enable vit puncture per rate, 8 bits, lsb is low rate */ 89#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 90#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 91#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ 92#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */ 93#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 94#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 95#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 96#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 97#endif 98 99#define AR_PHY_FIND_SIG_LOW AR_CHAN_OFFSET(BB_find_signal_low) 100#define AR_PHY_SFCORR AR_CHAN_OFFSET(BB_sfcorr) 101#if 0 102#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 103#define AR_PHY_SFCORR_M2COUNT_THR_S 0 104#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 105#define AR_PHY_SFCORR_M1_THRESH_S 17 106#define AR_PHY_SFCORR_M2_THRESH 0x7F000000 107#define AR_PHY_SFCORR_M2_THRESH_S 24 108#endif 109 110#define AR_PHY_SFCORR_LOW AR_CHAN_OFFSET(BB_self_corr_low) 111#define AR_PHY_SFCORR_EXT AR_CHAN_OFFSET(BB_ext_chan_scorr_thr) 112#if 0 113#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00] 114#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 115#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07] 116#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 117#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14] 118#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 119#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21] 120#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 121#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 122#endif 123 124#define AR_PHY_EXT_CCA AR_CHAN_OFFSET(BB_ext_chan_pwr_thr_2_b0) 125#define AR_PHY_RADAR_0 AR_CHAN_OFFSET(BB_radar_detection) /* radar detection settings */ 126#define AR_PHY_RADAR_1 AR_CHAN_OFFSET(BB_radar_detection_2) 127#define AR_PHY_RADAR_1_CF_BIN_THRESH 0x07000000 128#define AR_PHY_RADAR_1_CF_BIN_THRESH_S 24 129#define AR_PHY_RADAR_EXT AR_CHAN_OFFSET(BB_extension_radar) /* extension channel radar settings */ 130#define AR_PHY_MULTICHAIN_CTRL AR_CHAN_OFFSET(BB_multichain_control) 131#define AR_PHY_PERCHAIN_CSD AR_CHAN_OFFSET(BB_per_chain_csd) 132 133#define AR_PHY_TX_PHASE_RAMP_0 AR_CHAN_OFFSET(BB_tx_phase_ramp_b0) 134#define AR_PHY_ADC_GAIN_DC_CORR_0 AR_CHAN_OFFSET(BB_adc_gain_dc_corr_b0) 135#define AR_PHY_IQ_ADC_MEAS_0_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_0_b0) 136#define AR_PHY_IQ_ADC_MEAS_1_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_1_b0) 137#define AR_PHY_IQ_ADC_MEAS_2_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_2_b0) 138#define AR_PHY_IQ_ADC_MEAS_3_B0 AR_CHAN_OFFSET(BB_iq_adc_meas_3_b0) 139 140#define AR_PHY_TX_IQ_CORR_0 AR_CHAN_OFFSET(BB_tx_iq_corr_b0) 141#define AR_PHY_TX_CRC AR_CHAN_OFFSET(BB_tx_crc) 142#define AR_PHY_TST_DAC_CONST AR_CHAN_OFFSET(BB_tstdac_constant) 143#define AR_PHY_SPUR_REPORT_0 AR_CHAN_OFFSET(BB_spur_report_b0) 144#define AR_PHY_CHAN_INFO_TAB_0 AR_CHAN_OFFSET(BB_chan_info_chan_tab_b0) 145 146 147/* 148 * Channel Field Definitions 149 */ 150/* BB_timing_controls_2 */ 151#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000 152#define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff 153#define AR_PHY_TIMING2_HT_Fine_Timing_EN 0x80000000 154#define AR_PHY_TIMING2_DC_OFFSET 0x08000000 155#define AR_PHY_TIMING2_DC_OFFSET_S 27 156 157/* BB_timing_controls_3 */ 158#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 159#define AR_PHY_TIMING3_DSC_MAN_S 17 160#define AR_PHY_TIMING3_DSC_EXP 0x0001E000 161#define AR_PHY_TIMING3_DSC_EXP_S 13 162/* BB_timing_control_4 */ 163#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ 164#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ 165#define AR_PHY_TIMING4_DO_CAL 0x10000 /* perform calibration */ 166#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000 167#define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28 168#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000 169#define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29 170 171#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000 172#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30 173#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000 174#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31 175 176/* BB_adc_gain_dc_corr_b0 */ 177#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 178#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 179/* BB_self_corr_low */ 180#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 181#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 182#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 183#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 184#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 185#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 186#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 187/* BB_sfcorr */ 188#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 189#define AR_PHY_SFCORR_M2COUNT_THR_S 0 190#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 191#define AR_PHY_SFCORR_M1_THRESH_S 17 192#define AR_PHY_SFCORR_M2_THRESH 0x7F000000 193#define AR_PHY_SFCORR_M2_THRESH_S 24 194/* BB_ext_chan_scorr_thr */ 195#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00] 196#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 197#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07] 198#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 199#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14] 200#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 201#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21] 202#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 203#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000 204#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28 205#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 206/* BB_ext_chan_pwr_thr_2_b0 */ 207#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 208#define AR_PHY_EXT_CCA_THRESH62_S 16 209#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000 210#define AR_PHY_EXT_MINCCA_PWR_S 16 211#define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L // [15:09] 212#define AR_PHY_EXT_CYCPWR_THR1_S 9 213/* BB_timing_control_5 */ 214#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE 215#define AR_PHY_TIMING5_CYCPWR_THR1_S 1 216#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001 217#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0 218#define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000 219#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16 220#define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16) 221#define AR_PHY_TIMING5_RSSI_THR1A_S 16 222#define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15) 223/* BB_radar_detection) */ 224#define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */ 225#define AR_PHY_RADAR_0_ENA_S 0 226#define AR_PHY_RADAR_0_FFT_ENA 0x80000000 /* Enable FFT data */ 227#define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */ 228#define AR_PHY_RADAR_0_INBAND_S 1 229#define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */ 230#define AR_PHY_RADAR_0_PRSSI_S 6 231#define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */ 232#define AR_PHY_RADAR_0_HEIGHT_S 12 233#define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */ 234#define AR_PHY_RADAR_0_RRSSI_S 18 235#define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */ 236#define AR_PHY_RADAR_0_FIRPWR_S 24 237/* BB_radar_detection_2 */ 238#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 /* enable to check radar relative power */ 239#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 /* enable to use the average inband power 240 * measured over 128 cycles 241 */ 242#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 /* relative pwr thresh */ 243#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 244#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 /* Enable to block radar check if weak OFDM 245 * sig or pkt is immediately after tx to rx 246 * transition 247 */ 248#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 /* Enable to use max rssi */ 249#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 /* Enable to use pulse relative step check */ 250#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 /* Pulse relative step threshold */ 251#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 252#define AR_PHY_RADAR_1_MAXLEN 0x000000FF /* Max length of radar pulse */ 253#define AR_PHY_RADAR_1_MAXLEN_S 0 254/* BB_extension_radar */ 255#define AR_PHY_RADAR_EXT_ENA 0x00004000 /* Enable extension channel radar detection */ 256#define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000 257#define AR_PHY_RADAR_DC_PWR_THRESH_S 15 258#define AR_PHY_RADAR_LB_DC_CAP 0x7f800000 259#define AR_PHY_RADAR_LB_DC_CAP_S 23 260/* per chain csd*/ 261#define AR_PHY_PERCHAIN_CSD_chn1_2chains 0x0000001f 262#define AR_PHY_PERCHAIN_CSD_chn1_2chains_S 0 263#define AR_PHY_PERCHAIN_CSD_chn1_3chains 0x000003e0 264#define AR_PHY_PERCHAIN_CSD_chn1_3chains_S 5 265#define AR_PHY_PERCHAIN_CSD_chn2_3chains 0x00007c00 266#define AR_PHY_PERCHAIN_CSD_chn2_3chains_S 10 267/* BB_find_signal_low */ 268#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6) 269#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6 270#define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12) 271#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12 272#define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19 273#define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f 274#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0 275#define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5 276/* BB_chan_info_chan_tab_b* */ 277#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008 278#define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3 279/* BB_rx_iq_corr_b* */ 280#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F /* Mask for kcos_theta-1 for q correction */ 281#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ 282#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80 /* Mask for sin_theta for i correction */ 283#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7 /* Shift for sin_theta for i correction */ 284#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000 /* enable IQ correction */ 285#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000 286#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15 287#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000 288#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22 289 290/* 291 * MRC Register Map 292 */ 293#define AR_MRC_BASE offsetof(struct bb_reg_map, bb_mrc_reg_map) 294#define AR_MRC_OFFSET(_x) (AR_MRC_BASE + offsetof(struct mrc_reg_map, _x)) 295 296#define AR_PHY_TIMING_3A AR_MRC_OFFSET(BB_timing_control_3a) 297#define AR_PHY_LDPC_CNTL1 AR_MRC_OFFSET(BB_ldpc_cntl1) 298#define AR_PHY_LDPC_CNTL2 AR_MRC_OFFSET(BB_ldpc_cntl2) 299#define AR_PHY_PILOT_SPUR_MASK AR_MRC_OFFSET(BB_pilot_spur_mask) 300#define AR_PHY_CHAN_SPUR_MASK AR_MRC_OFFSET(BB_chan_spur_mask) 301#define AR_PHY_SGI_DELTA AR_MRC_OFFSET(BB_short_gi_delta_slope) 302#define AR_PHY_ML_CNTL_1 AR_MRC_OFFSET(BB_ml_cntl1) 303#define AR_PHY_ML_CNTL_2 AR_MRC_OFFSET(BB_ml_cntl2) 304#define AR_PHY_TST_ADC AR_MRC_OFFSET(BB_tstadc) 305 306/* BB_pilot_spur_mask fields */ 307#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0 308#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5 309#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F 310#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0 311 312/* BB_chan_spur_mask fields */ 313#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0 314#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5 315#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F 316#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0 317 318/* 319 * MRC Feild Definitions 320 */ 321#define AR_PHY_SGI_DSC_MAN 0x0007FFF0 322#define AR_PHY_SGI_DSC_MAN_S 4 323#define AR_PHY_SGI_DSC_EXP 0x0000000F 324#define AR_PHY_SGI_DSC_EXP_S 0 325/* 326 * BBB Register Map 327 */ 328#define AR_BBB_BASE offsetof(struct bb_reg_map, bb_bbb_reg_map) 329#define AR_BBB_OFFSET(_x) (AR_BBB_BASE + offsetof(struct bbb_reg_map, _x)) 330 331#define AR_PHY_BBB_RX_CTRL(_i) AR_BBB_OFFSET(BB_bbb_rx_ctrl_##_i) 332 333/* 334 * AGC Register Map 335 */ 336#define AR_AGC_BASE offsetof(struct bb_reg_map, bb_agc_reg_map) 337#define AR_AGC_OFFSET(_x) (AR_AGC_BASE + offsetof(struct agc_reg_map, _x)) 338 339#define AR_PHY_SETTLING AR_AGC_OFFSET(BB_settling_time) 340#define AR_PHY_FORCEMAX_GAINS_0 AR_AGC_OFFSET(BB_gain_force_max_gains_b0) 341#define AR_PHY_GAINS_MINOFF0 AR_AGC_OFFSET(BB_gains_min_offsets_b0) 342#define AR_PHY_DESIRED_SZ AR_AGC_OFFSET(BB_desired_sigsize) 343#define AR_PHY_FIND_SIG AR_AGC_OFFSET(BB_find_signal) 344#define AR_PHY_AGC AR_AGC_OFFSET(BB_agc) 345#define AR_PHY_EXT_ATTEN_CTL_0 AR_AGC_OFFSET(BB_ext_atten_switch_ctl_b0) 346#define AR_PHY_CCA_0 AR_AGC_OFFSET(BB_cca_b0) 347#define AR_PHY_EXT_CCA0 AR_AGC_OFFSET(BB_cca_ctrl_2_b0) 348#define AR_PHY_RESTART AR_AGC_OFFSET(BB_restart) 349#define AR_PHY_MC_GAIN_CTRL AR_AGC_OFFSET(BB_multichain_gain_ctrl) 350#define AR_PHY_EXTCHN_PWRTHR1 AR_AGC_OFFSET(BB_ext_chan_pwr_thr_1) 351#define AR_PHY_EXT_CHN_WIN AR_AGC_OFFSET(BB_ext_chan_detect_win) 352#define AR_PHY_20_40_DET_THR AR_AGC_OFFSET(BB_pwr_thr_20_40_det) 353#define AR_PHY_RIFS_SRCH AR_AGC_OFFSET(BB_rifs_srch) 354#define AR_PHY_PEAK_DET_CTRL_1 AR_AGC_OFFSET(BB_peak_det_ctrl_1) 355 356#define AR_PHY_PEAK_DET_ENABLE 0x00000002 357 358#define AR_PHY_PEAK_DET_CTRL_2 AR_AGC_OFFSET(BB_peak_det_ctrl_2) 359#define AR_PHY_RX_GAIN_BOUNDS_1 AR_AGC_OFFSET(BB_rx_gain_bounds_1) 360#define AR_PHY_RX_GAIN_BOUNDS_2 AR_AGC_OFFSET(BB_rx_gain_bounds_2) 361#define AR_PHY_RSSI_0 AR_AGC_OFFSET(BB_rssi_b0) 362#define AR_PHY_SPUR_CCK_REP0 AR_AGC_OFFSET(BB_spur_est_cck_report_b0) 363#define AR_PHY_CCK_DETECT AR_AGC_OFFSET(BB_bbb_sig_detect) 364#define AR_PHY_DAG_CTRLCCK AR_AGC_OFFSET(BB_bbb_dagc_ctrl) 365#define AR_PHY_IQCORR_CTRL_CCK AR_AGC_OFFSET(BB_iqcorr_ctrl_cck) 366#define AR_PHY_DIG_DC_STATUS_I_B0 AR_AGC_OFFSET(BB_agc_dig_dc_status_i_b0) 367#define AR_PHY_DIG_DC_STATUS_Q_B0 AR_AGC_OFFSET(BB_agc_dig_dc_status_q_b0) 368#define AR_PHY_DIG_DC_C1_RES 0x000001ff 369#define AR_PHY_DIG_DC_C1_RES_S 0 370#define AR_PHY_DIG_DC_C2_RES 0x0003fe00 371#define AR_PHY_DIG_DC_C2_RES_S 9 372#define AR_PHY_DIG_DC_C3_RES 0x07fc0000 373#define AR_PHY_DIG_DC_C3_RES_S 18 374 375#define AR_PHY_CCK_SPUR_MIT AR_AGC_OFFSET(BB_cck_spur_mit) 376#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe 377#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1 378#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000 379#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29 380#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001 381#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0 382#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00 383#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9 384 385#define AR_PHY_MRC_CCK_CTRL AR_AGC_OFFSET(BB_mrc_cck_ctrl) 386#define AR_PHY_MRC_CCK_ENABLE 0x00000001 387#define AR_PHY_MRC_CCK_ENABLE_S 0 388#define AR_PHY_MRC_CCK_MUX_REG 0x00000002 389#define AR_PHY_MRC_CCK_MUX_REG_S 1 390 391#define AR_PHY_RX_OCGAIN AR_AGC_OFFSET(BB_rx_ocgain) 392 393#define AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ -110 394#define AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ -115 395#define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ -125 396#define AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ -125 397#define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ -95 398#define AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ -100 399#define AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ -105 400 401#define AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ -127 402#define AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ -127 403#define AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ -127 404#define AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ -127 405 406#define AR_PHY_BT_COEX_4 AR_AGC_OFFSET(BB_bt_coex_4) 407#define AR_PHY_BT_COEX_5 AR_AGC_OFFSET(BB_bt_coex_5) 408 409/* 410 * Noise floor readings at least CW_INT_DELTA above the nominal NF 411 * indicate that CW interference is present. 412 */ 413#define AR_PHY_CCA_CW_INT_DELTA 30 414 415/* 416 * AGC Field Definitions 417 */ 418/* BB_ext_atten_switch_ctl_b0 */ 419#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000 420#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18 421#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00 422#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10 423#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F 424#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0 425#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000 426#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17 427#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000 428#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12 429#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0 430#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6 431#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F 432#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0 433/* BB_gain_force_max_gains_b0 */ 434#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 435#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 436#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 437#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 438#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 439#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 440#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 441#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 442/* BB_settling_time */ 443#define AR_PHY_SETTLING_SWITCH 0x00003F80 444#define AR_PHY_SETTLING_SWITCH_S 7 445/* BB_desired_sigsize */ 446#define AR_PHY_DESIRED_SZ_ADC 0x000000FF 447#define AR_PHY_DESIRED_SZ_ADC_S 0 448#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 449#define AR_PHY_DESIRED_SZ_PGA_S 8 450#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 451#define AR_PHY_DESIRED_SZ_TOT_DES_S 20 452/* BB_cca_b0 */ 453#define AR_PHY_MINCCA_PWR 0x1FF00000 454#define AR_PHY_MINCCA_PWR_S 20 455#define AR_PHY_CCA_THRESH62 0x0007F000 456#define AR_PHY_CCA_THRESH62_S 12 457#define AR9280_PHY_MINCCA_PWR 0x1FF00000 458#define AR9280_PHY_MINCCA_PWR_S 20 459#define AR9280_PHY_CCA_THRESH62 0x000FF000 460#define AR9280_PHY_CCA_THRESH62_S 12 461/* BB_cca_ctrl_2_b0 */ 462#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 463#define AR_PHY_EXT_CCA0_THRESH62_S 0 464/* BB_bbb_sig_detect */ 465#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F 466#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 467#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 // [12:6] settling time for antenna switch 468#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 469#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 470#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 471 472/* BB_bbb_dagc_ctrl */ 473#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 474#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9 475#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 476#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 477 478/* BB_rifs_srch */ 479#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000 480 481/*B_tpc_7*/ 482#define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX 0x3f 483#define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX_S (0) 484 485/* BB_agc */ 486#define AR_PHY_AGC_QUICK_DROP_S (22) 487#define AR_PHY_AGC_QUICK_DROP (0xf << AR_PHY_AGC_QUICK_DROP_S) 488#define AR_PHY_AGC_COARSE_LOW 0x00007F80 489#define AR_PHY_AGC_COARSE_LOW_S 7 490#define AR_PHY_AGC_COARSE_HIGH 0x003F8000 491#define AR_PHY_AGC_COARSE_HIGH_S 15 492#define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F 493#define AR_PHY_AGC_COARSE_PWR_CONST_S 0 494/* BB_find_signal */ 495#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 496#define AR_PHY_FIND_SIG_FIRSTEP_S 12 497#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 498#define AR_PHY_FIND_SIG_FIRPWR_S 18 499#define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25 500#define AR_PHY_FIND_SIG_RELPWR (0x1f << 6) 501#define AR_PHY_FIND_SIG_RELPWR_S 6 502#define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11 503#define AR_PHY_FIND_SIG_RELSTEP 0x1f 504#define AR_PHY_FIND_SIG_RELSTEP_S 0 505#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5 506/* BB_restart */ 507#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ 508#define AR_PHY_RESTART_DIV_GC_S 18 509#define AR_PHY_RESTART_ENA 0x01 /* enable restart */ 510#define AR_PHY_DC_RESTART_DIS 0x40000000 /* disable DC restart */ 511 512#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000 //Mask BIT[31:24] 513#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24 514#define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000 //Mask BIT[23:16] 515#define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16 516 517#define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000 //Mask BIT[25:24] 518#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24 519 520/* 521 * SM Register Map 522 */ 523#define AR_SM_BASE offsetof(struct bb_reg_map, bb_sm_reg_map) 524#define AR_SM_OFFSET(_x) (AR_SM_BASE + offsetof(struct sm_reg_map, _x)) 525 526#define AR_PHY_D2_CHIP_ID AR_SM_OFFSET(BB_D2_chip_id) 527#define AR_PHY_GEN_CTRL AR_SM_OFFSET(BB_gen_controls) 528#define AR_PHY_MODE AR_SM_OFFSET(BB_modes_select) 529#define AR_PHY_ACTIVE AR_SM_OFFSET(BB_active) 530#define AR_PHY_SPUR_MASK_A AR_SM_OFFSET(BB_vit_spur_mask_A) 531#define AR_PHY_SPUR_MASK_B AR_SM_OFFSET(BB_vit_spur_mask_B) 532#define AR_PHY_SPECTRAL_SCAN AR_SM_OFFSET(BB_spectral_scan) 533#define AR_PHY_RADAR_BW_FILTER AR_SM_OFFSET(BB_radar_bw_filter) 534#define AR_PHY_SEARCH_START_DELAY AR_SM_OFFSET(BB_search_start_delay) 535#define AR_PHY_MAX_RX_LEN AR_SM_OFFSET(BB_max_rx_length) 536#define AR_PHY_FRAME_CTL AR_SM_OFFSET(BB_frame_control) 537#define AR_PHY_RFBUS_REQ AR_SM_OFFSET(BB_rfbus_request) 538#define AR_PHY_RFBUS_GRANT AR_SM_OFFSET(BB_rfbus_grant) 539#define AR_PHY_RIFS AR_SM_OFFSET(BB_rifs) 540#define AR_PHY_RX_CLR_DELAY AR_SM_OFFSET(BB_rx_clear_delay) 541#define AR_PHY_RX_DELAY AR_SM_OFFSET(BB_analog_power_on_time) 542#define AR_PHY_BB_POWERTX_RATE9 AR_SM_OFFSET(BB_powertx_rate9) 543#define AR_PHY_TPC_7 AR_SM_OFFSET(BB_tpc_7) 544#define AR_PHY_CL_MAP_0_B0 AR_SM_OFFSET(BB_cl_map_0_b0) 545#define AR_PHY_CL_MAP_1_B0 AR_SM_OFFSET(BB_cl_map_1_b0) 546#define AR_PHY_CL_MAP_2_B0 AR_SM_OFFSET(BB_cl_map_2_b0) 547#define AR_PHY_CL_MAP_3_B0 AR_SM_OFFSET(BB_cl_map_3_b0) 548 549#define AR_PHY_RF_CTL(_i) AR_SM_OFFSET(BB_tx_timing_##_i) 550 551#define AR_PHY_XPA_TIMING_CTL AR_SM_OFFSET(BB_xpa_timing_control) 552#define AR_PHY_MISC_PA_CTL AR_SM_OFFSET(BB_misc_pa_control) 553#define AR_PHY_SWITCH_CHAIN_0 AR_SM_OFFSET(BB_switch_table_chn_b0) 554#define AR_PHY_SWITCH_COM AR_SM_OFFSET(BB_switch_table_com1) 555#define AR_PHY_SWITCH_COM_2 AR_SM_OFFSET(BB_switch_table_com2) 556#define AR_PHY_RX_CHAINMASK AR_SM_OFFSET(BB_multichain_enable) 557#define AR_PHY_CAL_CHAINMASK AR_SM_OFFSET(BB_cal_chain_mask) 558#define AR_PHY_AGC_CONTROL AR_SM_OFFSET(BB_agc_control) 559#define AR_PHY_CALMODE AR_SM_OFFSET(BB_iq_adc_cal_mode) 560#define AR_PHY_FCAL_1 AR_SM_OFFSET(BB_fcal_1) 561#define AR_PHY_FCAL_2_0 AR_SM_OFFSET(BB_fcal_2_b0) 562#define AR_PHY_DFT_TONE_CTL_0 AR_SM_OFFSET(BB_dft_tone_ctrl_b0) 563#define AR_PHY_CL_CAL_CTL AR_SM_OFFSET(BB_cl_cal_ctrl) 564#define AR_PHY_BBGAINMAP_0_1_0 AR_SM_OFFSET(BB_cl_bbgain_map_0_1_b0) 565#define AR_PHY_BBGAINMAP_2_3_0 AR_SM_OFFSET(BB_cl_bbgain_map_2_3_b0) 566#define AR_PHY_CL_TAB_0 AR_SM_OFFSET(BB_cl_tab_b0) 567#define AR_PHY_SYNTH_CONTROL AR_SM_OFFSET(BB_synth_control) 568#define AR_PHY_ADDAC_CLK_SEL AR_SM_OFFSET(BB_addac_clk_select) 569#define AR_PHY_PLL_CTL AR_SM_OFFSET(BB_pll_cntl) 570#define AR_PHY_ANALOG_SWAP AR_SM_OFFSET(BB_analog_swap) 571#define AR_PHY_ADDAC_PARA_CTL AR_SM_OFFSET(BB_addac_parallel_control) 572#define AR_PHY_XPA_CFG AR_SM_OFFSET(BB_force_analog) 573#define AR_PHY_AIC_CTRL_0_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_0_b0) 574#define AR_PHY_AIC_CTRL_1_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_1_b0) 575#define AR_PHY_AIC_CTRL_2_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_2_b0) 576#define AR_PHY_AIC_CTRL_3_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_ctrl_3_b0) 577#define AR_PHY_AIC_STAT_0_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_stat_0_b0) 578#define AR_PHY_AIC_STAT_1_B0_10 AR_SM_OFFSET(overlay_0xa580.Jupiter_10.BB_aic_stat_1_b0) 579#define AR_PHY_AIC_CTRL_0_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_0_b0) 580#define AR_PHY_AIC_CTRL_1_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_1_b0) 581#define AR_PHY_AIC_CTRL_2_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_2_b0) 582#define AR_PHY_AIC_CTRL_3_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_3_b0) 583#define AR_PHY_AIC_CTRL_4_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_ctrl_4_b0) 584#define AR_PHY_AIC_STAT_0_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_0_b0) 585#define AR_PHY_AIC_STAT_1_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_1_b0) 586#define AR_PHY_AIC_STAT_2_B0_20 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_aic_stat_2_b0) 587#define AR_PHY_AIC_CTRL_0_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_ctrl_0_b1) 588#define AR_PHY_AIC_CTRL_1_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_ctrl_1_b1) 589#define AR_PHY_AIC_STAT_0_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_stat_0_b1) 590#define AR_PHY_AIC_STAT_1_B1_10 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_aic_stat_1_b1) 591#define AR_PHY_AIC_CTRL_0_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_0_b1) 592#define AR_PHY_AIC_CTRL_1_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_1_b1) 593#define AR_PHY_AIC_CTRL_4_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_ctrl_4_b1) 594#define AR_PHY_AIC_STAT_0_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_0_b1) 595#define AR_PHY_AIC_STAT_1_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_1_b1) 596#define AR_PHY_AIC_STAT_2_B1_20 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_20.BB_aic_stat_2_b1) 597#define AR_PHY_AIC_SRAM_ADDR_B0 AR_SM_OFFSET(BB_tables_intf_addr_b0) 598#define AR_PHY_AIC_SRAM_DATA_B0 AR_SM_OFFSET(BB_tables_intf_data_b0) 599#define AR_PHY_AIC_SRAM_ADDR_B1 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_tables_intf_addr_b1) 600#define AR_PHY_AIC_SRAM_DATA_B1 AR_SM1_OFFSET(overlay_0x4b0.Jupiter_10.BB_tables_intf_data_b1) 601 602 603/* AIC fields */ 604#define AR_PHY_AIC_MON_ENABLE 0x80000000 605#define AR_PHY_AIC_MON_ENABLE_S 31 606#define AR_PHY_AIC_CAL_MAX_HOP_COUNT 0x7F000000 607#define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S 24 608#define AR_PHY_AIC_CAL_MIN_VALID_COUNT 0x00FE0000 609#define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S 17 610#define AR_PHY_AIC_F_WLAN 0x0001FC00 611#define AR_PHY_AIC_F_WLAN_S 10 612#define AR_PHY_AIC_CAL_CH_VALID_RESET 0x00000200 613#define AR_PHY_AIC_CAL_CH_VALID_RESET_S 9 614#define AR_PHY_AIC_CAL_ENABLE 0x00000100 615#define AR_PHY_AIC_CAL_ENABLE_S 8 616#define AR_PHY_AIC_BTTX_PWR_THR 0x000000FE 617#define AR_PHY_AIC_BTTX_PWR_THR_S 1 618#define AR_PHY_AIC_ENABLE 0x00000001 619#define AR_PHY_AIC_ENABLE_S 0 620#define AR_PHY_AIC_CAL_BT_REF_DELAY 0x78000000 621#define AR_PHY_AIC_CAL_BT_REF_DELAY_S 27 622#define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO 0x07000000 623#define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S 24 624#define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO 0x00F00000 625#define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S 20 626#define AR_PHY_AIC_BT_IDLE_CFG 0x00080000 627#define AR_PHY_AIC_BT_IDLE_CFG_S 19 628#define AR_PHY_AIC_STDBY_COND 0x00060000 629#define AR_PHY_AIC_STDBY_COND_S 17 630#define AR_PHY_AIC_STDBY_ROT_ATT_DB 0x0001F800 631#define AR_PHY_AIC_STDBY_ROT_ATT_DB_S 11 632#define AR_PHY_AIC_STDBY_COM_ATT_DB 0x00000700 633#define AR_PHY_AIC_STDBY_COM_ATT_DB_S 8 634#define AR_PHY_AIC_RSSI_MAX 0x000000F0 635#define AR_PHY_AIC_RSSI_MAX_S 4 636#define AR_PHY_AIC_RSSI_MIN 0x0000000F 637#define AR_PHY_AIC_RSSI_MIN_S 0 638#define AR_PHY_AIC_RADIO_DELAY 0x7F000000 639#define AR_PHY_AIC_RADIO_DELAY_S 24 640#define AR_PHY_AIC_CAL_STEP_SIZE_CORR 0x00F00000 641#define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S 20 642#define AR_PHY_AIC_CAL_ROT_IDX_CORR 0x000F8000 643#define AR_PHY_AIC_CAL_ROT_IDX_CORR_S 15 644#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR 0x00006000 645#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S 13 646#define AR_PHY_AIC_ROT_IDX_COUNT_MAX 0x00001C00 647#define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S 10 648#define AR_PHY_AIC_CAL_SYNTH_TOGGLE 0x00000200 649#define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S 9 650#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX 0x00000100 651#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S 8 652#define AR_PHY_AIC_CAL_SYNTH_SETTLING 0x000000FF 653#define AR_PHY_AIC_CAL_SYNTH_SETTLING_S 0 654#define AR_PHY_AIC_MON_MAX_HOP_COUNT 0x0FE00000 655#define AR_PHY_AIC_MON_MAX_HOP_COUNT_S 21 656#define AR_PHY_AIC_MON_MIN_STALE_COUNT 0x001FC000 657#define AR_PHY_AIC_MON_MIN_STALE_COUNT_S 14 658#define AR_PHY_AIC_MON_PWR_EST_LONG 0x00002000 659#define AR_PHY_AIC_MON_PWR_EST_LONG_S 13 660#define AR_PHY_AIC_MON_PD_TALLY_SCALING 0x00001800 661#define AR_PHY_AIC_MON_PD_TALLY_SCALING_S 11 662#define AR_PHY_AIC_MON_PERF_THR 0x000007C0 663#define AR_PHY_AIC_MON_PERF_THR_S 6 664#define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED 0x00000020 665#define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S 5 666#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING 0x00000018 667#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S 3 668#define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR 0x00000006 669#define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S 1 670#define AR_PHY_AIC_CAL_PWR_EST_LONG 0x00000001 671#define AR_PHY_AIC_CAL_PWR_EST_LONG_S 0 672#define AR_PHY_AIC_MON_DONE 0x80000000 673#define AR_PHY_AIC_MON_DONE_S 31 674#define AR_PHY_AIC_MON_ACTIVE 0x40000000 675#define AR_PHY_AIC_MON_ACTIVE_S 30 676#define AR_PHY_AIC_MEAS_COUNT 0x3F000000 677#define AR_PHY_AIC_MEAS_COUNT_S 24 678#define AR_PHY_AIC_CAL_ANT_ISO_EST 0x00FC0000 679#define AR_PHY_AIC_CAL_ANT_ISO_EST_S 18 680#define AR_PHY_AIC_CAL_HOP_COUNT 0x0003F800 681#define AR_PHY_AIC_CAL_HOP_COUNT_S 11 682#define AR_PHY_AIC_CAL_VALID_COUNT 0x000007F0 683#define AR_PHY_AIC_CAL_VALID_COUNT_S 4 684#define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR 0x00000008 685#define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S 3 686#define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR 0x00000004 687#define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S 2 688#define AR_PHY_AIC_CAL_DONE 0x00000002 689#define AR_PHY_AIC_CAL_DONE_S 1 690#define AR_PHY_AIC_CAL_ACTIVE 0x00000001 691#define AR_PHY_AIC_CAL_ACTIVE_S 0 692#define AR_PHY_AIC_MEAS_MAG_MIN 0xFFC00000 693#define AR_PHY_AIC_MEAS_MAG_MIN_S 22 694#define AR_PHY_AIC_MON_STALE_COUNT 0x003F8000 695#define AR_PHY_AIC_MON_STALE_COUNT_S 15 696#define AR_PHY_AIC_MON_HOP_COUNT 0x00007F00 697#define AR_PHY_AIC_MON_HOP_COUNT_S 8 698#define AR_PHY_AIC_CAL_AIC_SM 0x000000F8 699#define AR_PHY_AIC_CAL_AIC_SM_S 3 700#define AR_PHY_AIC_SM 0x00000007 701#define AR_PHY_AIC_SM_S 0 702#define AR_PHY_AIC_SRAM_VALID 0x00000001 703#define AR_PHY_AIC_SRAM_VALID_S 0 704#define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB 0x0000007E 705#define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S 1 706#define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN 0x00000080 707#define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S 7 708#define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB 0x00003F00 709#define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S 8 710#define AR_PHY_AIC_SRAM_VGA_DIR_SIGN 0x00004000 711#define AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S 14 712#define AR_PHY_AIC_SRAM_COM_ATT_6DB 0x00038000 713#define AR_PHY_AIC_SRAM_COM_ATT_6DB_S 15 714 715#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW 3 716#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0 717 718/* BB_cl_tab_bx */ 719#define AR_PHY_CL_TAB_CARR_LK_DC_ADD_I 0x07FF0000 720#define AR_PHY_CL_TAB_CARR_LK_DC_ADD_I_S 16 721#define AR_PHY_CL_TAB_CARR_LK_DC_ADD_Q 0x0000FFE0 722#define AR_PHY_CL_TAB_CARR_LK_DC_ADD_Q_S 5 723#define AR_PHY_CL_TAB_GAIN_MOD 0x0000001F 724#define AR_PHY_CL_TAB_GAIN_MOD_S 0 725 726/* BB_vit_spur_mask_A fields */ 727#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00 728#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10 729#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF 730#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 731 732/* enable_flt_svd*/ 733#define AR_PHY_ENABLE_FLT_SVD 0x00001000 734#define AR_PHY_ENABLE_FLT_SVD_S 12 735 736#define AR_PHY_TEST AR_SM_OFFSET(BB_test_controls) 737 738#define AR_PHY_TEST_BBB_OBS_SEL 0x780000 739#define AR_PHY_TEST_BBB_OBS_SEL_S 19 /* bits 19 to 22 are cf_bbb_obs_sel*/ 740 741#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23 742#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)// This is bit 5 for cf_rx_obs_sel 743 744#define AR_PHY_TEST_CHAIN_SEL 0xC0000000 745#define AR_PHY_TEST_CHAIN_SEL_S 30 /*bits 30 and 31 are tstdac_out_sel which selects which chain to drive out*/ 746 747#define AR_PHY_TEST_CTL_STATUS AR_SM_OFFSET(BB_test_controls_status) 748#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1 749#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 /*cf_tstdac_en, driver to tstdac bus, 0=disable, 1=enable*/ 750#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C 751#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2 /* cf_tx_obs_sel, bits 2:4*/ 752#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60 753#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5 /* cf_tx_obs_sel, bits 5:6, setting to 11 selects ADC*/ 754#define AR_PHY_TEST_CTL_TSTADC_EN 0x100 755#define AR_PHY_TEST_CTL_TSTADC_EN_S 8 /*cf_tstadc_en, driver to tstadc bus, 0=disable, 1=enable*/ 756#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00 757#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 /* cf_tx_obs_sel, bits 10:13*/ 758#define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000 759#define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29 760 761 762#define AR_PHY_TSTDAC AR_SM_OFFSET(BB_tstdac) 763 764#define AR_PHY_CHAN_STATUS AR_SM_OFFSET(BB_channel_status) 765#define AR_PHY_CHAN_INFO_MEMORY AR_SM_OFFSET(BB_chaninfo_ctrl) 766#define AR_PHY_CHNINFO_NOISEPWR AR_SM_OFFSET(BB_chan_info_noise_pwr) 767#define AR_PHY_CHNINFO_GAINDIFF AR_SM_OFFSET(BB_chan_info_gain_diff) 768#define AR_PHY_CHNINFO_FINETIM AR_SM_OFFSET(BB_chan_info_fine_timing) 769#define AR_PHY_CHAN_INFO_GAIN_0 AR_SM_OFFSET(BB_chan_info_gain_b0) 770#define AR_PHY_SCRAMBLER_SEED AR_SM_OFFSET(BB_scrambler_seed) 771#define AR_PHY_CCK_TX_CTRL AR_SM_OFFSET(BB_bbb_tx_ctrl) 772 773#define AR_PHY_TX_FIR(_i) AR_SM_OFFSET(BB_bbb_txfir_##_i) 774 775#define AR_PHY_HEAVYCLIP_CTL AR_SM_OFFSET(BB_heavy_clip_ctrl) 776#define AR_PHY_HEAVYCLIP_20 AR_SM_OFFSET(BB_heavy_clip_20) 777#define AR_PHY_HEAVYCLIP_40 AR_SM_OFFSET(BB_heavy_clip_40) 778#define AR_PHY_ILLEGAL_TXRATE AR_SM_OFFSET(BB_illegal_tx_rate) 779 780#define AR_PHY_POWER_TX_RATE(_i) AR_SM_OFFSET(BB_powertx_rate##_i) 781 782#define AR_PHY_PWRTX_MAX AR_SM_OFFSET(BB_powertx_max) /* TPC register */ 783#define AR_PHY_PWRTX_MAX_TPC_ENABLE 0x00000040 784#define AR_PHY_POWER_TX_SUB AR_SM_OFFSET(BB_powertx_sub) 785#define AR_PHY_PER_PACKET_POWERTX_MAX 0x00000040 786#define AR_PHY_PER_PACKET_POWERTX_MAX_S 6 787#define AR_PHY_POWER_TX_SUB_2_DISABLE 0xFFFFFFC0 /* 2 chain */ 788#define AR_PHY_POWER_TX_SUB_3_DISABLE 0xFFFFF000 /* 3 chain */ 789 790#define AR_PHY_TPC(_i) AR_SM_OFFSET(BB_tpc_##_i) /* values 1-3, 7-10 and 12-15 */ 791#define AR_PHY_TPC_4_B0 AR_SM_OFFSET(BB_tpc_4_b0) 792#define AR_PHY_TPC_5_B0 AR_SM_OFFSET(BB_tpc_5_b0) 793#define AR_PHY_TPC_6_B0 AR_SM_OFFSET(BB_tpc_6_b0) 794#define AR_PHY_TPC_18 AR_SM_OFFSET(BB_tpc_18) 795#define AR_PHY_TPC_19 AR_SM_OFFSET(BB_tpc_19) 796 797#define AR_PHY_TX_FORCED_GAIN AR_SM_OFFSET(BB_tx_forced_gain) 798 799#define AR_PHY_PDADC_TAB_0 AR_SM_OFFSET(BB_pdadc_tab_b0) 800 801#define AR_PHY_RTT_CTRL AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_ctrl) 802#define AR_PHY_RTT_TABLE_SW_INTF_B0 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_table_sw_intf_b0) 803#define AR_PHY_RTT_TABLE_SW_INTF_1_B0 AR_SM_OFFSET(overlay_0xa580.Jupiter_20.BB_rtt_table_sw_intf_1_b0) 804 805#define AR_PHY_TX_IQCAL_CONTROL_0(_ah) \ 806 (AR_SREV_POSEIDON(_ah) ? \ 807 AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_0) : \ 808 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_control_0)) 809 810#define AR_PHY_TX_IQCAL_CONTROL_1(_ah) \ 811 (AR_SREV_POSEIDON(_ah) ? \ 812 AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_1) : \ 813 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_control_1)) 814 815#define AR_PHY_TX_IQCAL_START(_ah) \ 816 (AR_SREV_POSEIDON(_ah) ? \ 817 AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_control_0) : \ 818 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_start)) 819 820#define AR_PHY_TX_IQCAL_STATUS_B0(_ah) \ 821 (AR_SREV_POSEIDON(_ah) ? \ 822 AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiqcal_status_b0) : \ 823 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiqcal_status_b0)) 824 825#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_01_b0) 826#define AR_PHY_TX_IQCAL_CORR_COEFF_23_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_23_b0) 827#define AR_PHY_TX_IQCAL_CORR_COEFF_45_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_45_b0) 828#define AR_PHY_TX_IQCAL_CORR_COEFF_67_B0 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_txiq_corr_coeff_67_b0) 829 830#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_01_b0) 831#define AR_PHY_TX_IQCAL_CORR_COEFF_23_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_23_b0) 832#define AR_PHY_TX_IQCAL_CORR_COEFF_45_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_45_b0) 833#define AR_PHY_TX_IQCAL_CORR_COEFF_67_B0_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_txiq_corr_coeff_67_b0) 834 835#define AR_PHY_TXGAIN_TAB(_i) AR_SM_OFFSET(BB_tx_gain_tab_##_i) /* values 1-22 */ 836#define AR_PHY_TXGAIN_TAB_PAL(_i) AR_SM_OFFSET(BB_tx_gain_tab_pal_##_i) /* values 1-22 */ 837#define AR_PHY_PANIC_WD_STATUS AR_SM_OFFSET(BB_panic_watchdog_status) 838#define AR_PHY_PANIC_WD_CTL_1 AR_SM_OFFSET(BB_panic_watchdog_ctrl_1) 839#define AR_PHY_PANIC_WD_CTL_2 AR_SM_OFFSET(BB_panic_watchdog_ctrl_2) 840#define AR_PHY_BT_CTL AR_SM_OFFSET(BB_bluetooth_cntl) 841#define AR_PHY_ONLY_WARMRESET AR_SM_OFFSET(BB_phyonly_warm_reset) 842#define AR_PHY_ONLY_CTL AR_SM_OFFSET(BB_phyonly_control) 843#define AR_PHY_ECO_CTRL AR_SM_OFFSET(BB_eco_ctrl) 844#define AR_PHY_BB_THERM_ADC_1 AR_SM_OFFSET(BB_therm_adc_1) 845#define AR_PHY_BB_THERM_ADC_4 AR_SM_OFFSET(BB_therm_adc_4) 846 847#define AR_PHY_65NM(_field) offsetof(struct radio65_reg, _field) 848#define AR_PHY_65NM_CH0_TXRF1 AR_PHY_65NM(ch0_TXRF1) 849#define AR_PHY_65NM_CH0_TXRF2 AR_PHY_65NM(ch0_TXRF2) 850#define AR_PHY_65NM_CH0_TXRF2_DB2G 0x07000000 851#define AR_PHY_65NM_CH0_TXRF2_DB2G_S 24 852#define AR_PHY_65NM_CH0_TXRF2_OB2G_CCK 0x00E00000 853#define AR_PHY_65NM_CH0_TXRF2_OB2G_CCK_S 21 854#define AR_PHY_65NM_CH0_TXRF2_OB2G_PSK 0x001C0000 855#define AR_PHY_65NM_CH0_TXRF2_OB2G_PSK_S 18 856#define AR_PHY_65NM_CH0_TXRF2_OB2G_QAM 0x00038000 857#define AR_PHY_65NM_CH0_TXRF2_OB2G_QAM_S 15 858#define AR_PHY_65NM_CH0_TXRF3 AR_PHY_65NM(ch0_TXRF3) 859#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001E 860#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1 861#define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE 0x00000001 862#define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE_S 0 863#define AR_PHY_65NM_CH1_TXRF1 AR_PHY_65NM(ch1_TXRF1) 864#define AR_PHY_65NM_CH1_TXRF2 AR_PHY_65NM(ch1_TXRF2) 865#define AR_PHY_65NM_CH1_TXRF3 AR_PHY_65NM(ch1_TXRF3) 866#define AR_PHY_65NM_CH2_TXRF1 AR_PHY_65NM(ch2_TXRF1) 867#define AR_PHY_65NM_CH2_TXRF2 AR_PHY_65NM(ch2_TXRF2) 868#define AR_PHY_65NM_CH2_TXRF3 AR_PHY_65NM(ch2_TXRF3) 869 870#define AR_PHY_65NM_CH0_SYNTH4 AR_PHY_65NM(ch0_SYNTH4) 871#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 872#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1 873#define AR_PHY_65NM_CH0_SYNTH7 AR_PHY_65NM(ch0_SYNTH7) 874#define AR_PHY_65NM_CH0_BIAS1 AR_PHY_65NM(ch0_BIAS1) 875#define AR_PHY_65NM_CH0_BIAS2 AR_PHY_65NM(ch0_BIAS2) 876#define AR_PHY_65NM_CH0_BIAS4 AR_PHY_65NM(ch0_BIAS4) 877#define AR_PHY_65NM_CH0_RXTX4 AR_PHY_65NM(ch0_RXTX4) 878#define AR_PHY_65NM_CH0_SYNTH12 AR_PHY_65NM(ch0_SYNTH12) 879#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000 880#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19 881#define AR_PHY_65NM_CH1_RXTX4 AR_PHY_65NM(ch1_RXTX4) 882#define AR_PHY_65NM_CH2_RXTX4 AR_PHY_65NM(ch2_RXTX4) 883#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000 884#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30 885 886#define AR_PHY_65NM_CH0_TOP AR_PHY_65NM(overlay_0x16180.Osprey.ch0_TOP) 887#define AR_PHY_65NM_CH0_TOP_JUPITER AR_PHY_65NM(overlay_0x16180.Jupiter.ch0_TOP1) 888#define AR_PHY_65NM_CH0_TOP_XPABIASLVL 0x00000300 889#define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S 8 890#define AR_PHY_65NM_CH0_TOP2 AR_PHY_65NM(overlay_0x16180.Osprey.ch0_TOP2) 891 892#define AR_OSPREY_CH0_XTAL AR_PHY_65NM(overlay_0x16180.Osprey.ch0_XTAL) 893#define AR_OSPREY_CHO_XTAL_CAPINDAC 0x7F000000 894#define AR_OSPREY_CHO_XTAL_CAPINDAC_S 24 895#define AR_OSPREY_CHO_XTAL_CAPOUTDAC 0x00FE0000 896#define AR_OSPREY_CHO_XTAL_CAPOUTDAC_S 17 897 898#define AR_PHY_65NM_CH0_THERM AR_PHY_65NM(overlay_0x16180.Osprey.ch0_THERM) 899#define AR_PHY_65NM_CH0_THERM_JUPITER AR_PHY_65NM(overlay_0x16180.Jupiter.ch0_THERM) 900 901#define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB 0x00000003 902#define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S 0 903#define AR_PHY_65NM_CH0_THERM_XPASHORT2GND 0x00000004 904#define AR_PHY_65NM_CH0_THERM_XPASHORT2GND_S 2 905#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00 906#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8 907#define AR_PHY_65NM_CH0_THERM_START 0x20000000 908#define AR_PHY_65NM_CH0_THERM_START_S 29 909#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 910#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 911 912#define AR_PHY_65NM_CH0_RXTX1 AR_PHY_65NM(ch0_RXTX1) 913#define AR_PHY_65NM_CH0_RXTX2 AR_PHY_65NM(ch0_RXTX2) 914#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004 915#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S 2 916#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008 917#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S 3 918#define AR_PHY_65NM_CH0_RXTX3 AR_PHY_65NM(ch0_RXTX3) 919#define AR_PHY_65NM_CH1_RXTX1 AR_PHY_65NM(ch1_RXTX1) 920#define AR_PHY_65NM_CH1_RXTX2 AR_PHY_65NM(ch1_RXTX2) 921#define AR_PHY_65NM_CH1_RXTX3 AR_PHY_65NM(ch1_RXTX3) 922#define AR_PHY_65NM_CH2_RXTX1 AR_PHY_65NM(ch2_RXTX1) 923#define AR_PHY_65NM_CH2_RXTX2 AR_PHY_65NM(ch2_RXTX2) 924#define AR_PHY_65NM_CH2_RXTX3 AR_PHY_65NM(ch2_RXTX3) 925 926#define AR_PHY_65NM_CH0_BB1 AR_PHY_65NM(ch0_BB1) 927#define AR_PHY_65NM_CH0_BB2 AR_PHY_65NM(ch0_BB2) 928#define AR_PHY_65NM_CH0_BB3 AR_PHY_65NM(ch0_BB3) 929#define AR_PHY_65NM_CH1_BB1 AR_PHY_65NM(ch1_BB1) 930#define AR_PHY_65NM_CH1_BB2 AR_PHY_65NM(ch1_BB2) 931#define AR_PHY_65NM_CH1_BB3 AR_PHY_65NM(ch1_BB3) 932#define AR_PHY_65NM_CH2_BB1 AR_PHY_65NM(ch2_BB1) 933#define AR_PHY_65NM_CH2_BB2 AR_PHY_65NM(ch2_BB2) 934#define AR_PHY_CH_BB3_SEL_OFST_READBK 0x00000300 935#define AR_PHY_CH_BB3_SEL_OFST_READBK_S 8 936#define AR_PHY_CH_BB3_OFSTCORRI2VQ 0x03e00000 937#define AR_PHY_CH_BB3_OFSTCORRI2VQ_S 21 938#define AR_PHY_CH_BB3_OFSTCORRI2VI 0x7c000000 939#define AR_PHY_CH_BB3_OFSTCORRI2VI_S 26 940 941#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000 942#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19 943#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000 944#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22 945#define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000 946#define AR_PHY_LNAGAIN_LONG_SHIFT_S 29 947#define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000 948#define AR_PHY_MXRGAIN_LONG_SHIFT_S 24 949#define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000 950#define AR_PHY_VGAGAIN_LONG_SHIFT_S 26 951#define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001 952#define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0 953#define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002 954#define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1 955#define AR_PHY_MANTXGAIN_LONG_SHIFT 0x80000000 956#define AR_PHY_MANTXGAIN_LONG_SHIFT_S 31 957 958/* 959 * SM Field Definitions 960 */ 961 962/* BB_cl_cal_ctrl - AR_PHY_CL_CAL_CTL */ 963#define AR_PHY_CL_CAL_ENABLE 0x00000002 /* do carrier leak calibration after agc_calibrate_done */ 964#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 965#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 966#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 967#define AR_PHY_CL_MAP_HW_GEN 0x80000000 968#define AR_PHY_CL_MAP_HW_GEN_S 31 969 970/* BB_addac_parallel_control - AR_PHY_ADDAC_PARA_CTL */ 971#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000 972 973/* BB_fcal_2_b0 - AR_PHY_FCAL_2_0 */ 974#define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000 975#define AR_PHY_FCAL20_CAP_STATUS_0_S 20 976 977/* BB_rfbus_request */ 978#define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */ 979/* BB_rfbus_grant */ 980#define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */ 981/* BB_gen_controls */ 982#define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */ 983#define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */ 984#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */ 985#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ 986#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ 987#define AR_PHY_GC_DYN2040_PRI_CH_S 4 988 989#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ 990#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */ 991#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ 992#define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ 993#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ 994#define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */ 995#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */ 996 997#define AR_PHY_MS_HALF_RATE 0x00000020 998#define AR_PHY_MS_QUARTER_RATE 0x00000040 999 1000/* BB_analog_power_on_time */ 1001#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ 1002/* BB_agc_control */ 1003#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ 1004#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */ 1005#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */ 1006#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */ 1007#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */ 1008#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */ 1009#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */ 1010#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */ 1011#define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000 /* allow peak deteter calibration */ 1012 1013#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 1014#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 1015 1016/* BB_iq_adc_cal_mode */ 1017#define AR_PHY_CALMODE_IQ 0x00000000 1018#define AR_PHY_CALMODE_ADC_GAIN 0x00000001 1019#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 1020#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 1021/* BB_analog_swap */ 1022#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 1023/* BB_modes_select */ 1024#define AR_PHY_MODE_OFDM 0x00000000 /* OFDM */ 1025#define AR_PHY_MODE_CCK 0x00000001 /* CCK */ 1026#define AR_PHY_MODE_DYNAMIC 0x00000004 /* dynamic CCK/OFDM mode */ 1027#define AR_PHY_MODE_DYNAMIC_S 2 1028#define AR_PHY_MODE_HALF 0x00000020 /* enable half rate */ 1029#define AR_PHY_MODE_QUARTER 0x00000040 /* enable quarter rate */ 1030#define AR_PHY_MAC_CLK_MODE 0x00000080 /* MAC runs at 128/141MHz clock */ 1031#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 /* Disable dynamic CCK detection */ 1032#define AR_PHY_MODE_SVD_HALF 0x00000200 /* enable svd half rate */ 1033#define AR_PHY_MODE_DISABLE_CCK 0x00000100 1034#define AR_PHY_MODE_DISABLE_CCK_S 8 1035/* BB_active */ 1036#define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */ 1037#define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */ 1038/* BB_force_analog */ 1039#define AR_PHY_FORCE_XPA_CFG 0x000000001 1040#define AR_PHY_FORCE_XPA_CFG_S 0 1041/* BB_xpa_timing_control */ 1042#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000 1043#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24 1044#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000 1045#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16 1046#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00 1047#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8 1048#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF 1049#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0 1050/* BB_tx_timing_3 */ 1051#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 1052#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 1053/* BB_tx_timing_2 */ 1054#define AR_PHY_TX_END_DATA_START 0x000000FF 1055#define AR_PHY_TX_END_DATA_START_S 0 1056#define AR_PHY_TX_END_PA_ON 0x0000FF00 1057#define AR_PHY_TX_END_PA_ON_S 8 1058/* BB_tpc_5_b0 */ 1059/* ar2413 power control */ 1060#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F 1061#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 1062#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 1063#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 1064#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 1065#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 1066#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 1067#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 1068#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 1069#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 1070/* BB_tpc_1 */ 1071#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 1072#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 1073#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 1074#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 1075#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 1076#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 1077#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 1078#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 1079#define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e 1080#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1 1081#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001 1082 1083/* BB_tx_forced_gain */ 1084#define AR_PHY_TXGAIN_FORCE 0x00000001 1085#define AR_PHY_TXGAIN_FORCE_S 0 1086#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00 1087#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10 1088#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000 1089#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14 1090#define AR_PHY_TXGAIN_FORCED_PADVGNRC 0x003c0000 1091#define AR_PHY_TXGAIN_FORCED_PADVGNRC_S 18 1092#define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000 1093#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22 1094#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0 1095#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6 1096#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e 1097#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1 1098#define AR_PHY_TXGAIN_FORCED_TXBB6DBGAIN 0x00000030 1099#define AR_PHY_TXGAIN_FORCED_TXBB6DBGAIN_S 4 1100 1101/* BB_powertx_rate1 */ 1102#define AR_PHY_POWER_TX_RATE1 0x9934 1103#define AR_PHY_POWER_TX_RATE2 0x9938 1104#define AR_PHY_POWER_TX_RATE_MAX AR_PHY_PWRTX_MAX 1105#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 1106/* BB_test_controls */ 1107#define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */ 1108#define RFSILENT_BB 0x00002000 /* shush bb */ 1109/* BB_chan_info_gain_diff */ 1110#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF /* PPM value is 12-bit signed integer */ 1111#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800 /* Sign bit */ 1112#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 /* Maximum absolute value */ 1113/* BB_chaninfo_ctrl */ 1114#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 1115/* BB_search_start_delay */ 1116#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ 1117/* BB_bbb_tx_ctrl */ 1118#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 1119/* BB_spectral_scan */ 1120#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 /* Enable spectral scan */ 1121#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0 1122#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan */ 1123#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 1124#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports */ 1125#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 1126#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports */ 1127#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 1128#define AR_PHY_SPECTRAL_SCAN_COUNT 0x0FFF0000 /* Number of reports */ 1129#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 1130#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x10000000 /* Short repeat */ 1131#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 28 1132#define AR_PHY_SPECTRAL_SCAN_PRIORITY_HI 0x20000000 /* high priority */ 1133#define AR_PHY_SPECTRAL_SCAN_PRIORITY_HI_S 29 1134/* BB_channel_status */ 1135#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004 1136/* BB_rtt_ctrl */ 1137#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001 1138#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0 1139#define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E 1140#define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1 1141#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080 1142#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7 1143/* BB_rtt_table_sw_intf_b0 */ 1144#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0 0x00000001 1145#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0_S 0 1146#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_0 0x00000002 1147#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_0_S 1 1148#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_0 0x0000001C 1149#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_0_S 2 1150/* BB_rtt_table_sw_intf_1_b0 */ 1151#define AR_PHY_RTT_SW_RTT_TABLE_DATA_0 0xFFFFFFF0 1152#define AR_PHY_RTT_SW_RTT_TABLE_DATA_0_S 4 1153/* BB_txiqcal_control_0 */ 1154#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000 1155#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31 1156/* BB_txiqcal_control_1 */ 1157#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000 1158#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 1159/* BB_txiqcal_start */ 1160#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 1161#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0 1162/* BB_txiqcal_start for Poseidon */ 1163#define AR_PHY_TX_IQCAL_START_DO_CAL_POSEIDON 0x80000000 1164#define AR_PHY_TX_IQCAL_START_DO_CAL_POSEIDON_S 31 1165 1166/* Generic B0, B1, B2 IQ Cal bit fields */ 1167/* BB_txiqcal_status_b* */ 1168#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 1169#define AR_PHY_CALIBRATED_GAINS_0_S 1 1170#define AR_PHY_CALIBRATED_GAINS_0 (0x1f<<AR_PHY_CALIBRATED_GAINS_0_S) 1171/* BB_txiq_corr_coeff_01_b* */ 1172#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0 1173#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff 1174#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 14 1175#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE (0x00003fff<<AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S) 1176 1177/* temp compensation */ 1178/* BB_tpc_18 */ 1179#define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff //Mask bits 7:0 1180#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0 1181/* BB_tpc_19 */ 1182#define AR_PHY_TPC_19_ALPHA_THERM 0xff //Mask bits 7:0 1183#define AR_PHY_TPC_19_ALPHA_THERM_S 0 1184 1185/* ch0_RXTX4 */ 1186#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 1187#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28 1188 1189/* BB_therm_adc_1 */ 1190#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff 1191#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0 1192 1193/* BB_therm_adc_4 */ 1194#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM 0x000000ff 1195#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_S 0 1196 1197/* BB_switch_table_chn_b */ 1198#define AR_PHY_SWITCH_TABLE_R0 0x00000010 1199#define AR_PHY_SWITCH_TABLE_R0_S 4 1200#define AR_PHY_SWITCH_TABLE_R1 0x00000040 1201#define AR_PHY_SWITCH_TABLE_R1_S 6 1202#define AR_PHY_SWITCH_TABLE_R12 0x00000100 1203#define AR_PHY_SWITCH_TABLE_R12_S 8 1204 1205/* 1206 * Channel 1 Register Map 1207 */ 1208#define AR_CHAN1_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_chn1_reg_map) 1209#define AR_CHAN1_OFFSET(_x) (AR_CHAN1_BASE + offsetof(struct chn1_reg_map, _x)) 1210 1211#define AR_PHY_TIMING4_1 AR_CHAN1_OFFSET(BB_timing_control_4_b1) 1212#define AR_PHY_EXT_CCA_1 AR_CHAN1_OFFSET(BB_ext_chan_pwr_thr_2_b1) 1213#define AR_PHY_TX_PHASE_RAMP_1 AR_CHAN1_OFFSET(BB_tx_phase_ramp_b1) 1214#define AR_PHY_ADC_GAIN_DC_CORR_1 AR_CHAN1_OFFSET(BB_adc_gain_dc_corr_b1) 1215 1216#define AR_PHY_IQ_ADC_MEAS_0_B1 AR_CHAN_OFFSET(BB_iq_adc_meas_0_b1) 1217#define AR_PHY_IQ_ADC_MEAS_1_B1 AR_CHAN_OFFSET(BB_iq_adc_meas_1_b1) 1218#define AR_PHY_IQ_ADC_MEAS_2_B1 AR_CHAN_OFFSET(BB_iq_adc_meas_2_b1) 1219#define AR_PHY_IQ_ADC_MEAS_3_B1 AR_CHAN_OFFSET(BB_iq_adc_meas_3_b1) 1220 1221#define AR_PHY_TX_IQ_CORR_1 AR_CHAN1_OFFSET(BB_tx_iq_corr_b1) 1222#define AR_PHY_SPUR_REPORT_1 AR_CHAN1_OFFSET(BB_spur_report_b1) 1223#define AR_PHY_CHAN_INFO_TAB_1 AR_CHAN1_OFFSET(BB_chan_info_chan_tab_b1) 1224#define AR_PHY_RX_IQCAL_CORR_B1 AR_CHAN1_OFFSET(BB_rx_iq_corr_b1) 1225 1226/* 1227 * Channel 1 Field Definitions 1228 */ 1229/* BB_ext_chan_pwr_thr_2_b1 */ 1230#define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 1231#define AR_PHY_CH1_EXT_MINCCA_PWR_S 16 1232 1233/* 1234 * AGC 1 Register Map 1235 */ 1236#define AR_AGC1_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_agc1_reg_map) 1237#define AR_AGC1_OFFSET(_x) (AR_AGC1_BASE + offsetof(struct agc1_reg_map, _x)) 1238 1239#define AR_PHY_FORCEMAX_GAINS_1 AR_AGC1_OFFSET(BB_gain_force_max_gains_b1) 1240#define AR_PHY_GAINS_MINOFF_1 AR_AGC1_OFFSET(BB_gains_min_offsets_b1) 1241#define AR_PHY_EXT_ATTEN_CTL_1 AR_AGC1_OFFSET(BB_ext_atten_switch_ctl_b1) 1242#define AR_PHY_CCA_1 AR_AGC1_OFFSET(BB_cca_b1) 1243#define AR_PHY_CCA_CTRL_1 AR_AGC1_OFFSET(BB_cca_ctrl_2_b1) 1244#define AR_PHY_RSSI_1 AR_AGC1_OFFSET(BB_rssi_b1) 1245#define AR_PHY_SPUR_CCK_REP_1 AR_AGC1_OFFSET(BB_spur_est_cck_report_b1) 1246#define AR_PHY_RX_OCGAIN_2 AR_AGC1_OFFSET(BB_rx_ocgain2) 1247#define AR_PHY_DIG_DC_STATUS_I_B1 AR_AGC1_OFFSET(BB_agc_dig_dc_status_i_b1) 1248#define AR_PHY_DIG_DC_STATUS_Q_B1 AR_AGC1_OFFSET(BB_agc_dig_dc_status_q_b1) 1249 1250/* 1251 * AGC 1 Register Map for Poseidon 1252 */ 1253#define AR_AGC1_BASE_POSEIDON offsetof(struct bb_reg_map, overlay_0xa800.Poseidon.bb_agc1_reg_map) 1254#define AR_AGC1_OFFSET_POSEIDON(_x) (AR_AGC1_BASE_POSEIDON + offsetof(struct agc1_reg_map, _x)) 1255 1256#define AR_PHY_FORCEMAX_GAINS_1_POSEIDON AR_AGC1_OFFSET_POSEIDON(BB_gain_force_max_gains_b1) 1257#define AR_PHY_EXT_ATTEN_CTL_1_POSEIDON AR_AGC1_OFFSET_POSEIDON(BB_ext_atten_switch_ctl_b1) 1258#define AR_PHY_RSSI_1_POSEIDON AR_AGC1_OFFSET_POSEIDON(BB_rssi_b1) 1259#define AR_PHY_RX_OCGAIN_2_POSEIDON AR_AGC1_OFFSET_POSEIDON(BB_rx_ocgain2) 1260 1261/* 1262 * AGC 1 Field Definitions 1263 */ 1264/* BB_cca_b1 */ 1265#define AR_PHY_CH1_MINCCA_PWR 0x1FF00000 1266#define AR_PHY_CH1_MINCCA_PWR_S 20 1267 1268/* 1269 * SM 1 Register Map 1270 */ 1271#define AR_SM1_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_sm1_reg_map) 1272#define AR_SM1_OFFSET(_x) (AR_SM1_BASE + offsetof(struct sm1_reg_map, _x)) 1273 1274#define AR_PHY_SWITCH_CHAIN_1 AR_SM1_OFFSET(BB_switch_table_chn_b1) 1275#define AR_PHY_FCAL_2_1 AR_SM1_OFFSET(BB_fcal_2_b1) 1276#define AR_PHY_DFT_TONE_CTL_1 AR_SM1_OFFSET(BB_dft_tone_ctrl_b1) 1277#define AR_PHY_BBGAINMAP_0_1_1 AR_SM1_OFFSET(BB_cl_bbgain_map_0_1_b1) 1278#define AR_PHY_BBGAINMAP_2_3_1 AR_SM1_OFFSET(BB_cl_bbgain_map_2_3_b1) 1279#define AR_PHY_CL_TAB_1 AR_SM1_OFFSET(BB_cl_tab_b1) 1280#define AR_PHY_CHAN_INFO_GAIN_1 AR_SM1_OFFSET(BB_chan_info_gain_b1) 1281#define AR_PHY_TPC_4_B1 AR_SM1_OFFSET(BB_tpc_4_b1) 1282#define AR_PHY_TPC_5_B1 AR_SM1_OFFSET(BB_tpc_5_b1) 1283#define AR_PHY_TPC_6_B1 AR_SM1_OFFSET(BB_tpc_6_b1) 1284#define AR_PHY_TPC_11_B1 AR_SM1_OFFSET(BB_tpc_11_b1) 1285#define AR_SCORPION_PHY_TPC_19_B1 AR_SM1_OFFSET(overlay_b440.Scorpion.BB_tpc_19_b1) 1286#define AR_PHY_PDADC_TAB_1 AR_SM1_OFFSET(overlay_b440.BB_pdadc_tab_b1) 1287 1288 1289#define AR_PHY_RTT_TABLE_SW_INTF_B1 AR_SM1_OFFSET(overlay_b440.Jupiter_20.BB_rtt_table_sw_intf_b1) 1290#define AR_PHY_RTT_TABLE_SW_INTF_1_B1 AR_SM1_OFFSET(overlay_b440.Jupiter_20.BB_rtt_table_sw_intf_1_b1) 1291 1292#define AR_PHY_TX_IQCAL_STATUS_B1 AR_SM1_OFFSET(BB_txiqcal_status_b1) 1293#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 AR_SM1_OFFSET(BB_txiq_corr_coeff_01_b1) 1294#define AR_PHY_TX_IQCAL_CORR_COEFF_23_B1 AR_SM1_OFFSET(BB_txiq_corr_coeff_23_b1) 1295#define AR_PHY_TX_IQCAL_CORR_COEFF_45_B1 AR_SM1_OFFSET(BB_txiq_corr_coeff_45_b1) 1296#define AR_PHY_TX_IQCAL_CORR_COEFF_67_B1 AR_SM1_OFFSET(BB_txiq_corr_coeff_67_b1) 1297#define AR_PHY_CL_MAP_0_B1 AR_SM1_OFFSET(BB_cl_map_0_b1) 1298#define AR_PHY_CL_MAP_1_B1 AR_SM1_OFFSET(BB_cl_map_1_b1) 1299#define AR_PHY_CL_MAP_2_B1 AR_SM1_OFFSET(BB_cl_map_2_b1) 1300#define AR_PHY_CL_MAP_3_B1 AR_SM1_OFFSET(BB_cl_map_3_b1) 1301/* 1302 * SM 1 Field Definitions 1303 */ 1304/* BB_rtt_table_sw_intf_b1 */ 1305#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_1 0x00000001 1306#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_1_S 0 1307#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_1 0x00000002 1308#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_1_S 1 1309#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_1 0x0000001C 1310#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_1_S 2 1311/* BB_rtt_table_sw_intf_1_b1 */ 1312#define AR_PHY_RTT_SW_RTT_TABLE_DATA_1 0xFFFFFFF0 1313#define AR_PHY_RTT_SW_RTT_TABLE_DATA_1_S 4 1314 1315/* 1316 * SM 1 Register Map for Poseidon 1317 */ 1318#define AR_SM1_BASE_POSEIDON offsetof(struct bb_reg_map, overlay_0xa800.Poseidon.bb_sm1_reg_map) 1319#define AR_SM1_OFFSET_POSEIDON(_x) (AR_SM1_BASE_POSEIDON + offsetof(struct sm1_reg_map, _x)) 1320 1321#define AR_PHY_SWITCH_CHAIN_1_POSEIDON AR_SM1_OFFSET_POSEIDON(BB_switch_table_chn_b1) 1322 1323/* 1324 * Channel 2 Register Map 1325 */ 1326#define AR_CHAN2_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_chn2_reg_map) 1327#define AR_CHAN2_OFFSET(_x) (AR_CHAN2_BASE + offsetof(struct chn2_reg_map, _x)) 1328 1329#define AR_PHY_TIMING4_2 AR_CHAN2_OFFSET(BB_timing_control_4_b2) 1330#define AR_PHY_EXT_CCA_2 AR_CHAN2_OFFSET(BB_ext_chan_pwr_thr_2_b2) 1331#define AR_PHY_TX_PHASE_RAMP_2 AR_CHAN2_OFFSET(BB_tx_phase_ramp_b2) 1332#define AR_PHY_ADC_GAIN_DC_CORR_2 AR_CHAN2_OFFSET(BB_adc_gain_dc_corr_b2) 1333 1334#define AR_PHY_IQ_ADC_MEAS_0_B2 AR_CHAN_OFFSET(BB_iq_adc_meas_0_b2) 1335#define AR_PHY_IQ_ADC_MEAS_1_B2 AR_CHAN_OFFSET(BB_iq_adc_meas_1_b2) 1336#define AR_PHY_IQ_ADC_MEAS_2_B2 AR_CHAN_OFFSET(BB_iq_adc_meas_2_b2) 1337#define AR_PHY_IQ_ADC_MEAS_3_B2 AR_CHAN_OFFSET(BB_iq_adc_meas_3_b2) 1338 1339#define AR_PHY_TX_IQ_CORR_2 AR_CHAN2_OFFSET(BB_tx_iq_corr_b2) 1340#define AR_PHY_SPUR_REPORT_2 AR_CHAN2_OFFSET(BB_spur_report_b2) 1341#define AR_PHY_CHAN_INFO_TAB_2 AR_CHAN2_OFFSET(BB_chan_info_chan_tab_b2) 1342#define AR_PHY_RX_IQCAL_CORR_B2 AR_CHAN2_OFFSET(BB_rx_iq_corr_b2) 1343 1344/* 1345 * Channel 2 Field Definitions 1346 */ 1347/* BB_ext_chan_pwr_thr_2_b2 */ 1348#define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000 1349#define AR_PHY_CH2_EXT_MINCCA_PWR_S 16 1350/* 1351 * AGC 2 Register Map 1352 */ 1353#define AR_AGC2_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_agc2_reg_map) 1354#define AR_AGC2_OFFSET(_x) (AR_AGC2_BASE + offsetof(struct agc2_reg_map, _x)) 1355 1356#define AR_PHY_FORCEMAX_GAINS_2 AR_AGC2_OFFSET(BB_gain_force_max_gains_b2) 1357#define AR_PHY_GAINS_MINOFF_2 AR_AGC2_OFFSET(BB_gains_min_offsets_b2) 1358#define AR_PHY_EXT_ATTEN_CTL_2 AR_AGC2_OFFSET(BB_ext_atten_switch_ctl_b2) 1359#define AR_PHY_CCA_2 AR_AGC2_OFFSET(BB_cca_b2) 1360#define AR_PHY_CCA_CTRL_2 AR_AGC2_OFFSET(BB_cca_ctrl_2_b2) 1361#define AR_PHY_RSSI_2 AR_AGC2_OFFSET(BB_rssi_b2) 1362#define AR_PHY_SPUR_CCK_REP_2 AR_AGC2_OFFSET(BB_spur_est_cck_report_b2) 1363 1364/* 1365 * AGC 2 Field Definitions 1366 */ 1367/* BB_cca_b2 */ 1368#define AR_PHY_CH2_MINCCA_PWR 0x1FF00000 1369#define AR_PHY_CH2_MINCCA_PWR_S 20 1370 1371/* 1372 * SM 2 Register Map 1373 */ 1374#define AR_SM2_BASE offsetof(struct bb_reg_map, overlay_0xa800.Osprey.bb_sm2_reg_map) 1375#define AR_SM2_OFFSET(_x) (AR_SM2_BASE + offsetof(struct sm2_reg_map, _x)) 1376 1377#define AR_PHY_SWITCH_CHAIN_2 AR_SM2_OFFSET(BB_switch_table_chn_b2) 1378#define AR_PHY_FCAL_2_2 AR_SM2_OFFSET(BB_fcal_2_b2) 1379#define AR_PHY_DFT_TONE_CTL_2 AR_SM2_OFFSET(BB_dft_tone_ctrl_b2) 1380#define AR_PHY_BBGAINMAP_0_1_2 AR_SM2_OFFSET(BB_cl_bbgain_map_0_1_b2) 1381#define AR_PHY_BBGAINMAP_2_3_2 AR_SM2_OFFSET(BB_cl_bbgain_map_2_3_b2) 1382#define AR_PHY_CL_TAB_2 AR_SM2_OFFSET(BB_cl_tab_b2) 1383#define AR_PHY_CHAN_INFO_GAIN_2 AR_SM2_OFFSET(BB_chan_info_gain_b2) 1384#define AR_PHY_TPC_4_B2 AR_SM2_OFFSET(BB_tpc_4_b2) 1385#define AR_PHY_TPC_5_B2 AR_SM2_OFFSET(BB_tpc_5_b2) 1386#define AR_PHY_TPC_6_B2 AR_SM2_OFFSET(BB_tpc_6_b2) 1387#define AR_PHY_TPC_11_B2 AR_SM2_OFFSET(BB_tpc_11_b2) 1388#define AR_SCORPION_PHY_TPC_19_B2 AR_SM2_OFFSET(overlay_c440.Scorpion.BB_tpc_19_b2) 1389#define AR_PHY_PDADC_TAB_2 AR_SM2_OFFSET(overlay_c440.BB_pdadc_tab_b2) 1390#define AR_PHY_TX_IQCAL_STATUS_B2 AR_SM2_OFFSET(BB_txiqcal_status_b2) 1391#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 AR_SM2_OFFSET(BB_txiq_corr_coeff_01_b2) 1392#define AR_PHY_TX_IQCAL_CORR_COEFF_23_B2 AR_SM2_OFFSET(BB_txiq_corr_coeff_23_b2) 1393#define AR_PHY_TX_IQCAL_CORR_COEFF_45_B2 AR_SM2_OFFSET(BB_txiq_corr_coeff_45_b2) 1394#define AR_PHY_TX_IQCAL_CORR_COEFF_67_B2 AR_SM2_OFFSET(BB_txiq_corr_coeff_67_b2) 1395 1396/* 1397 * bb_chn_ext_reg_map 1398 */ 1399#define AR_CHN_EXT_BASE_POSEIDON offsetof(struct bb_reg_map, overlay_0xa800.Poseidon.bb_chn_ext_reg_map) 1400#define AR_CHN_EXT_OFFSET_POSEIDON(_x) (AR_CHN_EXT_BASE_POSEIDON + offsetof(struct chn_ext_reg_map, _x)) 1401 1402#define AR_PHY_PAPRD_VALID_OBDB_POSEIDON AR_CHN_EXT_OFFSET_POSEIDON(BB_paprd_valid_obdb_b0) 1403#define AR_PHY_PAPRD_VALID_OBDB_0 0x3f 1404#define AR_PHY_PAPRD_VALID_OBDB_0_S 0 1405#define AR_PHY_PAPRD_VALID_OBDB_1 0x3f 1406#define AR_PHY_PAPRD_VALID_OBDB_1_S 6 1407#define AR_PHY_PAPRD_VALID_OBDB_2 0x3f 1408#define AR_PHY_PAPRD_VALID_OBDB_2_S 12 1409#define AR_PHY_PAPRD_VALID_OBDB_3 0x3f 1410#define AR_PHY_PAPRD_VALID_OBDB_3_S 18 1411#define AR_PHY_PAPRD_VALID_OBDB_4 0x3f 1412#define AR_PHY_PAPRD_VALID_OBDB_4_S 24 1413 1414/* BB_txiqcal_status_b1 */ 1415#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001 1416 1417/* 1418 * AGC 3 Register Map 1419 */ 1420#define AR_AGC3_BASE offsetof(struct bb_reg_map, bb_agc3_reg_map) 1421#define AR_AGC3_OFFSET(_x) (AR_AGC3_BASE + offsetof(struct agc3_reg_map, _x)) 1422 1423#define AR_PHY_RSSI_3 AR_AGC3_OFFSET(BB_rssi_b3) 1424 1425/* 1426 * Misc helper defines 1427 */ 1428#define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE) 1429 1430#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1431#define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1432#define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1433 1434#define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1435#define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1436#define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1437 1438#define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1439#define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1440#define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1441#define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 1442 1443#define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */ 1444#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */ 1445#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */ 1446#define AR_PHY_CHIP_ID_SOWL_REV_0 0xb0 /* 9160 Rev 0 (sowl 1.0) BB */ 1447 1448/* BB Panic Watchdog control register 1 */ 1449#define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001 1450#define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002 1451#define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000 1452#define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC 1453/* BB Panic Watchdog control register 2 */ 1454#define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002 1455#define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004 1456#define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9 1457/* BB Panic Watchdog status register */ 1458#define AR_PHY_BB_WD_STATUS 0x00000007 /* snapshot of r_panic_watchdog_sm */ 1459#define AR_PHY_BB_WD_STATUS_S 0 1460#define AR_PHY_BB_WD_DET_HANG 0x00000008 /* panic_watchdog_det_hang */ 1461#define AR_PHY_BB_WD_DET_HANG_S 3 1462#define AR_PHY_BB_WD_RADAR_SM 0x000000F0 /* snapshot of radar state machine r_rdr_sm */ 1463#define AR_PHY_BB_WD_RADAR_SM_S 4 1464#define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00 /* snapshot of rx state machine (OFDM) r_rx_sm */ 1465#define AR_PHY_BB_WD_RX_OFDM_SM_S 8 1466#define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000 /* snapshot of rx state machine (CCK) r_rx_sm_cck */ 1467#define AR_PHY_BB_WD_RX_CCK_SM_S 12 1468#define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000 /* snapshot of tx state machine (OFDM) r_tx_sm */ 1469#define AR_PHY_BB_WD_TX_OFDM_SM_S 16 1470#define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000 /* snapshot of tx state machine (CCK) r_tx_sm_cck */ 1471#define AR_PHY_BB_WD_TX_CCK_SM_S 20 1472#define AR_PHY_BB_WD_AGC_SM 0x0F000000 /* snapshot of AGC state machine r_agc_sm */ 1473#define AR_PHY_BB_WD_AGC_SM_S 24 1474#define AR_PHY_BB_WD_SRCH_SM 0xF0000000 /* snapshot of agc search state machine r_srch_sm */ 1475#define AR_PHY_BB_WD_SRCH_SM_S 28 1476 1477#define AR_PHY_BB_WD_STATUS_CLR 0x00000008 /* write 0 to reset watchdog */ 1478 1479 1480/***** PAPRD *****/ 1481#define AR_PHY_PAPRD_AM2AM AR_CHAN_OFFSET(BB_paprd_am2am_mask) 1482#define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff 1483#define AR_PHY_PAPRD_AM2AM_MASK_S 0 1484 1485#define AR_PHY_PAPRD_AM2PM AR_CHAN_OFFSET(BB_paprd_am2pm_mask) 1486#define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff 1487#define AR_PHY_PAPRD_AM2PM_MASK_S 0 1488 1489#define AR_PHY_PAPRD_HT40 AR_CHAN_OFFSET(BB_paprd_ht40_mask) 1490#define AR_PHY_PAPRD_HT40_MASK 0x01ffffff 1491#define AR_PHY_PAPRD_HT40_MASK_S 0 1492 1493#define AR_PHY_PAPRD_CTRL0_B0 AR_CHAN_OFFSET(BB_paprd_ctrl0_b0) 1494#define AR_PHY_PAPRD_CTRL0_B0_PAPRD_ENABLE_0 1 1495#define AR_PHY_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_S 0 1496#define AR_PHY_PAPRD_CTRL0_B0_USE_SINGLE_TABLE_MASK 0x00000001 1497#define AR_PHY_PAPRD_CTRL0_B0_USE_SINGLE_TABLE_MASK_S 0x00000001 1498#define AR_PHY_PAPRD_CTRL0_B0_PAPRD_MAG_THRSH_0 0x1F 1499#define AR_PHY_PAPRD_CTRL0_B0_PAPRD_MAG_THRSH_0_S 27 1500 1501#define AR_PHY_PAPRD_CTRL1_B0 AR_CHAN_OFFSET(BB_paprd_ctrl1_b0) 1502#define AR_PHY_PAPRD_CTRL1_B0_PAPRD_POWER_AT_AM2AM_CAL_0 0x3f 1503#define AR_PHY_PAPRD_CTRL1_B0_PAPRD_POWER_AT_AM2AM_CAL_0_S 3 1504#define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2PM_ENABLE_0 1 1505#define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2PM_ENABLE_0_S 2 1506#define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2AM_ENABLE_0 1 1507#define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_AM2AM_ENABLE_0_S 1 1508#define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_SCALING_ENA 1 1509#define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_SCALING_ENA_S 0 1510#define AR_PHY_PAPRD_CTRL1_B0_PA_GAIN_SCALE_FACT_0_MASK 0xFF 1511#define AR_PHY_PAPRD_CTRL1_B0_PA_GAIN_SCALE_FACT_0_MASK_S 9 1512#define AR_PHY_PAPRD_CTRL1_B0_PAPRD_MAG_SCALE_FACT_0 0x7FF 1513#define AR_PHY_PAPRD_CTRL1_B0_PAPRD_MAG_SCALE_FACT_0_S 17 1514 1515#define AR_PHY_PAPRD_CTRL0_B1 AR_CHAN1_OFFSET(BB_paprd_ctrl0_b1) 1516#define AR_PHY_PAPRD_CTRL0_B1_PAPRD_MAG_THRSH_1 0x1F 1517#define AR_PHY_PAPRD_CTRL0_B1_PAPRD_MAG_THRSH_1_S 27 1518#define AR_PHY_PAPRD_CTRL0_B1_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1 1 1519#define AR_PHY_PAPRD_CTRL0_B1_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1_S 1 1520#define AR_PHY_PAPRD_CTRL0_B1_PAPRD_ENABLE_1 1 1521#define AR_PHY_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_S 0 1522 1523#define AR_PHY_PAPRD_CTRL1_B1 AR_CHAN1_OFFSET(BB_paprd_ctrl1_b1) 1524#define AR_PHY_PAPRD_CTRL1_B1_PAPRD_POWER_AT_AM2AM_CAL_1 0x3f 1525#define AR_PHY_PAPRD_CTRL1_B1_PAPRD_POWER_AT_AM2AM_CAL_1_S 3 1526#define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2PM_ENABLE_1 1 1527#define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2PM_ENABLE_1_S 2 1528#define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2AM_ENABLE_1 1 1529#define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_AM2AM_ENABLE_1_S 1 1530#define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_SCALING_ENA 1 1531#define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_SCALING_ENA_S 0 1532#define AR_PHY_PAPRD_CTRL1_B1_PA_GAIN_SCALE_FACT_1_MASK 0xFF 1533#define AR_PHY_PAPRD_CTRL1_B1_PA_GAIN_SCALE_FACT_1_MASK_S 9 1534#define AR_PHY_PAPRD_CTRL1_B1_PAPRD_MAG_SCALE_FACT_1 0x7FF 1535#define AR_PHY_PAPRD_CTRL1_B1_PAPRD_MAG_SCALE_FACT_1_S 17 1536 1537#define AR_PHY_PAPRD_CTRL0_B2 AR_CHAN2_OFFSET(BB_paprd_ctrl0_b2) 1538#define AR_PHY_PAPRD_CTRL0_B2_PAPRD_MAG_THRSH_2 0x1F 1539#define AR_PHY_PAPRD_CTRL0_B2_PAPRD_MAG_THRSH_2_S 27 1540#define AR_PHY_PAPRD_CTRL0_B2_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2 1 1541#define AR_PHY_PAPRD_CTRL0_B2_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2_S 1 1542#define AR_PHY_PAPRD_CTRL0_B2_PAPRD_ENABLE_2 1 1543#define AR_PHY_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_S 0 1544 1545 1546#define AR_PHY_PAPRD_CTRL1_B2 AR_CHAN2_OFFSET(BB_paprd_ctrl1_b2) 1547#define AR_PHY_PAPRD_CTRL1_B2_PAPRD_POWER_AT_AM2AM_CAL_2 0x3f 1548#define AR_PHY_PAPRD_CTRL1_B2_PAPRD_POWER_AT_AM2AM_CAL_2_S 3 1549#define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2PM_ENABLE_2 1 1550#define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2PM_ENABLE_2_S 2 1551#define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2AM_ENABLE_2 1 1552#define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_AM2AM_ENABLE_2_S 1 1553#define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_SCALING_ENA 1 1554#define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_SCALING_ENA_S 0 1555#define AR_PHY_PAPRD_CTRL1_B2_PA_GAIN_SCALE_FACT_2_MASK 0xFF 1556#define AR_PHY_PAPRD_CTRL1_B2_PA_GAIN_SCALE_FACT_2_MASK_S 9 1557#define AR_PHY_PAPRD_CTRL1_B2_PAPRD_MAG_SCALE_FACT_2 0x7FF 1558#define AR_PHY_PAPRD_CTRL1_B2_PAPRD_MAG_SCALE_FACT_2_S 17 1559 1560#define AR_PHY_PAPRD_TRAINER_CNTL1 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_cntl1) 1561#define AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_cntl1) 1562#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x3f 1563#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12 1564#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 1 1565#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S 11 1566#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 1 1567#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S 10 1568#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 1 1569#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S 9 1570#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 1 1571#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S 8 1572#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x3F 1573#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S 1 1574#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 1 1575#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0 1576 1577#define AR_PHY_PAPRD_TRAINER_CNTL2 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_cntl2) 1578#define AR_PHY_PAPRD_TRAINER_CNTL2_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_cntl2) 1579#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF 1580#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0 1581 1582#define AR_PHY_PAPRD_TRAINER_CNTL3 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_cntl3) 1583#define AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_cntl3) 1584#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 1 1585#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29 1586#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0xF 1587#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S 24 1588#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0xF 1589#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20 1590#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0xF 1591#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20 1592#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x7 1593#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S 17 1594#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x1F 1595#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S 12 1596#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x3F 1597#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S 6 1598#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x3F 1599#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0 1600 1601#define AR_PHY_PAPRD_TRAINER_CNTL4 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_cntl4) 1602#define AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_cntl4) 1603#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x3FF 1604#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16 1605#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0xF 1606#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S 12 1607#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0xFFF 1608#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0 1609 1610#define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_0_b0) 1611#define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0_PAPRD_PRE_POST_SCALING_0_0 0x3FFFF 1612#define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0_PAPRD_PRE_POST_SCALING_0_0_S 0 1613 1614#define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_1_b0) 1615#define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0_PAPRD_PRE_POST_SCALING_1_0 0x3FFFF 1616#define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0_PAPRD_PRE_POST_SCALING_1_0_S 0 1617 1618#define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_2_b0) 1619#define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0_PAPRD_PRE_POST_SCALING_2_0 0x3FFFF 1620#define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0_PAPRD_PRE_POST_SCALING_2_0_S 0 1621 1622#define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_3_b0) 1623#define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0_PAPRD_PRE_POST_SCALING_3_0 0x3FFFF 1624#define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0_PAPRD_PRE_POST_SCALING_3_0_S 0 1625 1626#define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_4_b0) 1627#define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0_PAPRD_PRE_POST_SCALING_4_0 0x3FFFF 1628#define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0_PAPRD_PRE_POST_SCALING_4_0_S 0 1629 1630#define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_5_b0) 1631#define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0_PAPRD_PRE_POST_SCALING_5_0 0x3FFFF 1632#define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0_PAPRD_PRE_POST_SCALING_5_0_S 0 1633 1634#define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_6_b0) 1635#define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0_PAPRD_PRE_POST_SCALING_6_0 0x3FFFF 1636#define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0_PAPRD_PRE_POST_SCALING_6_0_S 0 1637 1638#define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 AR_CHAN_OFFSET(BB_paprd_pre_post_scale_7_b0) 1639#define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0_PAPRD_PRE_POST_SCALING_7_0 0x3FFFF 1640#define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0_PAPRD_PRE_POST_SCALING_7_0_S 0 1641 1642#define AR_PHY_PAPRD_TRAINER_STAT1 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_stat1) 1643#define AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_stat1) 1644#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0xff 1645#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S 9 1646#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x1f 1647#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S 4 1648#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x1 1649#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S 3 1650#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x1 1651#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S 2 1652#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x1 1653#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S 1 1654#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 1 1655#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0 1656 1657#define AR_PHY_PAPRD_TRAINER_STAT2 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_stat2) 1658#define AR_PHY_PAPRD_TRAINER_STAT2_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_stat2) 1659#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x3 1660#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S 21 1661#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x1F 1662#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S 16 1663#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0xffff 1664#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0 1665 1666#define AR_PHY_PAPRD_TRAINER_STAT3 AR_SM_OFFSET(overlay_0xa580.Osprey.BB_paprd_trainer_stat3) 1667#define AR_PHY_PAPRD_TRAINER_STAT3_POSEIDON AR_SM_OFFSET(overlay_0xa580.Poseidon.BB_paprd_trainer_stat3) 1668#define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0xfffff 1669#define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0 1670 1671#define AR_PHY_TPC_12 AR_SM_OFFSET(BB_tpc_12) 1672#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x1F 1673#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25 1674 1675#define AR_PHY_TPC_19_ALT_ALPHA_VOLT 0x1f 1676#define AR_PHY_TPC_19_ALT_ALPHA_VOLT_S 16 1677 1678#define AR_PHY_TPC_18_ALT_THERM_CAL_VALUE 0xff 1679#define AR_PHY_TPC_18_ALT_THERM_CAL_VALUE_S 0 1680 1681#define AR_PHY_TPC_18_ALT_VOLT_CAL_VALUE 0xff 1682#define AR_PHY_TPC_18_ALT_VOLT_CAL_VALUE_S 8 1683 1684#define AR_PHY_THERM_ADC_4 AR_SM_OFFSET(BB_therm_adc_4) 1685#define AR_PHY_THERM_ADC_4_LATEST_THERM_VALUE 0xFF 1686#define AR_PHY_THERM_ADC_4_LATEST_THERM_VALUE_S 0 1687#define AR_PHY_THERM_ADC_4_LATEST_VOLT_VALUE 0xFF 1688#define AR_PHY_THERM_ADC_4_LATEST_VOLT_VALUE_S 8 1689 1690 1691#define AR_PHY_TPC_11_B0 AR_SM_OFFSET(BB_tpc_11_b0) 1692#define AR_PHY_TPC_11_B0_OLPC_GAIN_DELTA_0 0xFF 1693#define AR_PHY_TPC_11_B0_OLPC_GAIN_DELTA_0_S 16 1694 1695#define AR_PHY_TPC_11_B1 AR_SM1_OFFSET(BB_tpc_11_b1) 1696#define AR_PHY_TPC_11_B1_OLPC_GAIN_DELTA_1 0xFF 1697#define AR_PHY_TPC_11_B1_OLPC_GAIN_DELTA_1_S 16 1698 1699#define AR_PHY_TPC_11_B2 AR_SM2_OFFSET(BB_tpc_11_b2) 1700#define AR_PHY_TPC_11_B2_OLPC_GAIN_DELTA_2 0xFF 1701#define AR_PHY_TPC_11_B2_OLPC_GAIN_DELTA_2_S 16 1702 1703 1704#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x7 1705#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S 1 1706#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x3 1707#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S 4 1708#define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0xf 1709#define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S 6 1710#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0xf 1711#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S 10 1712#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0xf 1713#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S 14 1714#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0xf 1715#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S 18 1716#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x3 1717#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S 22 1718#define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 1 1719#define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S 24 1720#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 1 1721#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0 1722 1723#define AR_PHY_TPC_1 AR_SM_OFFSET(BB_tpc_1) 1724#define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x1f 1725#define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1 1726#define AR_PHY_TPC_1_FORCE_DAC_GAIN 1 1727#define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0 1728 1729#define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 1 1730#define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3 1731 1732#define AR_PHY_PAPRD_MEM_TAB_B0 AR_CHAN_OFFSET(BB_paprd_mem_tab_b0) 1733#define AR_PHY_PAPRD_MEM_TAB_B1 AR_CHAN1_OFFSET(BB_paprd_mem_tab_b1) 1734#define AR_PHY_PAPRD_MEM_TAB_B2 AR_CHAN2_OFFSET(BB_paprd_mem_tab_b2) 1735 1736#define AR_PHY_PA_GAIN123_B0 AR_CHAN_OFFSET(BB_pa_gain123_b0) 1737#define AR_PHY_PA_GAIN123_B0_PA_GAIN1_0 0x3FF 1738#define AR_PHY_PA_GAIN123_B0_PA_GAIN1_0_S 0 1739 1740#define AR_PHY_PA_GAIN123_B1 AR_CHAN1_OFFSET(BB_pa_gain123_b1) 1741#define AR_PHY_PA_GAIN123_B1_PA_GAIN1_1 0x3FF 1742#define AR_PHY_PA_GAIN123_B1_PA_GAIN1_1_S 0 1743 1744#define AR_PHY_PA_GAIN123_B2 AR_CHAN2_OFFSET(BB_pa_gain123_b2) 1745#define AR_PHY_PA_GAIN123_B2_PA_GAIN1_2 0x3FF 1746#define AR_PHY_PA_GAIN123_B2_PA_GAIN1_2_S 0 1747 1748//Legacy 54M 1749#define AR_PHY_POWERTX_RATE2 AR_SM_OFFSET(BB_powertx_rate2) 1750#define AR_PHY_POWERTX_RATE2_POWERTX54M_7 0x3F 1751#define AR_PHY_POWERTX_RATE2_POWERTX54M_7_S 24 1752 1753#define AR_PHY_POWERTX_RATE5 AR_SM_OFFSET(BB_powertx_rate5) 1754#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F 1755#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0 1756//HT20 MCS5 1757#define AR_PHY_POWERTX_RATE5_POWERTXHT20_3 0x3F 1758#define AR_PHY_POWERTX_RATE5_POWERTXHT20_3_S 24 1759 1760//HT20 MCS7 1761#define AR_PHY_POWERTX_RATE6 AR_SM_OFFSET(BB_powertx_rate6) 1762#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F 1763#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S 8 1764//HT20 MCS6 1765#define AR_PHY_POWERTX_RATE6_POWERTXHT20_4 0x3F 1766#define AR_PHY_POWERTX_RATE6_POWERTXHT20_4_S 0 1767 1768#define AR_PHY_POWERTX_RATE7 AR_SM_OFFSET(BB_powertx_rate7) 1769//HT40 MCS5 1770#define AR_PHY_POWERTX_RATE7_POWERTXHT40_3 0x3F 1771#define AR_PHY_POWERTX_RATE7_POWERTXHT40_3_S 24 1772 1773//HT40 MCS7 1774#define AR_PHY_POWERTX_RATE8 AR_SM_OFFSET(BB_powertx_rate8) 1775#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F 1776#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8 1777//HT40 MCS6 1778#define AR_PHY_POWERTX_RATE8_POWERTXHT40_4 0x3F 1779#define AR_PHY_POWERTX_RATE8_POWERTXHT40_4_S 0 1780 1781//HT20 MCS15 1782#define AR_PHY_POWERTX_RATE10 AR_SM_OFFSET(BB_powertx_rate10) 1783#define AR_PHY_POWERTX_RATE10_POWERTXHT20_9 0x3F 1784#define AR_PHY_POWERTX_RATE10_POWERTXHT20_9_S 8 1785 1786//HT20 MCS23 1787#define AR_PHY_POWERTX_RATE11 AR_SM_OFFSET(BB_powertx_rate11) 1788#define AR_PHY_POWERTX_RATE11_POWERTXHT20_13 0x3F 1789#define AR_PHY_POWERTX_RATE11_POWERTXHT20_13_S 8 1790 1791#define AR_PHY_CL_TAB_0_CL_GAIN_MOD 0x1F 1792#define AR_PHY_CL_TAB_0_CL_GAIN_MOD_S 0 1793 1794#define AR_PHY_CL_TAB_1_CL_GAIN_MOD 0x1F 1795#define AR_PHY_CL_TAB_1_CL_GAIN_MOD_S 0 1796 1797#define AR_PHY_CL_TAB_2_CL_GAIN_MOD 0x1F 1798#define AR_PHY_CL_TAB_2_CL_GAIN_MOD_S 0 1799 1800/* 1801 * Hornet/Poseidon Analog Registers 1802 */ 1803#define AR_HORNET_CH0_TOP AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_TOP) 1804#define AR_HORNET_CH0_TOP2 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_TOP2) 1805#define AR_HORNET_CH0_TOP2_XPABIASLVL 0xf000 1806#define AR_HORNET_CH0_TOP2_XPABIASLVL_S 12 1807 1808#define AR_SCORPION_CH0_TOP AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_TOP) 1809#define AR_SCORPION_CH0_TOP_XPABIASLVL 0x3c0 1810#define AR_SCORPION_CH0_TOP_XPABIASLVL_S 6 1811 1812#define AR_SCORPION_CH0_XTAL AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_XTAL) 1813 1814#define AR_HORNET_CH0_THERM AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_THERM) 1815 1816#define AR_HORNET_CH0_XTAL AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_XTAL) 1817#define AR_HORNET_CHO_XTAL_CAPINDAC 0x7F000000 1818#define AR_HORNET_CHO_XTAL_CAPINDAC_S 24 1819#define AR_HORNET_CHO_XTAL_CAPOUTDAC 0x00FE0000 1820#define AR_HORNET_CHO_XTAL_CAPOUTDAC_S 17 1821 1822#define AR_HORNET_CH0_DDR_DPLL2 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_DDR_DPLL2) 1823#define AR_HORNET_CH0_DDR_DPLL3 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_DDR_DPLL3) 1824#define AR_PHY_CCA_NOM_VAL_HORNET_2GHZ -118 1825 1826#define AR_PHY_BB_DPLL1 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_BB_DPLL1) 1827#define AR_PHY_BB_DPLL1_REFDIV 0xF8000000 1828#define AR_PHY_BB_DPLL1_REFDIV_S 27 1829#define AR_PHY_BB_DPLL1_NINI 0x07FC0000 1830#define AR_PHY_BB_DPLL1_NINI_S 18 1831#define AR_PHY_BB_DPLL1_NFRAC 0x0003FFFF 1832#define AR_PHY_BB_DPLL1_NFRAC_S 0 1833 1834#define AR_PHY_BB_DPLL2 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_BB_DPLL2) 1835#define AR_PHY_BB_DPLL2_RANGE 0x80000000 1836#define AR_PHY_BB_DPLL2_RANGE_S 31 1837#define AR_PHY_BB_DPLL2_LOCAL_PLL 0x40000000 1838#define AR_PHY_BB_DPLL2_LOCAL_PLL_S 30 1839#define AR_PHY_BB_DPLL2_KI 0x3C000000 1840#define AR_PHY_BB_DPLL2_KI_S 26 1841#define AR_PHY_BB_DPLL2_KD 0x03F80000 1842#define AR_PHY_BB_DPLL2_KD_S 19 1843#define AR_PHY_BB_DPLL2_EN_NEGTRIG 0x00040000 1844#define AR_PHY_BB_DPLL2_EN_NEGTRIG_S 18 1845#define AR_PHY_BB_DPLL2_SEL_1SDM 0x00020000 1846#define AR_PHY_BB_DPLL2_SEL_1SDM_S 17 1847#define AR_PHY_BB_DPLL2_PLL_PWD 0x00010000 1848#define AR_PHY_BB_DPLL2_PLL_PWD_S 16 1849#define AR_PHY_BB_DPLL2_OUTDIV 0x0000E000 1850#define AR_PHY_BB_DPLL2_OUTDIV_S 13 1851#define AR_PHY_BB_DPLL2_DELTA 0x00001F80 1852#define AR_PHY_BB_DPLL2_DELTA_S 7 1853#define AR_PHY_BB_DPLL2_SPARE 0x0000007F 1854#define AR_PHY_BB_DPLL2_SPARE_S 0 1855 1856#define AR_PHY_BB_DPLL3 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_BB_DPLL3) 1857#define AR_PHY_BB_DPLL3_MEAS_AT_TXON 0x80000000 1858#define AR_PHY_BB_DPLL3_MEAS_AT_TXON_S 31 1859#define AR_PHY_BB_DPLL3_DO_MEAS 0x40000000 1860#define AR_PHY_BB_DPLL3_DO_MEAS_S 30 1861#define AR_PHY_BB_DPLL3_PHASE_SHIFT 0x3F800000 1862#define AR_PHY_BB_DPLL3_PHASE_SHIFT_S 23 1863#define AR_PHY_BB_DPLL3_SQSUM_DVC 0x007FFFF8 1864#define AR_PHY_BB_DPLL3_SQSUM_DVC_S 3 1865#define AR_PHY_BB_DPLL3_SPARE 0x00000007 1866#define AR_PHY_BB_DPLL3_SPARE_S 0x0 1867 1868#define AR_PHY_BB_DPLL4 AR_PHY_65NM(overlay_0x16180.Poseidon.ch0_BB_DPLL4) 1869#define AR_PHY_BB_DPLL4_MEAN_DVC 0xFFE00000 1870#define AR_PHY_BB_DPLL4_MEAN_DVC_S 21 1871#define AR_PHY_BB_DPLL4_VC_MEAS0 0x001FFFF0 1872#define AR_PHY_BB_DPLL4_VC_MEAS0_S 4 1873#define AR_PHY_BB_DPLL4_MEAS_DONE 0x00000008 1874#define AR_PHY_BB_DPLL4_MEAS_DONE_S 3 1875#define AR_PHY_BB_DPLL4_SPARE 0x00000007 1876#define AR_PHY_BB_DPLL4_SPARE_S 0 1877 1878/* 1879 * Wasp Analog Registers 1880 */ 1881#define AR_PHY_PLL_CONTROL AR_PHY_65NM(overlay_0x16180.Osprey.ch0_pll_cntl) 1882#define AR_PHY_PLL_MODE AR_PHY_65NM(overlay_0x16180.Osprey.ch0_pll_mode) 1883#define AR_PHY_PLL_BB_DPLL3 AR_PHY_65NM(overlay_0x16180.Osprey.ch0_bb_dpll3) 1884#define AR_PHY_PLL_BB_DPLL4 AR_PHY_65NM(overlay_0x16180.Osprey.ch0_bb_dpll4) 1885 1886/* 1887 * Wasp/Hornet PHY USB PLL control 1888 */ 1889#define AR_PHY_USB_CTRL1 0x16c84 1890#define AR_PHY_USB_CTRL2 0x16c88 1891 1892/* 1893 * PMU Register Map 1894 */ 1895#define AR_PHY_PMU(_field) offsetof(struct pmu_reg, _field) 1896#define AR_PHY_PMU1 AR_PHY_PMU(ch0_PMU1) 1897#define AR_PHY_PMU2 AR_PHY_PMU(ch0_PMU2) 1898#define AR_PHY_JUPITER_PMU(_field) offsetof(struct radio65_reg, _field) 1899#define AR_PHY_PMU1_JUPITER AR_PHY_JUPITER_PMU(overlay_0x16180.Jupiter.ch0_PMU1) 1900#define AR_PHY_PMU2_JUPITER AR_PHY_JUPITER_PMU(overlay_0x16180.Jupiter.ch0_PMU2) 1901 1902/* 1903 * GLB Register Map 1904 */ 1905#define AR_PHY_GLB(_field) offsetof(struct glb_reg, _field) 1906#define AR_PHY_GLB_CONTROL_JUPITER AR_PHY_GLB(overlap_0x20044.Jupiter.GLB_CONTROL) 1907 1908/* 1909 * PMU Field Definitions 1910 */ 1911/* ch0_PMU1 */ 1912#define AR_PHY_PMU1_PWD 0x00000001 /* power down switch regulator */ 1913#define AR_PHY_PMU1_PWD_S 0 1914 1915/* ch0_PMU2 */ 1916#define AR_PHY_PMU2_PGM 0x00200000 1917#define AR_PHY_PMU2_PGM_S 21 1918 1919/* ch0_PHY_CTRL2 */ 1920#define AR_PHY_CTRL2_TX_MAN_CAL 0x03C00000 1921#define AR_PHY_CTRL2_TX_MAN_CAL_S 22 1922#define AR_PHY_CTRL2_TX_CAL_SEL 0x00200000 1923#define AR_PHY_CTRL2_TX_CAL_SEL_S 21 1924#define AR_PHY_CTRL2_TX_CAL_EN 0x00100000 1925#define AR_PHY_CTRL2_TX_CAL_EN_S 20 1926 1927#define PCIE_CO_ERR_CTR_CTRL 0x40e8 1928#define PCIE_CO_ERR_CTR_CTR0 0x40e0 1929#define PCIE_CO_ERR_CTR_CTR1 0x40e4 1930 1931 1932#define RCVD_ERR_CTR_RUN 0x0001 1933#define RCVD_ERR_CTR_AUTO_STOP 0x0002 1934#define BAD_TLP_ERR_CTR_RUN 0x0004 1935#define BAD_TLP_ERR_CTR_AUTO_STOP 0x0008 1936#define BAD_DLLP_ERR_CTR_RUN 0x0010 1937#define BAD_DLLP_ERR_CTR_AUTO_STOP 0x0020 1938#define RPLY_TO_ERR_CTR_RUN 0x0040 1939#define RPLY_TO_ERR_CTR_AUTO_STOP 0x0080 1940#define RPLY_NUM_RO_ERR_CTR_RUN 0x0100 1941#define RPLY_NUM_RO_ERR_CTR_AUTO_STOP 0x0200 1942 1943#define RCVD_ERR_MASK 0x000000ff 1944#define RCVD_ERR_MASK_S 0 1945#define BAD_TLP_ERR_MASK 0x0000ff00 1946#define BAD_TLP_ERR_MASK_S 8 1947#define BAD_DLLP_ERR_MASK 0x00ff0000 1948#define BAD_DLLP_ERR_MASK_S 16 1949 1950#define RPLY_TO_ERR_MASK 0x000000ff 1951#define RPLY_TO_ERR_MASK_S 0 1952#define RPLY_NUM_RO_ERR_MASK 0x0000ff00 1953#define RPLY_NUM_RO_ERR_MASK_S 8 1954 1955#define AR_MERLIN_RADIO_SYNTH4 offsetof(struct merlin2_0_radio_reg_map, SYNTH4) 1956#define AR_MERLIN_RADIO_SYNTH6 offsetof(struct merlin2_0_radio_reg_map, SYNTH6) 1957#define AR_MERLIN_RADIO_SYNTH7 offsetof(struct merlin2_0_radio_reg_map, SYNTH7) 1958#define AR_MERLIN_RADIO_TOP0 offsetof(struct merlin2_0_radio_reg_map, TOP0) 1959#define AR_MERLIN_RADIO_TOP1 offsetof(struct merlin2_0_radio_reg_map, TOP1) 1960#define AR_MERLIN_RADIO_TOP2 offsetof(struct merlin2_0_radio_reg_map, TOP2) 1961#define AR_MERLIN_RADIO_TOP3 offsetof(struct merlin2_0_radio_reg_map, TOP3) 1962#endif /* _ATH_AR9300PHY_H_ */ 1963