1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: releng/12.0/sys/dev/jme/if_jmereg.h 326255 2017-11-27 14:52:40Z pfg $ 30 */ 31 32#ifndef _IF_JMEREG_H 33#define _IF_JMEREG_H 34 35/* 36 * JMicron Inc. PCI vendor ID 37 */ 38#define VENDORID_JMICRON 0x197B 39 40/* 41 * JMC250 PCI device ID 42 */ 43#define DEVICEID_JMC250 0x0250 44#define DEVICEREVID_JMC250_A0 0x00 45#define DEVICEREVID_JMC250_A2 0x11 46 47/* 48 * JMC260 PCI device ID 49 */ 50#define DEVICEID_JMC260 0x0260 51#define DEVICEREVID_JMC260_A0 0x00 52 53#define DEVICEID_JMC2XX_MASK 0x0FF0 54 55/* JMC250 PCI configuration register. */ 56#define JME_PCI_BAR0 0x10 /* 16KB memory window. */ 57 58#define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ 59 60#define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 61 62#define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 63 64#define JME_PCI_EROM 0x30 65 66#define JME_PCI_DBG 0x9C 67 68#define JME_PCI_PAR0 0xA4 /* JMC25x/JMC26x REVFM >= 5 */ 69 70#define JME_PCI_PAR1 0xA8 /* JMC25x/JMC26x REVFM >= 5 */ 71 72#define JME_PCI_SPI 0xB0 73 74#define SPI_ENB 0x00000010 75#define SPI_SO_STATUS 0x00000008 76#define SPI_SI_CTRL 0x00000004 77#define SPI_SCK_CTRL 0x00000002 78#define SPI_CS_N_CTRL 0x00000001 79 80#define JME_EFUSE_CTL1 0xB8 81#define EFUSE_CTL1_DATA_MASK 0xF0000000 82#define EFUSE_CTL1_EXECUTE 0x08000000 83#define EFUSE_CTL1_CMD_AUTOLOAD 0x02000000 84#define EFUSE_CTL1_CMD_READ 0x04000000 85#define EFUSE_CTL1_CMD_BLOW 0x06000000 86#define EFUSE_CTL1_CMD_MASK 0x06000000 87#define EFUSE_CTL1_AUTOLOAD_ERR 0x00010000 88#define EFUSE_CTL1_BYTE_SEL_MASK 0x0000FF00 89#define EFUSE_CTL1_BIT_SEL_MASK 0x00000070 90#define EFUSE_CTL1_AUTOLAOD_DONE 0x00000001 91 92#define JME_EFUSE_CTL2 0xBC 93#define EFUSE_CTL2_RESET 0x00008000 94 95#define JME_PCI_PHYCFG0 0xC0 96 97#define JME_PCI_PHYCFG1 0xC4 98 99#define JME_PCI_PHYCFG2 0xC8 100 101#define JME_PCI_PHYCFG3 0xCC 102 103#define JME_PCI_PIPECTL1 0xD0 104 105#define JME_PCI_PIPECTL2 0xD4 106 107/* PCIe link error/status. */ 108#define JME_PCI_LES 0xD8 109 110/* Proprietary register 0. */ 111#define JME_PCI_PE0 0xE0 112#define PE0_SPI_EXIST 0x00200000 113#define PE0_PME_D0 0x00100000 114#define PE0_PME_D3H 0x00080000 115#define PE0_PME_SPI_PAD 0x00040000 116#define PE0_MASK_ASPM 0x00020000 117#define PE0_EEPROM_RW_DIS 0x00008000 118#define PE0_PCI_INTA 0x00001000 119#define PE0_PCI_INTB 0x00002000 120#define PE0_PCI_INTC 0x00003000 121#define PE0_PCI_INTD 0x00004000 122#define PE0_PCI_SVSSID_WR_ENB 0x00000800 123#define PE0_MSIX_SIZE_8 0x00000700 124#define PE0_MSIX_SIZE_7 0x00000600 125#define PE0_MSIX_SIZE_6 0x00000500 126#define PE0_MSIX_SIZE_5 0x00000400 127#define PE0_MSIX_SIZE_4 0x00000300 128#define PE0_MSIX_SIZE_3 0x00000200 129#define PE0_MSIX_SIZE_2 0x00000100 130#define PE0_MSIX_SIZE_1 0x00000000 131#define PE0_MSIX_SIZE_DEF 0x00000700 132#define PE0_MSIX_CAP_DIS 0x00000080 133#define PE0_MSI_PVMC_ENB 0x00000040 134#define PE0_LCAP_EXIT_LAT_MASK 0x00000038 135#define PE0_LCAP_EXIT_LAT_DEF 0x00000038 136#define PE0_PM_AUXC_MASK 0x00000007 137#define PE0_PM_AUXC_DEF 0x00000007 138 139/* Proprietary register 1. */ 140#define JME_PCI_PE1 0xE4 141#define PE1_GIGA_PDOWN_MASK 0x0000C000 142#define PE1_GIGA_PDOWN_DIS 0x00000000 143#define PE1_GIGA_PDOWN_D3 0x00004000 144#define PE1_GIGA_PDOWN_PCIE_SHUTDOWN 0x00008000 145#define PE1_GIGA_PDOWN_PCIE_IDDQ 0x0000C000 146 147#define JME_EFUSE_EEPROM 0xE8 148#define JME_EFUSE_EEPROM_WRITE 0x80000000 149#define JME_EFUSE_EEPROM_FUNC_MASK 0x70000000 150#define JME_EFUSE_EEPROM_PAGE_MASK 0x0F000000 151#define JME_EFUSE_EEPROM_ADDR_MASK 0x00FF0000 152#define JME_EFUSE_EEPROM_DATA_MASK 0x0000FF00 153#define JME_EFUSE_EEPROM_SMBSTAT_MASK 0x000000FF 154#define JME_EFUSE_EEPROM_FUNC_SHIFT 28 155#define JME_EFUSE_EEPROM_PAGE_SHIFT 24 156#define JME_EFUSE_EEPROM_ADDR_SHIFT 16 157#define JME_EFUSE_EEPROM_DATA_SHIFT 8 158#define JME_EFUSE_EEPROM_SMBSTAT_SHIFT 0 159 160#define JME_EFUSE_EEPROM_FUNC0 0 161#define JME_EFUSE_EEPROM_PAGE_BAR0 0 162#define JME_EFUSE_EEPROM_PAGE_BAR1 1 163#define JME_EFUSE_EEPROM_PAGE_BAR2 2 164 165#define JME_PCI_PHYTEST 0xF8 166 167#define JME_PCI_GPR 0xFC 168 169/* 170 * JMC Register Map. 171 * ----------------------------------------------------------------------- 172 * Register Size IO space Memory space 173 * ----------------------------------------------------------------------- 174 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 175 * BAR1 + 0x7F BAR0 + 0x7F 176 * ----------------------------------------------------------------------- 177 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 178 * BAR2 + 0x7F BAR0 + 0x47F 179 * ----------------------------------------------------------------------- 180 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 181 * BAR2 + 0x7F BAR0 + 0x87F 182 * ----------------------------------------------------------------------- 183 * To simplify register access fuctions and to get better performance 184 * this driver doesn't support IO space access. It could be implemented 185 * as a function which selects appropriate BARs to access requested 186 * register. 187 */ 188 189/* Tx control and status. */ 190#define JME_TXCSR 0x0000 191#define TXCSR_QWEIGHT_MASK 0x0F000000 192#define TXCSR_QWEIGHT_SHIFT 24 193#define TXCSR_TXQ_SEL_MASK 0x00070000 194#define TXCSR_TXQ_SEL_SHIFT 16 195#define TXCSR_TXQ_START 0x00000001 196#define TXCSR_TXQ_START_SHIFT 8 197#define TXCSR_FIFO_THRESH_4QW 0x00000000 198#define TXCSR_FIFO_THRESH_8QW 0x00000040 199#define TXCSR_FIFO_THRESH_12QW 0x00000080 200#define TXCSR_FIFO_THRESH_16QW 0x000000C0 201#define TXCSR_DMA_SIZE_64 0x00000000 202#define TXCSR_DMA_SIZE_128 0x00000010 203#define TXCSR_DMA_SIZE_256 0x00000020 204#define TXCSR_DMA_SIZE_512 0x00000030 205#define TXCSR_DMA_BURST 0x00000004 206#define TXCSR_TX_SUSPEND 0x00000002 207#define TXCSR_TX_ENB 0x00000001 208#define TXCSR_TXQ0 0 209#define TXCSR_TXQ1 1 210#define TXCSR_TXQ2 2 211#define TXCSR_TXQ3 3 212#define TXCSR_TXQ4 4 213#define TXCSR_TXQ5 5 214#define TXCSR_TXQ6 6 215#define TXCSR_TXQ7 7 216#define TXCSR_TXQ_WEIGHT(x) \ 217 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 218#define TXCSR_TXQ_WEIGHT_MIN 0 219#define TXCSR_TXQ_WEIGHT_MAX 15 220#define TXCSR_TXQ_N_SEL(x) \ 221 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 222#define TXCSR_TXQ_N_START(x) \ 223 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 224 225/* Tx queue descriptor base address. 16bytes alignment required. */ 226#define JME_TXDBA_LO 0x0004 227#define JME_TXDBA_HI 0x0008 228 229/* Tx queue descriptor count. multiple of 16(max = 1024). */ 230#define JME_TXQDC 0x000C 231#define TXQDC_MASK 0x0000007F0 232 233/* Tx queue next descriptor address. */ 234#define JME_TXNDA 0x0010 235#define TXNDA_ADDR_MASK 0xFFFFFFF0 236#define TXNDA_DESC_EMPTY 0x00000008 237#define TXNDA_DESC_VALID 0x00000004 238#define TXNDA_DESC_WAIT 0x00000002 239#define TXNDA_DESC_FETCH 0x00000001 240 241/* Tx MAC control ans status. */ 242#define JME_TXMAC 0x0014 243#define TXMAC_IFG2_MASK 0xC0000000 244#define TXMAC_IFG2_DEFAULT 0x40000000 245#define TXMAC_IFG1_MASK 0x30000000 246#define TXMAC_IFG1_DEFAULT 0x20000000 247#define TXMAC_PAUSE_CNT_MASK 0x00FF0000 248#define TXMAC_THRESH_1_PKT 0x00000300 249#define TXMAC_THRESH_1_2_PKT 0x00000200 250#define TXMAC_THRESH_1_4_PKT 0x00000100 251#define TXMAC_THRESH_1_8_PKT 0x00000000 252#define TXMAC_FRAME_BURST 0x00000080 253#define TXMAC_CARRIER_EXT 0x00000040 254#define TXMAC_IFG_ENB 0x00000020 255#define TXMAC_BACKOFF 0x00000010 256#define TXMAC_CARRIER_SENSE 0x00000008 257#define TXMAC_COLL_ENB 0x00000004 258#define TXMAC_CRC_ENB 0x00000002 259#define TXMAC_PAD_ENB 0x00000001 260 261/* Tx pause frame control. */ 262#define JME_TXPFC 0x0018 263#define TXPFC_VLAN_TAG_MASK 0xFFFF0000 264#define TXPFC_VLAN_TAG_SHIFT 16 265#define TXPFC_VLAN_ENB 0x00008000 266#define TXPFC_PAUSE_ENB 0x00000001 267 268/* Tx timer/retry at half duplex. */ 269#define JME_TXTRHD 0x001C 270#define TXTRHD_RT_PERIOD_ENB 0x80000000 271#define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 272#define TXTRHD_RT_PERIOD_SHIFT 8 273#define TXTRHD_RT_LIMIT_ENB 0x00000080 274#define TXTRHD_RT_LIMIT_MASK 0x0000007F 275#define TXTRHD_RT_LIMIT_SHIFT 0 276#define TXTRHD_RT_PERIOD_DEFAULT 8192 277#define TXTRHD_RT_LIMIT_DEFAULT 8 278 279/* Rx control & status. */ 280#define JME_RXCSR 0x0020 281#define RXCSR_FIFO_FTHRESH_16T 0x00000000 282#define RXCSR_FIFO_FTHRESH_32T 0x10000000 283#define RXCSR_FIFO_FTHRESH_64T 0x20000000 284#define RXCSR_FIFO_FTHRESH_128T 0x30000000 285#define RXCSR_FIFO_FTHRESH_MASK 0x30000000 286#define RXCSR_FIFO_THRESH_16QW 0x00000000 287#define RXCSR_FIFO_THRESH_32QW 0x04000000 288#define RXCSR_FIFO_THRESH_64QW 0x08000000 /* JMC250/JMC260 REVFM < 2 */ 289#define RXCSR_FIFO_THRESH_128QW 0x0C000000 /* JMC250/JMC260 REVFM < 2 */ 290#define RXCSR_FIFO_THRESH_MASK 0x0C000000 291#define RXCSR_DMA_SIZE_16 0x00000000 292#define RXCSR_DMA_SIZE_32 0x01000000 293#define RXCSR_DMA_SIZE_64 0x02000000 294#define RXCSR_DMA_SIZE_128 0x03000000 295#define RXCSR_RXQ_SEL_MASK 0x00030000 296#define RXCSR_RXQ_SEL_SHIFT 16 297#define RXCSR_DESC_RT_GAP_MASK 0x0000F000 298#define RXCSR_DESC_RT_GAP_SHIFT 12 299#define RXCSR_DESC_RT_GAP_256 0x00000000 300#define RXCSR_DESC_RT_GAP_512 0x00001000 301#define RXCSR_DESC_RT_GAP_1024 0x00002000 302#define RXCSR_DESC_RT_GAP_2048 0x00003000 303#define RXCSR_DESC_RT_GAP_4096 0x00004000 304#define RXCSR_DESC_RT_GAP_8192 0x00005000 305#define RXCSR_DESC_RT_GAP_16384 0x00006000 306#define RXCSR_DESC_RT_GAP_32768 0x00007000 307#define RXCSR_DESC_RT_CNT_MASK 0x00000F00 308#define RXCSR_DESC_RT_CNT_SHIFT 8 309#define RXCSR_PASS_WAKEUP_PKT 0x00000040 310#define RXCSR_PASS_MAGIC_PKT 0x00000020 311#define RXCSR_PASS_RUNT_PKT 0x00000010 312#define RXCSR_PASS_BAD_PKT 0x00000008 313#define RXCSR_RXQ_START 0x00000004 314#define RXCSR_RX_SUSPEND 0x00000002 315#define RXCSR_RX_ENB 0x00000001 316 317#define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 318#define RXCSR_RXQ0 0 319#define RXCSR_RXQ1 1 320#define RXCSR_RXQ2 2 321#define RXCSR_RXQ3 3 322#define RXCSR_DESC_RT_CNT(x) \ 323 (((x) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 324#define RXCSR_DESC_RT_CNT_DEFAULT 0 325 326/* Rx queue descriptor base address. 16bytes alignment needed. */ 327#define JME_RXDBA_LO 0x0024 328#define JME_RXDBA_HI 0x0028 329 330/* Rx queue descriptor count. multiple of 16(max = 1024). */ 331#define JME_RXQDC 0x002C 332#define RXQDC_MASK 0x0000007F0 333 334/* Rx queue next descriptor address. */ 335#define JME_RXNDA 0x0030 336#define RXNDA_ADDR_MASK 0xFFFFFFF0 337#define RXNDA_DESC_EMPTY 0x00000008 338#define RXNDA_DESC_VALID 0x00000004 339#define RXNDA_DESC_WAIT 0x00000002 340#define RXNDA_DESC_FETCH 0x00000001 341 342/* Rx MAC control and status. */ 343#define JME_RXMAC 0x0034 344#define RXMAC_RSS_UNICAST 0x00000000 345#define RXMAC_RSS_UNI_MULTICAST 0x00010000 346#define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 347#define RXMAC_RSS_ALLFRAME 0x00030000 348#define RXMAC_PROMISC 0x00000800 349#define RXMAC_BROADCAST 0x00000400 350#define RXMAC_MULTICAST 0x00000200 351#define RXMAC_UNICAST 0x00000100 352#define RXMAC_ALLMULTI 0x00000080 353#define RXMAC_MULTICAST_FILTER 0x00000040 354#define RXMAC_COLL_DET_ENB 0x00000020 355#define RXMAC_FC_ENB 0x00000008 356#define RXMAC_VLAN_ENB 0x00000004 357#define RXMAC_PAD_10BYTES 0x00000002 358#define RXMAC_CSUM_ENB 0x00000001 359 360/* Rx unicast MAC address. Read-only on JMC25x/JMC26x REVFM >= 5 */ 361#define JME_PAR0 0x0038 362#define JME_PAR1 0x003C 363 364/* Rx multicast address hash table. */ 365#define JME_MAR0 0x0040 366#define JME_MAR1 0x0044 367 368/* Wakeup frame output data port. */ 369#define JME_WFODP 0x0048 370 371/* Wakeup frame output interface. */ 372#define JME_WFOI 0x004C 373#define WFOI_MASK_0_31 0x00000000 374#define WFOI_MASK_31_63 0x00000010 375#define WFOI_MASK_64_95 0x00000020 376#define WFOI_MASK_96_127 0x00000030 377#define WFOI_MASK_SEL 0x00000008 378#define WFOI_CRC_SEL 0x00000000 379#define WFOI_WAKEUP_FRAME_MASK 0x00000007 380#define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 381 382/* Station management interface. */ 383#define JME_SMI 0x0050 384#define SMI_DATA_MASK 0xFFFF0000 385#define SMI_DATA_SHIFT 16 386#define SMI_REG_ADDR_MASK 0x0000F800 387#define SMI_REG_ADDR_SHIFT 11 388#define SMI_PHY_ADDR_MASK 0x000007C0 389#define SMI_PHY_ADDR_SHIFT 6 390#define SMI_OP_WRITE 0x00000020 391#define SMI_OP_READ 0x00000000 392#define SMI_OP_EXECUTE 0x00000010 393#define SMI_MDIO 0x00000008 394#define SMI_MDOE 0x00000004 395#define SMI_MDC 0x00000002 396#define SMI_MDEN 0x00000001 397#define SMI_REG_ADDR(x) \ 398 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 399#define SMI_PHY_ADDR(x) \ 400 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 401 402/* Global host control. */ 403#define JME_GHC 0x0054 404#define GHC_LOOPBACK 0x80000000 405#define GHC_RESET 0x40000000 406#define GHC_RX_DMA_PWR_DIS 0x04000000 /* JMC250 REVFM >= 2 */ 407#define GHC_FIFO_RD_PWR_DIS 0x02000000 /* JMC250 REVFM >= 2 */ 408#define GHC_FIFO_WR_PWR_DIS 0x01000000 /* JMC250 REVFM >= 2 */ 409#define GHC_TX_OFFLD_CLK_100 0x00800000 /* JMC250/JMC260 REVFM >= 2 */ 410#define GHC_TX_OFFLD_CLK_1000 0x00400000 /* JMC250/JMC260 REVFM >= 2 */ 411#define GHC_TX_OFFLD_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 412#define GHC_TX_MAC_CLK_100 0x00200000 /* JMC250/JMC260 REVFM >= 2 */ 413#define GHC_TX_MAC_CLK_1000 0x00100000 /* JMC250/JMC260 REVFM >= 2 */ 414#define GHC_TX_MAC_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 415#define GHC_AUTO_PHY_STAT_DIS 0x00000080 /* JMC250/JMC260 REVFM >= 2 */ 416#define GHC_FULL_DUPLEX 0x00000040 417#define GHC_SPEED_UNKNOWN 0x00000000 418#define GHC_SPEED_10 0x00000010 419#define GHC_SPEED_100 0x00000020 420#define GHC_SPEED_1000 0x00000030 421#define GHC_SPEED_MASK 0x00000030 422#define GHC_LINK_OFF 0x00000004 423#define GHC_LINK_ON 0x00000002 424#define GHC_LINK_STAT_POLLING 0x00000001 425 426/* Power management control and status. */ 427#define JME_PMCS 0x0060 428#define PMCS_WAKEUP_FRAME_7 0x80000000 429#define PMCS_WAKEUP_FRAME_6 0x40000000 430#define PMCS_WAKEUP_FRAME_5 0x20000000 431#define PMCS_WAKEUP_FRAME_4 0x10000000 432#define PMCS_WAKEUP_FRAME_3 0x08000000 433#define PMCS_WAKEUP_FRAME_2 0x04000000 434#define PMCS_WAKEUP_FRAME_1 0x02000000 435#define PMCS_WAKEUP_FRAME_0 0x01000000 436#define PMCS_LINK_FAIL 0x00040000 437#define PMCS_LINK_RISING 0x00020000 438#define PMCS_MAGIC_FRAME 0x00010000 439#define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 440#define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 441#define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 442#define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 443#define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 444#define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 445#define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 446#define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 447#define PMCS_LINK_FAIL_ENB 0x00000004 448#define PMCS_LINK_RISING_ENB 0x00000002 449#define PMCS_MAGIC_FRAME_ENB 0x00000001 450#define PMCS_WOL_ENB_MASK 0x0000FFFF 451 452/* 453 * Statistic registers control and status. 454 * These statistics registers are valid only for JMC250/JMC260 REVFM >= 2. 455 */ 456#define JME_STATCSR 0x0064 457#define STATCSR_RXMPT_DIS 0x00000080 458#define STATCSR_OFLOW_DIS 0x00000040 459#define STATCSR_MIIRXER_DIS 0x00000020 460#define STATCSR_CRCERR_DIS 0x00000010 461#define STATCSR_RXBAD_DIS 0x00000008 462#define STATCSR_RXGOOD_DIS 0x00000004 463#define STATCSR_TXBAD_DIS 0x00000002 464#define STATCSR_TXGOOD_DIS 0x00000001 465 466#define JME_STAT_TXGOOD 0x0068 467 468#define JME_STAT_RXGOOD 0x006C 469 470#define JME_STAT_CRCMII 0x0070 471#define STAT_RX_CRC_ERR_MASK 0xFFFF0000 472#define STAT_RX_MII_ERR_MASK 0x0000FFFF 473#define STAT_RX_CRC_ERR_SHIFT 16 474#define STAT_RX_MII_ERR_SHIFT 0 475 476#define JME_STAT_RXERR 0x0074 477#define STAT_RXERR_OFLOW_MASK 0xFFFF0000 478#define STAT_RXERR_MPTY_MASK 0x0000FFFF 479#define STAT_RXERR_OFLOW_SHIFT 16 480#define STAT_RXERR_MPTY_SHIFT 0 481 482#define JME_STAT_RESERVED1 0x0078 483 484#define JME_STAT_FAIL 0x007C 485#define STAT_FAIL_RX_MASK 0xFFFF0000 486#define STAT_FAIL_TX_MASK 0x0000FFFF 487#define STAT_FAIL_RX_SHIFT 16 488#define STAT_FAIL_TX_SHIFT 0 489 490/* Giga PHY & EEPROM registers. */ 491#define JME_PHY_EEPROM_BASE_ADDR 0x0400 492 493#define JME_GIGAR0LO 0x0400 494#define JME_GIGAR0HI 0x0404 495#define JME_GIGARALO 0x0408 496#define JME_GIGARAHI 0x040C 497#define JME_GIGARBLO 0x0410 498#define JME_GIGARBHI 0x0414 499#define JME_GIGARCLO 0x0418 500#define JME_GIGARCHI 0x041C 501#define JME_GIGARDLO 0x0420 502#define JME_GIGARDHI 0x0424 503#define JME_PHYPOWDN 0x0424 /* JMC250/JMC260 REVFM >= 5 */ 504 505/* BIST status and control. */ 506#define JME_GIGACSR 0x0428 507#define GIGACSR_STATUS 0x40000000 508#define GIGACSR_CTRL_MASK 0x30000000 509#define GIGACSR_CTRL_DEFAULT 0x30000000 510#define GIGACSR_TX_CLK_MASK 0x0F000000 511#define GIGACSR_RX_CLK_MASK 0x00F00000 512#define GIGACSR_TX_CLK_INV 0x00080000 513#define GIGACSR_RX_CLK_INV 0x00040000 514#define GIGACSR_PHY_RST 0x00010000 515#define GIGACSR_IRQ_N_O 0x00001000 516#define GIGACSR_BIST_OK 0x00000200 517#define GIGACSR_BIST_DONE 0x00000100 518#define GIGACSR_BIST_LED_ENB 0x00000010 519#define GIGACSR_BIST_MASK 0x00000003 520 521/* PHY Link Status. */ 522#define JME_LNKSTS 0x0430 523#define LINKSTS_SPEED_10 0x00000000 524#define LINKSTS_SPEED_100 0x00004000 525#define LINKSTS_SPEED_1000 0x00008000 526#define LINKSTS_FULL_DUPLEX 0x00002000 527#define LINKSTS_PAGE_RCVD 0x00001000 528#define LINKSTS_SPDDPX_RESOLVED 0x00000800 529#define LINKSTS_UP 0x00000400 530#define LINKSTS_ANEG_COMP 0x00000200 531#define LINKSTS_MDI_CROSSOVR 0x00000040 532#define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 533#define LINKSTS_LPAR_PAUSE 0x00000001 534 535/* SMB control and status. */ 536#define JME_SMBCSR 0x0440 537#define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 538#define SMBCSR_WR_DATA_NACK 0x00040000 539#define SMBCSR_CMD_NACK 0x00020000 540#define SMBCSR_RELOAD 0x00010000 541#define SMBCSR_CMD_ADDR_MASK 0x0000FF00 542#define SMBCSR_SCL_STAT 0x00000080 543#define SMBCSR_SDA_STAT 0x00000040 544#define SMBCSR_EEPROM_PRESENT 0x00000020 545#define SMBCSR_INIT_LD_DONE 0x00000010 546#define SMBCSR_HW_BUSY_MASK 0x0000000F 547#define SMBCSR_HW_IDLE 0x00000000 548 549/* SMB interface. */ 550#define JME_SMBINTF 0x0444 551#define SMBINTF_RD_DATA_MASK 0xFF000000 552#define SMBINTF_RD_DATA_SHIFT 24 553#define SMBINTF_WR_DATA_MASK 0x00FF0000 554#define SMBINTF_WR_DATA_SHIFT 16 555#define SMBINTF_ADDR_MASK 0x0000FF00 556#define SMBINTF_ADDR_SHIFT 8 557#define SMBINTF_RD 0x00000020 558#define SMBINTF_WR 0x00000000 559#define SMBINTF_CMD_TRIGGER 0x00000010 560#define SMBINTF_BUSY 0x00000010 561#define SMBINTF_FAST_MODE 0x00000008 562#define SMBINTF_GPIO_SCL 0x00000004 563#define SMBINTF_GPIO_SDA 0x00000002 564#define SMBINTF_GPIO_ENB 0x00000001 565 566#define JME_EEPROM_SIG0 0x55 567#define JME_EEPROM_SIG1 0xAA 568#define JME_EEPROM_DESC_BYTES 3 569#define JME_EEPROM_DESC_END 0x80 570#define JME_EEPROM_FUNC_MASK 0x70 571#define JME_EEPROM_FUNC_SHIFT 4 572#define JME_EEPROM_PAGE_MASK 0x0F 573#define JME_EEPROM_PAGE_SHIFT 0 574 575#define JME_EEPROM_FUNC0 0 576/* PCI configuration space. */ 577#define JME_EEPROM_PAGE_BAR0 0 578/* 128 bytes I/O window. */ 579#define JME_EEPROM_PAGE_BAR1 1 580/* 256 bytes I/O window. */ 581#define JME_EEPROM_PAGE_BAR2 2 582 583#define JME_EEPROM_END 0xFF 584 585#define JME_EEPROM_MKDESC(f, p) \ 586 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 587 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 588 589/* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 590#define JME_EEPINTF 0x0448 591#define EEPINTF_DATA_MASK 0xFFFF0000 592#define EEPINTF_DATA_SHIFT 16 593#define EEPINTF_ADDR_MASK 0x0000FC00 594#define EEPINTF_ADDR_SHIFT 10 595#define EEPRINTF_OP_MASK 0x00000300 596#define EEPINTF_OP_EXECUTE 0x00000080 597#define EEPINTF_DATA_OUT 0x00000008 598#define EEPINTF_DATA_IN 0x00000004 599#define EEPINTF_CLK 0x00000002 600#define EEPINTF_SEL 0x00000001 601 602/* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 603#define JME_EEPCSR 0x044C 604#define EEPCSR_EEPROM_RELOAD 0x00000002 605#define EEPCSR_EEPROM_PRESENT 0x00000001 606 607/* Misc registers. */ 608#define JME_MISC_BASE_ADDR 0x800 609 610/* Timer control and status. */ 611#define JME_TMCSR 0x0800 612#define TMCSR_SW_INTR 0x80000000 613#define TMCSR_TIMER_INTR 0x10000000 614#define TMCSR_TIMER_ENB 0x01000000 615#define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 616 617/* GPIO control and status. */ 618#define JME_GPIO 0x0804 619#define GPIO_4_SPI_IN 0x80000000 620#define GPIO_3_SPI_IN 0x40000000 621#define GPIO_4_SPI_OUT 0x20000000 622#define GPIO_4_SPI_OUT_ENB 0x10000000 623#define GPIO_3_SPI_OUT 0x08000000 624#define GPIO_3_SPI_OUT_ENB 0x04000000 625#define GPIO_3_4_LED 0x00000000 626#define GPIO_3_4_GPIO 0x02000000 627#define GPIO_2_CLKREQN_IN 0x00100000 628#define GPIO_2_CLKREQN_OUT 0x00040000 629#define GPIO_2_CLKREQN_OUT_ENB 0x00020000 630#define GPIO_1_LED42_IN 0x00001000 631#define GPIO_1_LED42_OUT 0x00000400 632#define GPIO_1_LED42_OUT_ENB 0x00000200 633#define GPIO_1_LED42_ENB 0x00000100 634#define GPIO_0_SDA_IN 0x00000010 635#define GPIO_0_SDA_OUT 0x00000004 636#define GPIO_0_SDA_OUT_ENB 0x00000002 637#define GPIO_0_SDA_ENB 0x00000001 638 639/* General purpose register 0. */ 640#define JME_GPREG0 0x0808 641#define GPREG0_SH_POST_DW7_DIS 0x80000000 642#define GPREG0_SH_POST_DW6_DIS 0x40000000 643#define GPREG0_SH_POST_DW5_DIS 0x20000000 644#define GPREG0_SH_POST_DW4_DIS 0x10000000 645#define GPREG0_SH_POST_DW3_DIS 0x08000000 646#define GPREG0_SH_POST_DW2_DIS 0x04000000 647#define GPREG0_SH_POST_DW1_DIS 0x02000000 648#define GPREG0_SH_POST_DW0_DIS 0x01000000 649#define GPREG0_DMA_RD_REQ_8 0x00000000 650#define GPREG0_DMA_RD_REQ_6 0x00100000 651#define GPREG0_DMA_RD_REQ_5 0x00200000 652#define GPREG0_DMA_RD_REQ_4 0x00300000 653#define GPREG0_POST_DW0_ENB 0x00040000 654#define GPREG0_PCC_CLR_DIS 0x00020000 655#define GPREG0_FORCE_SCL_OUT 0x00010000 656#define GPREG0_DL_RSTB_DIS 0x00008000 657#define GPREG0_STICKY_RESET 0x00004000 658#define GPREG0_DL_RSTB_CFG_DIS 0x00002000 659#define GPREG0_LINK_CHG_POLL 0x00001000 660#define GPREG0_LINK_CHG_DIRECT 0x00000000 661#define GPREG0_MSI_GEN_SEL 0x00000800 662#define GPREG0_SMB_PAD_PU_DIS 0x00000400 663#define GPREG0_PCC_UNIT_16US 0x00000000 664#define GPREG0_PCC_UNIT_256US 0x00000100 665#define GPREG0_PCC_UNIT_US 0x00000200 666#define GPREG0_PCC_UNIT_MS 0x00000300 667#define GPREG0_PCC_UNIT_MASK 0x00000300 668#define GPREG0_INTR_EVENT_ENB 0x00000080 669#define GPREG0_PME_ENB 0x00000020 670#define GPREG0_PHY_ADDR_MASK 0x0000001F 671#define GPREG0_PHY_ADDR_SHIFT 0 672#define GPREG0_PHY_ADDR 1 673 674/* General purpose register 1. */ 675#define JME_GPREG1 0x080C 676#define GPREG1_RX_MAC_CLK_DIS 0x04000000 /* JMC250/JMC260 REVFM >= 2 */ 677#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 678#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 679#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 680#define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 681#define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 682#define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 683#define GPREG1_INTDLY_MASK 0x00000007 684 685/* MSIX entry number of interrupt source. */ 686#define JME_MSINUM_BASE 0x0810 687#define JME_MSINUM_END 0x081F 688#define MSINUM_MASK 0x7FFFFFFF 689#define MSINUM_ENTRY_MASK 7 690#define MSINUM_REG_INDEX(x) ((x) / 8) 691#define MSINUM_INTR_SOURCE(x, y) \ 692 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 693#define MSINUM_NUM_INTR_SOURCE 32 694 695/* Interrupt event status. */ 696#define JME_INTR_STATUS 0x0820 697#define INTR_SW 0x80000000 698#define INTR_TIMER 0x40000000 699#define INTR_LINKCHG 0x20000000 700#define INTR_PAUSE 0x10000000 701#define INTR_MAGIC_PKT 0x08000000 702#define INTR_WAKEUP_PKT 0x04000000 703#define INTR_RXQ0_COAL_TO 0x02000000 704#define INTR_RXQ1_COAL_TO 0x01000000 705#define INTR_RXQ2_COAL_TO 0x00800000 706#define INTR_RXQ3_COAL_TO 0x00400000 707#define INTR_TXQ_COAL_TO 0x00200000 708#define INTR_RXQ0_COAL 0x00100000 709#define INTR_RXQ1_COAL 0x00080000 710#define INTR_RXQ2_COAL 0x00040000 711#define INTR_RXQ3_COAL 0x00020000 712#define INTR_TXQ_COAL 0x00010000 713#define INTR_RXQ3_DESC_EMPTY 0x00008000 714#define INTR_RXQ2_DESC_EMPTY 0x00004000 715#define INTR_RXQ1_DESC_EMPTY 0x00002000 716#define INTR_RXQ0_DESC_EMPTY 0x00001000 717#define INTR_RXQ3_COMP 0x00000800 718#define INTR_RXQ2_COMP 0x00000400 719#define INTR_RXQ1_COMP 0x00000200 720#define INTR_RXQ0_COMP 0x00000100 721#define INTR_TXQ7_COMP 0x00000080 722#define INTR_TXQ6_COMP 0x00000040 723#define INTR_TXQ5_COMP 0x00000020 724#define INTR_TXQ4_COMP 0x00000010 725#define INTR_TXQ3_COMP 0x00000008 726#define INTR_TXQ2_COMP 0x00000004 727#define INTR_TXQ1_COMP 0x00000002 728#define INTR_TXQ0_COMP 0x00000001 729 730#define INTR_RXQ_COAL_TO \ 731 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 732 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 733 734#define INTR_RXQ_COAL \ 735 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 736 INTR_RXQ3_COAL) 737 738#define INTR_RXQ_COMP \ 739 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 740 INTR_RXQ3_COMP) 741 742#define INTR_RXQ_DESC_EMPTY \ 743 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 744 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 745 746#define INTR_RXQ_COMP \ 747 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 748 INTR_RXQ3_COMP) 749 750#define INTR_TXQ_COMP \ 751 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 752 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 753 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 754 755#define JME_INTRS \ 756 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 757 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 758 759#define N_INTR_SW 31 760#define N_INTR_TIMER 30 761#define N_INTR_LINKCHG 29 762#define N_INTR_PAUSE 28 763#define N_INTR_MAGIC_PKT 27 764#define N_INTR_WAKEUP_PKT 26 765#define N_INTR_RXQ0_COAL_TO 25 766#define N_INTR_RXQ1_COAL_TO 24 767#define N_INTR_RXQ2_COAL_TO 23 768#define N_INTR_RXQ3_COAL_TO 22 769#define N_INTR_TXQ_COAL_TO 21 770#define N_INTR_RXQ0_COAL 20 771#define N_INTR_RXQ1_COAL 19 772#define N_INTR_RXQ2_COAL 18 773#define N_INTR_RXQ3_COAL 17 774#define N_INTR_TXQ_COAL 16 775#define N_INTR_RXQ3_DESC_EMPTY 15 776#define N_INTR_RXQ2_DESC_EMPTY 14 777#define N_INTR_RXQ1_DESC_EMPTY 13 778#define N_INTR_RXQ0_DESC_EMPTY 12 779#define N_INTR_RXQ3_COMP 11 780#define N_INTR_RXQ2_COMP 10 781#define N_INTR_RXQ1_COMP 9 782#define N_INTR_RXQ0_COMP 8 783#define N_INTR_TXQ7_COMP 7 784#define N_INTR_TXQ6_COMP 6 785#define N_INTR_TXQ5_COMP 5 786#define N_INTR_TXQ4_COMP 4 787#define N_INTR_TXQ3_COMP 3 788#define N_INTR_TXQ2_COMP 2 789#define N_INTR_TXQ1_COMP 1 790#define N_INTR_TXQ0_COMP 0 791 792/* Interrupt request status. */ 793#define JME_INTR_REQ_STATUS 0x0824 794 795/* Interrupt enable - setting port. */ 796#define JME_INTR_MASK_SET 0x0828 797 798/* Interrupt enable - clearing port. */ 799#define JME_INTR_MASK_CLR 0x082C 800 801/* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 802#define JME_PCCRX0 0x0830 803#define JME_PCCRX1 0x0834 804#define JME_PCCRX2 0x0838 805#define JME_PCCRX3 0x083C 806#define PCCRX_COAL_TO_MASK 0xFFFF0000 807#define PCCRX_COAL_TO_SHIFT 16 808#define PCCRX_COAL_PKT_MASK 0x0000FF00 809#define PCCRX_COAL_PKT_SHIFT 8 810 811#define PCCRX_COAL_TO_MIN 1 812#define PCCRX_COAL_TO_DEFAULT 100 813#define PCCRX_COAL_TO_MAX 65535 814 815#define PCCRX_COAL_PKT_MIN 1 816#define PCCRX_COAL_PKT_DEFAULT 2 817#define PCCRX_COAL_PKT_MAX 255 818 819/* Packet completion coalescing control of Tx queue. */ 820#define JME_PCCTX 0x0840 821#define PCCTX_COAL_TO_MASK 0xFFFF0000 822#define PCCTX_COAL_TO_SHIFT 16 823#define PCCTX_COAL_PKT_MASK 0x0000FF00 824#define PCCTX_COAL_PKT_SHIFT 8 825#define PCCTX_COAL_TXQ7 0x00000080 826#define PCCTX_COAL_TXQ6 0x00000040 827#define PCCTX_COAL_TXQ5 0x00000020 828#define PCCTX_COAL_TXQ4 0x00000010 829#define PCCTX_COAL_TXQ3 0x00000008 830#define PCCTX_COAL_TXQ2 0x00000004 831#define PCCTX_COAL_TXQ1 0x00000002 832#define PCCTX_COAL_TXQ0 0x00000001 833 834#define PCCTX_COAL_TO_MIN 1 835#define PCCTX_COAL_TO_DEFAULT 100 836#define PCCTX_COAL_TO_MAX 65535 837 838#define PCCTX_COAL_PKT_MIN 1 839#define PCCTX_COAL_PKT_DEFAULT 8 840#define PCCTX_COAL_PKT_MAX 255 841 842/* Chip mode and FPGA version. */ 843#define JME_CHIPMODE 0x0844 844#define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 845#define CHIPMODE_FPGA_REV_SHIFT 16 846#define CHIPMODE_NOT_FPGA 0 847#define CHIPMODE_REV_MASK 0x0000FF00 848#define CHIPMODE_REV_SHIFT 8 849#define CHIPMODE_MODE_48P 0x0000000C 850#define CHIPMODE_MODE_64P 0x00000004 851#define CHIPMODE_MODE_128P_MAC 0x00000003 852#define CHIPMODE_MODE_128P_DBG 0x00000002 853#define CHIPMODE_MODE_128P_PHY 0x00000000 854/* Chip full mask revision. */ 855#define CHIPMODE_REVFM(x) ((x) & 0x0F) 856/* Chip ECO revision. */ 857#define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F) 858 859/* Shadow status base address high/low. */ 860#define JME_SHBASE_ADDR_HI 0x0848 861#define JME_SHBASE_ADDR_LO 0x084C 862#define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 863#define SHBASE_POST_FORCE 0x00000002 864#define SHBASE_POST_ENB 0x00000001 865 866#define JME_PCDRX_BASE 0x0850 867#define JME_PCDRX_END 0x0857 868#define PCDRX_REG(x) (JME_PCDRX_BASE + (((x) / 2) * 4)) 869#define PCDRX1_TO_THROTTLE_MASK 0xFF000000 870#define PCDRX1_TO_MASK 0x00FF0000 871#define PCDRX0_TO_THROTTLE_MASK 0x0000FF00 872#define PCDRX0_TO_MASK 0x000000FF 873#define PCDRX1_TO_THROTTLE_SHIFT 24 874#define PCDRX1_TO_SHIFT 16 875#define PCDRX0_TO_THROTTLE_SHIFT 8 876#define PCDRX0_TO_SHIFT 0 877#define PCDRX_TO_MIN 1 878#define PCDRX_TO_MAX 255 879 880#define JME_PCDTX 0x0858 881#define PCDTX_TO_THROTTLE_MASK 0x0000FF00 882#define PCDTX_TO_MASK 0x000000FF 883#define PCDTX_TO_THROTTLE_SHIFT 8 884#define PCDTX_TO_SHIFT 0 885#define PCDTX_TO_MIN 1 886#define PCDTX_TO_MAX 255 887 888#define JME_PCCPCD_STAT 0x085C 889#define PCCPCD_STAT_RX3_MASK 0xFF000000 890#define PCCPCD_STAT_RX2_MASK 0x00FF0000 891#define PCCPCD_STAT_RX1_MASK 0x0000FF00 892#define PCCPCD_STAT_RX0_MASK 0x000000FF 893#define PCCPCD_STAT_RX3_SHIFT 24 894#define PCCPCD_STAT_RX2_SHIFT 16 895#define PCCPCD_STAT_RX1_SHIFT 8 896#define PCCPCD_STAT_RX0_SHIFT 0 897 898/* TX data throughput in KB. */ 899#define JME_TX_THROUGHPUT 0x0860 900#define TX_THROUGHPUT_MASK 0x000FFFFF 901 902/* RX data throughput in KB. */ 903#define JME_RX_THROUGHPUT 0x0864 904#define RX_THROUGHPUT_MASK 0x000FFFFF 905 906#define JME_LPI_CTL 0x086C 907#define LPI_STAT_ANC_ANF 0x00000010 908#define LPI_STAT_AN_TIMEOUT 0x00000008 909#define LPI_STAT_RX_LPI 0x00000004 910#define LPI_INT_ENB 0x00000002 911#define LPI_REQ 0x00000001 912 913/* Timer 1 and 2. */ 914#define JME_TIMER1 0x0870 915#define JME_TIMER2 0x0874 916#define TIMER_ENB 0x01000000 917#define TIMER_CNT_MASK 0x00FFFFFF 918#define TIMER_CNT_SHIFT 0 919#define TIMER_UNIT 1024 /* 1024us */ 920 921/* Timer 3. */ 922#define JME_TIMER3 0x0878 923#define TIMER3_TIMEOUT 0x00010000 924#define TIMER3_TIMEOUT_COUNT_MASK 0x0000FF00 /* 130ms unit */ 925#define TIMER3_TIMEOUT_VAL_MASK 0x000000E0 926#define TIMER3_ENB 0x00000001 927#define TIMER3_TIMEOUT_COUNT_SHIFT 8 928#define TIMER3_TIMEOUT_VALUE_SHIFT 1 929 930/* Aggressive power mode control. */ 931#define JME_APMC 0x087C 932#define APMC_PCIE_SDOWN_STAT 0x80000000 933#define APMC_PCIE_SDOWN_ENB 0x40000000 934#define APMC_PSEUDO_HOT_PLUG 0x20000000 935#define APMC_EXT_PLUGIN_ENB 0x04000000 936#define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 937#define APMC_DIS_SRAM 0x00000004 938#define APMC_DIS_CLKPM 0x00000002 939#define APMC_DIS_CLKTX 0x00000001 940 941/* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 942#define JME_PCCSRX_BASE 0x0880 943#define JME_PCCSRX_END 0x088F 944#define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 945#define PCCSRX_TO_MASK 0xFFFF0000 946#define PCCSRX_TO_SHIFT 16 947#define PCCSRX_PKT_CNT_MASK 0x0000FF00 948#define PCCSRX_PKT_CNT_SHIFT 8 949 950/* Packet completion coalesing status of Tx queue. */ 951#define JME_PCCSTX 0x0890 952#define PCCSTX_TO_MASK 0xFFFF0000 953#define PCCSTX_TO_SHIFT 16 954#define PCCSTX_PKT_CNT_MASK 0x0000FF00 955#define PCCSTX_PKT_CNT_SHIFT 8 956 957/* Tx queues empty indicator. */ 958#define JME_TXQEMPTY 0x0894 959#define TXQEMPTY_TXQ7 0x00000080 960#define TXQEMPTY_TXQ6 0x00000040 961#define TXQEMPTY_TXQ5 0x00000020 962#define TXQEMPTY_TXQ4 0x00000010 963#define TXQEMPTY_TXQ3 0x00000008 964#define TXQEMPTY_TXQ2 0x00000004 965#define TXQEMPTY_TXQ1 0x00000002 966#define TXQEMPTY_TXQ0 0x00000001 967#define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 968 969/* RSS control registers. */ 970#define JME_RSS_BASE 0x0C00 971 972#define JME_RSSC 0x0C00 973#define RSSC_HASH_LEN_MASK 0x0000E000 974#define RSSC_HASH_64_ENTRY 0x0000A000 975#define RSSC_HASH_128_ENTRY 0x0000E000 976#define RSSC_HASH_NONE 0x00001000 977#define RSSC_HASH_IPV6 0x00000800 978#define RSSC_HASH_IPV4 0x00000400 979#define RSSC_HASH_IPV6_TCP 0x00000200 980#define RSSC_HASH_IPV4_TCP 0x00000100 981#define RSSC_NCPU_MASK 0x000000F8 982#define RSSC_NCPU_SHIFT 3 983#define RSSC_DIS_RSS 0x00000000 984#define RSSC_2RXQ_ENB 0x00000001 985#define RSSS_4RXQ_ENB 0x00000002 986 987/* CPU vector. */ 988#define JME_RSSCPU 0x0C04 989#define RSSCPU_N_SEL(x) ((1 << (x)) 990 991/* RSS Hash value. */ 992#define JME_RSSHASH 0x0C10 993 994#define JME_RSSHASH_STAT 0x0C14 995 996#define JME_RSS_RDATA0 0x0C18 997 998#define JME_RSS_RDATA1 0x0C1C 999 1000/* RSS secret key. */ 1001#define JME_RSSKEY_BASE 0x0C40 1002#define JME_RSSKEY_LAST 0x0C64 1003#define JME_RSSKEY_END 0x0C67 1004#define HASHKEY_NBYTES 40 1005#define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 1006#define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 1007 1008/* RSS indirection table entries. */ 1009#define JME_RSSTBL_BASE 0x0C80 1010#define JME_RSSTBL_END 0x0CFF 1011#define RSSTBL_NENTRY 128 1012#define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 1013#define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 1014 1015/* MSI-X table. */ 1016#define JME_MSIX_BASE_ADDR 0x2000 1017 1018#define JME_MSIX_BASE 0x2000 1019#define JME_MSIX_END 0x207F 1020#define JME_MSIX_NENTRY 8 1021#define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 1022#define MSIX_ADDR_HI_OFF 0x00 1023#define MSIX_ADDR_LO_OFF 0x04 1024#define MSIX_ADDR_LO_MASK 0xFFFFFFFC 1025#define MSIX_DATA_OFF 0x08 1026#define MSIX_VECTOR_OFF 0x0C 1027#define MSIX_VECTOR_RSVD 0x80000000 1028#define MSIX_VECTOR_DIS 0x00000001 1029 1030/* MSI-X PBA. */ 1031#define JME_MSIX_PBA_BASE_ADDR 0x3000 1032 1033#define JME_MSIX_PBA 0x3000 1034#define MSIX_PBA_RSVD_MASK 0xFFFFFF00 1035#define MSIX_PBA_RSVD_SHIFT 8 1036#define MSIX_PBA_PEND_MASK 0x000000FF 1037#define MSIX_PBA_PEND_SHIFT 0 1038#define MSIX_PBA_PEND_ENTRY7 0x00000080 1039#define MSIX_PBA_PEND_ENTRY6 0x00000040 1040#define MSIX_PBA_PEND_ENTRY5 0x00000020 1041#define MSIX_PBA_PEND_ENTRY4 0x00000010 1042#define MSIX_PBA_PEND_ENTRY3 0x00000008 1043#define MSIX_PBA_PEND_ENTRY2 0x00000004 1044#define MSIX_PBA_PEND_ENTRY1 0x00000002 1045#define MSIX_PBA_PEND_ENTRY0 0x00000001 1046 1047#define JME_PHY_OUI 0x001B8C 1048#define JME_PHY_MODEL 0x21 1049#define JME_PHY_REV 0x01 1050#define JME_PHY_ADDR 1 1051 1052/* JMC250 shadow status block. */ 1053struct jme_ssb { 1054 uint32_t dw0; 1055 uint32_t dw1; 1056 uint32_t dw2; 1057 uint32_t dw3; 1058 uint32_t dw4; 1059 uint32_t dw5; 1060 uint32_t dw6; 1061 uint32_t dw7; 1062}; 1063 1064/* JMC250 descriptor structures. */ 1065struct jme_desc { 1066 uint32_t flags; 1067 uint32_t buflen; 1068 uint32_t addr_hi; 1069 uint32_t addr_lo; 1070}; 1071 1072#define JME_TD_OWN 0x80000000 1073#define JME_TD_INTR 0x40000000 1074#define JME_TD_64BIT 0x20000000 1075#define JME_TD_TCPCSUM 0x10000000 1076#define JME_TD_UDPCSUM 0x08000000 1077#define JME_TD_IPCSUM 0x04000000 1078#define JME_TD_TSO 0x02000000 1079#define JME_TD_VLAN_TAG 0x01000000 1080#define JME_TD_VLAN_MASK 0x0000FFFF 1081 1082#define JME_TD_MSS_MASK 0xFFFC0000 1083#define JME_TD_MSS_SHIFT 18 1084#define JME_TD_BUF_LEN_MASK 0x0000FFFF 1085#define JME_TD_BUF_LEN_SHIFT 0 1086 1087#define JME_TD_FRAME_LEN_MASK 0x0000FFFF 1088#define JME_TD_FRAME_LEN_SHIFT 0 1089 1090/* 1091 * Only the first Tx descriptor of a packet is updated 1092 * after packet transmission. 1093 */ 1094#define JME_TD_TMOUT 0x20000000 1095#define JME_TD_RETRY_EXP 0x10000000 1096#define JME_TD_COLLISION 0x08000000 1097#define JME_TD_UNDERRUN 0x04000000 1098#define JME_TD_EHDR_SIZE_MASK 0x000000FF 1099#define JME_TD_EHDR_SIZE_SHIFT 0 1100 1101#define JME_TD_SEG_CNT_MASK 0xFFFF0000 1102#define JME_TD_SEG_CNT_SHIFT 16 1103#define JME_TD_RETRY_CNT_MASK 0x0000FFFF 1104#define JME_TD_RETRY_CNT_SHIFT 0 1105 1106#define JME_RD_OWN 0x80000000 1107#define JME_RD_INTR 0x40000000 1108#define JME_RD_64BIT 0x20000000 1109 1110#define JME_RD_BUF_LEN_MASK 0x0000FFFF 1111#define JME_RD_BUF_LEN_SHIFT 0 1112 1113/* 1114 * Only the first Rx descriptor of a packet is updated 1115 * after packet reception. 1116 */ 1117#define JME_RD_MORE_FRAG 0x20000000 1118#define JME_RD_TCP 0x10000000 1119#define JME_RD_UDP 0x08000000 1120#define JME_RD_IPCSUM 0x04000000 1121#define JME_RD_TCPCSUM 0x02000000 1122#define JME_RD_UDPCSUM 0x01000000 1123#define JME_RD_VLAN_TAG 0x00800000 1124#define JME_RD_IPV4 0x00400000 1125#define JME_RD_IPV6 0x00200000 1126#define JME_RD_PAUSE 0x00100000 1127#define JME_RD_MAGIC 0x00080000 1128#define JME_RD_WAKEUP 0x00040000 1129#define JME_RD_BCAST 0x00030000 1130#define JME_RD_MCAST 0x00020000 1131#define JME_RD_UCAST 0x00010000 1132#define JME_RD_VLAN_MASK 0x0000FFFF 1133#define JME_RD_VLAN_SHIFT 0 1134 1135#define JME_RD_VALID 0x80000000 1136#define JME_RD_CNT_MASK 0x7F000000 1137#define JME_RD_CNT_SHIFT 24 1138#define JME_RD_GIANT 0x00800000 1139#define JME_RD_GMII_ERR 0x00400000 1140#define JME_RD_NBL_RCVD 0x00200000 1141#define JME_RD_COLL 0x00100000 1142#define JME_RD_ABORT 0x00080000 1143#define JME_RD_RUNT 0x00040000 1144#define JME_RD_FIFO_OVRN 0x00020000 1145#define JME_RD_CRC_ERR 0x00010000 1146#define JME_RD_FRAME_LEN_MASK 0x0000FFFF 1147 1148#define JME_RX_ERR_STAT \ 1149 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 1150 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 1151 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 1152 1153#define JME_RD_ERR_MASK 0x00FF0000 1154#define JME_RD_ERR_SHIFT 16 1155#define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 1156#define JME_RX_ERR_BITS "\20" \ 1157 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 1158 "\5COLL\6NBLRCVD\7GMIIERR\10" 1159 1160#define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 1161#define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 1162#define JME_RX_PAD_BYTES 10 1163 1164#define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 1165 1166#define JME_RD_RSS_HASH_MASK 0x00003F00 1167#define JME_RD_RSS_HASH_SHIFT 8 1168#define JME_RD_RSS_HASH_NONE 0x00000000 1169#define JME_RD_RSS_HASH_IPV4 0x00000100 1170#define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1171#define JME_RD_RSS_HASH_IPV6 0x00000400 1172#define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1173#define JME_RD_HASH_FN_NONE 0x00000000 1174#define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1175 1176#endif 1177