1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* $FreeBSD$ */ 30#include "if_em.h" 31#include <sys/sbuf.h> 32#ifndef __HAIKU__ 33#include <machine/_inttypes.h> 34#endif 35 36#define em_mac_min e1000_82571 37#define igb_mac_min e1000_82575 38 39/********************************************************************* 40 * Driver version: 41 *********************************************************************/ 42char em_driver_version[] = "7.6.1-k"; 43 44/********************************************************************* 45 * PCI Device ID Table 46 * 47 * Used by probe to select devices to load on 48 * Last field stores an index into e1000_strings 49 * Last entry must be all 0s 50 * 51 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 52 *********************************************************************/ 53 54static pci_vendor_info_t em_vendor_info_array[] = 55{ 56 /* Intel(R) - lem-class legacy devices */ 57 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 61 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 62 63 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 64 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 66 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 67 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 69 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 70 71 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 72 73 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 74 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 75 76 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 79 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 80 81 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 85 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 86 87 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 89 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 96 97 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 98 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 99 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 100 101 /* Intel(R) - em-class devices */ 102 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 110 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 114 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 115 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 117 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 118 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 122 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 140 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 141 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 151 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 153 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 199 /* required last entry */ 200 PVID_END 201}; 202 203static pci_vendor_info_t igb_vendor_info_array[] = 204{ 205 /* Intel(R) - igb-class devices */ 206 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 207 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 208 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 209 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 210 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 211 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 212 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 213 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 214 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 215 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 216 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 217 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 218 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 219 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 220 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 221 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 222 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 223 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 226 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 227 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 228 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 229 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 230 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 231 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 232 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 235 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 236 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 237 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 238 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 239 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 240 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 241 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 242 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 243 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 244 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 245 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 246 /* required last entry */ 247 PVID_END 248}; 249 250/********************************************************************* 251 * Function prototypes 252 *********************************************************************/ 253static void *em_register(device_t); 254static void *igb_register(device_t); 255static int em_if_attach_pre(if_ctx_t); 256static int em_if_attach_post(if_ctx_t); 257static int em_if_detach(if_ctx_t); 258static int em_if_shutdown(if_ctx_t); 259static int em_if_suspend(if_ctx_t); 260static int em_if_resume(if_ctx_t); 261 262static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 263static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 264static void em_if_queues_free(if_ctx_t); 265 266static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 267static void em_if_init(if_ctx_t); 268static void em_if_stop(if_ctx_t); 269static void em_if_media_status(if_ctx_t, struct ifmediareq *); 270static int em_if_media_change(if_ctx_t); 271static int em_if_mtu_set(if_ctx_t, uint32_t); 272static void em_if_timer(if_ctx_t, uint16_t); 273static void em_if_vlan_register(if_ctx_t, u16); 274static void em_if_vlan_unregister(if_ctx_t, u16); 275static void em_if_watchdog_reset(if_ctx_t); 276static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 277 278static void em_identify_hardware(if_ctx_t); 279static int em_allocate_pci_resources(if_ctx_t); 280static void em_free_pci_resources(if_ctx_t); 281static void em_reset(if_ctx_t); 282static int em_setup_interface(if_ctx_t); 283static int em_setup_msix(if_ctx_t); 284 285static void em_initialize_transmit_unit(if_ctx_t); 286static void em_initialize_receive_unit(if_ctx_t); 287 288static void em_if_intr_enable(if_ctx_t); 289static void em_if_intr_disable(if_ctx_t); 290static void igb_if_intr_enable(if_ctx_t); 291static void igb_if_intr_disable(if_ctx_t); 292static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 293static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 294static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 295static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 296static void em_if_multi_set(if_ctx_t); 297static void em_if_update_admin_status(if_ctx_t); 298static void em_if_debug(if_ctx_t); 299static void em_update_stats_counters(struct e1000_softc *); 300static void em_add_hw_stats(struct e1000_softc *); 301static int em_if_set_promisc(if_ctx_t, int); 302static bool em_if_vlan_filter_capable(if_ctx_t); 303static bool em_if_vlan_filter_used(if_ctx_t); 304static void em_if_vlan_filter_enable(struct e1000_softc *); 305static void em_if_vlan_filter_disable(struct e1000_softc *); 306static void em_if_vlan_filter_write(struct e1000_softc *); 307static void em_setup_vlan_hw_support(if_ctx_t ctx); 308static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 309static void em_print_nvm_info(struct e1000_softc *); 310static void em_fw_version_locked(if_ctx_t); 311static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 312static void em_print_fw_version(struct e1000_softc *); 313static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 314static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 315static int em_get_rs(SYSCTL_HANDLER_ARGS); 316static void em_print_debug_info(struct e1000_softc *); 317static int em_is_valid_ether_addr(u8 *); 318static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 319static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 320 const char *, struct em_int_delay_info *, int, int); 321/* Management and WOL Support */ 322static void em_init_manageability(struct e1000_softc *); 323static void em_release_manageability(struct e1000_softc *); 324static void em_get_hw_control(struct e1000_softc *); 325static void em_release_hw_control(struct e1000_softc *); 326static void em_get_wakeup(if_ctx_t); 327static void em_enable_wakeup(if_ctx_t); 328static int em_enable_phy_wakeup(struct e1000_softc *); 329static void em_disable_aspm(struct e1000_softc *); 330 331int em_intr(void *); 332 333/* MSI-X handlers */ 334static int em_if_msix_intr_assign(if_ctx_t, int); 335static int em_msix_link(void *); 336static void em_handle_link(void *); 337 338static void em_enable_vectors_82574(if_ctx_t); 339 340static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 341static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 342static void em_if_led_func(if_ctx_t, int); 343 344static int em_get_regs(SYSCTL_HANDLER_ARGS); 345 346static void lem_smartspeed(struct e1000_softc *); 347static void igb_configure_queues(struct e1000_softc *); 348 349 350/********************************************************************* 351 * FreeBSD Device Interface Entry Points 352 *********************************************************************/ 353static device_method_t em_methods[] = { 354 /* Device interface */ 355 DEVMETHOD(device_register, em_register), 356 DEVMETHOD(device_probe, iflib_device_probe), 357 DEVMETHOD(device_attach, iflib_device_attach), 358 DEVMETHOD(device_detach, iflib_device_detach), 359 DEVMETHOD(device_shutdown, iflib_device_shutdown), 360 DEVMETHOD(device_suspend, iflib_device_suspend), 361 DEVMETHOD(device_resume, iflib_device_resume), 362 DEVMETHOD_END 363}; 364 365static device_method_t igb_methods[] = { 366 /* Device interface */ 367 DEVMETHOD(device_register, igb_register), 368 DEVMETHOD(device_probe, iflib_device_probe), 369 DEVMETHOD(device_attach, iflib_device_attach), 370 DEVMETHOD(device_detach, iflib_device_detach), 371 DEVMETHOD(device_shutdown, iflib_device_shutdown), 372 DEVMETHOD(device_suspend, iflib_device_suspend), 373 DEVMETHOD(device_resume, iflib_device_resume), 374 DEVMETHOD_END 375}; 376 377 378static driver_t em_driver = { 379 "em", em_methods, sizeof(struct e1000_softc), 380}; 381 382static devclass_t em_devclass; 383DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 384 385MODULE_DEPEND(em, pci, 1, 1, 1); 386MODULE_DEPEND(em, ether, 1, 1, 1); 387MODULE_DEPEND(em, iflib, 1, 1, 1); 388 389IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 390 391static driver_t igb_driver = { 392 "igb", igb_methods, sizeof(struct e1000_softc), 393}; 394 395static devclass_t igb_devclass; 396DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 397 398MODULE_DEPEND(igb, pci, 1, 1, 1); 399MODULE_DEPEND(igb, ether, 1, 1, 1); 400MODULE_DEPEND(igb, iflib, 1, 1, 1); 401 402IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 403 404static device_method_t em_if_methods[] = { 405 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 406 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 407 DEVMETHOD(ifdi_detach, em_if_detach), 408 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 409 DEVMETHOD(ifdi_suspend, em_if_suspend), 410 DEVMETHOD(ifdi_resume, em_if_resume), 411 DEVMETHOD(ifdi_init, em_if_init), 412 DEVMETHOD(ifdi_stop, em_if_stop), 413 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 414 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 415 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 416 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 417 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 418 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 419 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 420 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 421 DEVMETHOD(ifdi_media_status, em_if_media_status), 422 DEVMETHOD(ifdi_media_change, em_if_media_change), 423 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 424 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 425 DEVMETHOD(ifdi_timer, em_if_timer), 426 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 427 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 428 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 429 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 430 DEVMETHOD(ifdi_led_func, em_if_led_func), 431 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 432 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 433 DEVMETHOD(ifdi_debug, em_if_debug), 434 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 435 DEVMETHOD_END 436}; 437 438static driver_t em_if_driver = { 439 "em_if", em_if_methods, sizeof(struct e1000_softc) 440}; 441 442static device_method_t igb_if_methods[] = { 443 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 444 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 445 DEVMETHOD(ifdi_detach, em_if_detach), 446 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 447 DEVMETHOD(ifdi_suspend, em_if_suspend), 448 DEVMETHOD(ifdi_resume, em_if_resume), 449 DEVMETHOD(ifdi_init, em_if_init), 450 DEVMETHOD(ifdi_stop, em_if_stop), 451 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 452 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 453 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 454 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 455 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 456 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 457 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 458 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 459 DEVMETHOD(ifdi_media_status, em_if_media_status), 460 DEVMETHOD(ifdi_media_change, em_if_media_change), 461 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 462 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 463 DEVMETHOD(ifdi_timer, em_if_timer), 464 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 465 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 466 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 467 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 468 DEVMETHOD(ifdi_led_func, em_if_led_func), 469 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 470 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 471 DEVMETHOD(ifdi_debug, em_if_debug), 472 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 473 DEVMETHOD_END 474}; 475 476static driver_t igb_if_driver = { 477 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 478}; 479 480/********************************************************************* 481 * Tunable default values. 482 *********************************************************************/ 483 484#define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 485#define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 486 487#define MAX_INTS_PER_SEC 8000 488#define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 489 490/* Allow common code without TSO */ 491#ifndef CSUM_TSO 492#define CSUM_TSO 0 493#endif 494 495static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 496 "EM driver parameters"); 497 498static int em_disable_crc_stripping = 0; 499SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 500 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 501 502static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 503static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 504SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 505 0, "Default transmit interrupt delay in usecs"); 506SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 507 0, "Default receive interrupt delay in usecs"); 508 509static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 510static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 511SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 512 &em_tx_abs_int_delay_dflt, 0, 513 "Default transmit interrupt delay limit in usecs"); 514SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 515 &em_rx_abs_int_delay_dflt, 0, 516 "Default receive interrupt delay limit in usecs"); 517 518static int em_smart_pwr_down = false; 519SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 520 0, "Set to true to leave smart power down enabled on newer adapters"); 521 522/* Controls whether promiscuous also shows bad packets */ 523static int em_debug_sbp = false; 524SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 525 "Show bad packets in promiscuous mode"); 526 527/* How many packets rxeof tries to clean at a time */ 528static int em_rx_process_limit = 100; 529SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 530 &em_rx_process_limit, 0, 531 "Maximum number of received packets to process " 532 "at a time, -1 means unlimited"); 533 534/* Energy efficient ethernet - default to OFF */ 535static int eee_setting = 1; 536SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 537 "Enable Energy Efficient Ethernet"); 538 539/* 540** Tuneable Interrupt rate 541*/ 542static int em_max_interrupt_rate = 8000; 543SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 544 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 545 546 547 548/* Global used in WOL setup with multiport cards */ 549static int global_quad_port_a = 0; 550 551extern struct if_txrx igb_txrx; 552extern struct if_txrx em_txrx; 553extern struct if_txrx lem_txrx; 554 555static struct if_shared_ctx em_sctx_init = { 556 .isc_magic = IFLIB_MAGIC, 557 .isc_q_align = PAGE_SIZE, 558 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 559 .isc_tx_maxsegsize = PAGE_SIZE, 560 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 561 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 562 .isc_rx_maxsize = MJUM9BYTES, 563 .isc_rx_nsegments = 1, 564 .isc_rx_maxsegsize = MJUM9BYTES, 565 .isc_nfl = 1, 566 .isc_nrxqs = 1, 567 .isc_ntxqs = 1, 568 .isc_admin_intrcnt = 1, 569 .isc_vendor_info = em_vendor_info_array, 570 .isc_driver_version = em_driver_version, 571 .isc_driver = &em_if_driver, 572 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 573 574 .isc_nrxd_min = {EM_MIN_RXD}, 575 .isc_ntxd_min = {EM_MIN_TXD}, 576 .isc_nrxd_max = {EM_MAX_RXD}, 577 .isc_ntxd_max = {EM_MAX_TXD}, 578 .isc_nrxd_default = {EM_DEFAULT_RXD}, 579 .isc_ntxd_default = {EM_DEFAULT_TXD}, 580}; 581 582static struct if_shared_ctx igb_sctx_init = { 583 .isc_magic = IFLIB_MAGIC, 584 .isc_q_align = PAGE_SIZE, 585 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 586 .isc_tx_maxsegsize = PAGE_SIZE, 587 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 588 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 589 .isc_rx_maxsize = MJUM9BYTES, 590 .isc_rx_nsegments = 1, 591 .isc_rx_maxsegsize = MJUM9BYTES, 592 .isc_nfl = 1, 593 .isc_nrxqs = 1, 594 .isc_ntxqs = 1, 595 .isc_admin_intrcnt = 1, 596 .isc_vendor_info = igb_vendor_info_array, 597 .isc_driver_version = em_driver_version, 598 .isc_driver = &igb_if_driver, 599 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 600 601 .isc_nrxd_min = {EM_MIN_RXD}, 602 .isc_ntxd_min = {EM_MIN_TXD}, 603 .isc_nrxd_max = {IGB_MAX_RXD}, 604 .isc_ntxd_max = {IGB_MAX_TXD}, 605 .isc_nrxd_default = {EM_DEFAULT_RXD}, 606 .isc_ntxd_default = {EM_DEFAULT_TXD}, 607}; 608 609/***************************************************************** 610 * 611 * Dump Registers 612 * 613 ****************************************************************/ 614#define IGB_REGS_LEN 739 615 616static int em_get_regs(SYSCTL_HANDLER_ARGS) 617{ 618 struct e1000_softc *sc = (struct e1000_softc *)arg1; 619 struct e1000_hw *hw = &sc->hw; 620 struct sbuf *sb; 621 u32 *regs_buff; 622 int rc; 623 624 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 625 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 626 627 rc = sysctl_wire_old_buffer(req, 0); 628 MPASS(rc == 0); 629 if (rc != 0) { 630 free(regs_buff, M_DEVBUF); 631 return (rc); 632 } 633 634 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 635 MPASS(sb != NULL); 636 if (sb == NULL) { 637 free(regs_buff, M_DEVBUF); 638 return (ENOMEM); 639 } 640 641 /* General Registers */ 642 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 643 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 644 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 645 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 646 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 647 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 648 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 649 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 650 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 651 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 652 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 653 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 654 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 655 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 656 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 657 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 658 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 659 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 660 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 661 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 662 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 663 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 664 665 sbuf_printf(sb, "General Registers\n"); 666 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 667 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 668 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 669 670 sbuf_printf(sb, "Interrupt Registers\n"); 671 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 672 673 sbuf_printf(sb, "RX Registers\n"); 674 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 675 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 676 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 677 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 678 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 679 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 680 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 681 682 sbuf_printf(sb, "TX Registers\n"); 683 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 684 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 685 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 686 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 687 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 688 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 689 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 690 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 691 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 692 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 693 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 694 695 free(regs_buff, M_DEVBUF); 696 697#ifdef DUMP_DESCS 698 { 699 if_softc_ctx_t scctx = sc->shared; 700 struct rx_ring *rxr = &rx_que->rxr; 701 struct tx_ring *txr = &tx_que->txr; 702 int ntxd = scctx->isc_ntxd[0]; 703 int nrxd = scctx->isc_nrxd[0]; 704 int j; 705 706 for (j = 0; j < nrxd; j++) { 707 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 708 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 709 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 710 } 711 712 for (j = 0; j < min(ntxd, 256); j++) { 713 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 714 715 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 716 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 717 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 718 719 } 720 } 721#endif 722 723 rc = sbuf_finish(sb); 724 sbuf_delete(sb); 725 return(rc); 726} 727 728static void * 729em_register(device_t dev) 730{ 731 return (&em_sctx_init); 732} 733 734static void * 735igb_register(device_t dev) 736{ 737 return (&igb_sctx_init); 738} 739 740static int 741em_set_num_queues(if_ctx_t ctx) 742{ 743 struct e1000_softc *sc = iflib_get_softc(ctx); 744 int maxqueues; 745 746 /* Sanity check based on HW */ 747 switch (sc->hw.mac.type) { 748 case e1000_82576: 749 case e1000_82580: 750 case e1000_i350: 751 case e1000_i354: 752 maxqueues = 8; 753 break; 754 case e1000_i210: 755 case e1000_82575: 756 maxqueues = 4; 757 break; 758 case e1000_i211: 759 case e1000_82574: 760 maxqueues = 2; 761 break; 762 default: 763 maxqueues = 1; 764 break; 765 } 766 767 return (maxqueues); 768} 769 770#define LEM_CAPS \ 771 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 772 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 773 774#define EM_CAPS \ 775 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 776 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 777 IFCAP_LRO | IFCAP_VLAN_HWTSO 778 779#define IGB_CAPS \ 780 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 781 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 782 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 783 IFCAP_TSO6 784 785/********************************************************************* 786 * Device initialization routine 787 * 788 * The attach entry point is called when the driver is being loaded. 789 * This routine identifies the type of hardware, allocates all resources 790 * and initializes the hardware. 791 * 792 * return 0 on success, positive on failure 793 *********************************************************************/ 794static int 795em_if_attach_pre(if_ctx_t ctx) 796{ 797 struct e1000_softc *sc; 798 if_softc_ctx_t scctx; 799 device_t dev; 800 struct e1000_hw *hw; 801 struct sysctl_oid_list *child; 802 struct sysctl_ctx_list *ctx_list; 803 int error = 0; 804 805 INIT_DEBUGOUT("em_if_attach_pre: begin"); 806 dev = iflib_get_dev(ctx); 807 sc = iflib_get_softc(ctx); 808 809 sc->ctx = sc->osdep.ctx = ctx; 810 sc->dev = sc->osdep.dev = dev; 811 scctx = sc->shared = iflib_get_softc_ctx(ctx); 812 sc->media = iflib_get_media(ctx); 813 hw = &sc->hw; 814 815 sc->tx_process_limit = scctx->isc_ntxd[0]; 816 817 /* Determine hardware and mac info */ 818 em_identify_hardware(ctx); 819 820 /* SYSCTL stuff */ 821 ctx_list = device_get_sysctl_ctx(dev); 822 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 823 824 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 825 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 826 em_sysctl_nvm_info, "I", "NVM Information"); 827 828 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 829 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 830 em_sysctl_print_fw_version, "A", 831 "Prints FW/NVM Versions"); 832 833 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 834 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 835 em_sysctl_debug_info, "I", "Debug Information"); 836 837 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 838 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 839 em_set_flowcntl, "I", "Flow Control"); 840 841 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 842 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 843 em_get_regs, "A", "Dump Registers"); 844 845 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 846 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 847 em_get_rs, "I", "Dump RS indexes"); 848 849 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 850 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 851 if (bootverbose) 852 device_printf(dev, "attach_pre capping queues at %d\n", 853 scctx->isc_ntxqsets_max); 854 855 if (hw->mac.type >= igb_mac_min) { 856 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 857 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 858 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 859 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 860 scctx->isc_txrx = &igb_txrx; 861 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 862 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 863 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 864 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 865 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 866 CSUM_IP6_TCP | CSUM_IP6_UDP; 867 if (hw->mac.type != e1000_82575) 868 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 869 /* 870 ** Some new devices, as with ixgbe, now may 871 ** use a different BAR, so we need to keep 872 ** track of which is used. 873 */ 874 scctx->isc_msix_bar = pci_msix_table_bar(dev); 875 } else if (hw->mac.type >= em_mac_min) { 876 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 877 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 878 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 879 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 880 scctx->isc_txrx = &em_txrx; 881 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 882 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 883 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 884 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 885 /* 886 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 887 * by default as we don't have workarounds for all associated 888 * silicon errata. E. g., with several MACs such as 82573E, 889 * TSO only works at Gigabit speed and otherwise can cause the 890 * hardware to hang (which also would be next to impossible to 891 * work around given that already queued TSO-using descriptors 892 * would need to be flushed and vlan(4) reconfigured at runtime 893 * in case of a link speed change). Moreover, MACs like 82579 894 * still can hang at Gigabit even with all publicly documented 895 * TSO workarounds implemented. Generally, the penality of 896 * these workarounds is rather high and may involve copying 897 * mbuf data around so advantages of TSO lapse. Still, TSO may 898 * work for a few MACs of this class - at least when sticking 899 * with Gigabit - in which case users may enable TSO manually. 900 */ 901 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 902 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 903 /* 904 * We support MSI-X with 82574 only, but indicate to iflib(4) 905 * that it shall give MSI at least a try with other devices. 906 */ 907 if (hw->mac.type == e1000_82574) { 908 scctx->isc_msix_bar = pci_msix_table_bar(dev);; 909 } else { 910 scctx->isc_msix_bar = -1; 911 scctx->isc_disable_msix = 1; 912 } 913 } else { 914 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 915 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 916 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 917 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 918 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 919 scctx->isc_txrx = &lem_txrx; 920 scctx->isc_capabilities = LEM_CAPS; 921 if (hw->mac.type < e1000_82543) 922 scctx->isc_capabilities &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 923 /* 82541ER doesn't do HW tagging */ 924 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 925 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 926 /* INTx only */ 927 scctx->isc_msix_bar = 0; 928 scctx->isc_capenable = scctx->isc_capabilities; 929 } 930 931 /* Setup PCI resources */ 932 if (em_allocate_pci_resources(ctx)) { 933 device_printf(dev, "Allocation of PCI resources failed\n"); 934 error = ENXIO; 935 goto err_pci; 936 } 937 938 /* 939 ** For ICH8 and family we need to 940 ** map the flash memory, and this 941 ** must happen after the MAC is 942 ** identified 943 */ 944 if ((hw->mac.type == e1000_ich8lan) || 945 (hw->mac.type == e1000_ich9lan) || 946 (hw->mac.type == e1000_ich10lan) || 947 (hw->mac.type == e1000_pchlan) || 948 (hw->mac.type == e1000_pch2lan) || 949 (hw->mac.type == e1000_pch_lpt)) { 950 int rid = EM_BAR_TYPE_FLASH; 951 sc->flash = bus_alloc_resource_any(dev, 952 SYS_RES_MEMORY, &rid, RF_ACTIVE); 953 if (sc->flash == NULL) { 954 device_printf(dev, "Mapping of Flash failed\n"); 955 error = ENXIO; 956 goto err_pci; 957 } 958 /* This is used in the shared code */ 959 hw->flash_address = (u8 *)sc->flash; 960 sc->osdep.flash_bus_space_tag = 961 rman_get_bustag(sc->flash); 962 sc->osdep.flash_bus_space_handle = 963 rman_get_bushandle(sc->flash); 964 } 965 /* 966 ** In the new SPT device flash is not a 967 ** separate BAR, rather it is also in BAR0, 968 ** so use the same tag and an offset handle for the 969 ** FLASH read/write macros in the shared code. 970 */ 971 else if (hw->mac.type >= e1000_pch_spt) { 972 sc->osdep.flash_bus_space_tag = 973 sc->osdep.mem_bus_space_tag; 974 sc->osdep.flash_bus_space_handle = 975 sc->osdep.mem_bus_space_handle 976 + E1000_FLASH_BASE_ADDR; 977 } 978 979 /* Do Shared Code initialization */ 980 error = e1000_setup_init_funcs(hw, true); 981 if (error) { 982 device_printf(dev, "Setup of Shared code failed, error %d\n", 983 error); 984 error = ENXIO; 985 goto err_pci; 986 } 987 988 em_setup_msix(ctx); 989 e1000_get_bus_info(hw); 990 991 /* Set up some sysctls for the tunable interrupt delays */ 992 em_add_int_delay_sysctl(sc, "rx_int_delay", 993 "receive interrupt delay in usecs", &sc->rx_int_delay, 994 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 995 em_add_int_delay_sysctl(sc, "tx_int_delay", 996 "transmit interrupt delay in usecs", &sc->tx_int_delay, 997 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 998 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 999 "receive interrupt delay limit in usecs", 1000 &sc->rx_abs_int_delay, 1001 E1000_REGISTER(hw, E1000_RADV), 1002 em_rx_abs_int_delay_dflt); 1003 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1004 "transmit interrupt delay limit in usecs", 1005 &sc->tx_abs_int_delay, 1006 E1000_REGISTER(hw, E1000_TADV), 1007 em_tx_abs_int_delay_dflt); 1008 em_add_int_delay_sysctl(sc, "itr", 1009 "interrupt delay limit in usecs/4", 1010 &sc->tx_itr, 1011 E1000_REGISTER(hw, E1000_ITR), 1012 DEFAULT_ITR); 1013 1014 hw->mac.autoneg = DO_AUTO_NEG; 1015 hw->phy.autoneg_wait_to_complete = false; 1016 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1017 1018 if (hw->mac.type < em_mac_min) { 1019 e1000_init_script_state_82541(hw, true); 1020 e1000_set_tbi_compatibility_82543(hw, true); 1021 } 1022 /* Copper options */ 1023 if (hw->phy.media_type == e1000_media_type_copper) { 1024 hw->phy.mdix = AUTO_ALL_MODES; 1025 hw->phy.disable_polarity_correction = false; 1026 hw->phy.ms_type = EM_MASTER_SLAVE; 1027 } 1028 1029 /* 1030 * Set the frame limits assuming 1031 * standard ethernet sized frames. 1032 */ 1033 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1034 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1035 1036 /* 1037 * This controls when hardware reports transmit completion 1038 * status. 1039 */ 1040 hw->mac.report_tx_early = 1; 1041 1042 /* Allocate multicast array memory. */ 1043 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1044 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1045 if (sc->mta == NULL) { 1046 device_printf(dev, "Can not allocate multicast setup array\n"); 1047 error = ENOMEM; 1048 goto err_late; 1049 } 1050 1051 /* Check SOL/IDER usage */ 1052 if (e1000_check_reset_block(hw)) 1053 device_printf(dev, "PHY reset is blocked" 1054 " due to SOL/IDER session.\n"); 1055 1056 /* Sysctl for setting Energy Efficient Ethernet */ 1057 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1058 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1059 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1060 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1061 1062 /* 1063 ** Start from a known state, this is 1064 ** important in reading the nvm and 1065 ** mac from that. 1066 */ 1067 e1000_reset_hw(hw); 1068 1069 /* Make sure we have a good EEPROM before we read from it */ 1070 if (e1000_validate_nvm_checksum(hw) < 0) { 1071 /* 1072 ** Some PCI-E parts fail the first check due to 1073 ** the link being in sleep state, call it again, 1074 ** if it fails a second time its a real issue. 1075 */ 1076 if (e1000_validate_nvm_checksum(hw) < 0) { 1077 device_printf(dev, 1078 "The EEPROM Checksum Is Not Valid\n"); 1079 error = EIO; 1080 goto err_late; 1081 } 1082 } 1083 1084 /* Copy the permanent MAC address out of the EEPROM */ 1085 if (e1000_read_mac_addr(hw) < 0) { 1086 device_printf(dev, "EEPROM read error while reading MAC" 1087 " address\n"); 1088 error = EIO; 1089 goto err_late; 1090 } 1091 1092 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1093#ifndef __HAIKU__ 1094 if (sc->vf_ifp) { 1095 ether_gen_addr(iflib_get_ifp(ctx), 1096 (struct ether_addr *)hw->mac.addr); 1097 } else { 1098#else 1099 { 1100#endif 1101 device_printf(dev, "Invalid MAC address\n"); 1102 error = EIO; 1103 goto err_late; 1104 } 1105 } 1106 1107 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1108 em_fw_version_locked(ctx); 1109 1110 em_print_fw_version(sc); 1111 1112 /* Disable ULP support */ 1113 e1000_disable_ulp_lpt_lp(hw, true); 1114 1115 /* 1116 * Get Wake-on-Lan and Management info for later use 1117 */ 1118 em_get_wakeup(ctx); 1119 1120 /* Enable only WOL MAGIC by default */ 1121 scctx->isc_capenable &= ~IFCAP_WOL; 1122 if (sc->wol != 0) 1123 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1124 1125 iflib_set_mac(ctx, hw->mac.addr); 1126 1127 return (0); 1128 1129err_late: 1130 em_release_hw_control(sc); 1131err_pci: 1132 em_free_pci_resources(ctx); 1133 free(sc->mta, M_DEVBUF); 1134 1135 return (error); 1136} 1137 1138static int 1139em_if_attach_post(if_ctx_t ctx) 1140{ 1141 struct e1000_softc *sc = iflib_get_softc(ctx); 1142 struct e1000_hw *hw = &sc->hw; 1143 int error = 0; 1144 1145 /* Setup OS specific network interface */ 1146 error = em_setup_interface(ctx); 1147 if (error != 0) { 1148 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1149 goto err_late; 1150 } 1151 1152 em_reset(ctx); 1153 1154 /* Initialize statistics */ 1155 em_update_stats_counters(sc); 1156 hw->mac.get_link_status = 1; 1157 em_if_update_admin_status(ctx); 1158 em_add_hw_stats(sc); 1159 1160 /* Non-AMT based hardware can now take control from firmware */ 1161 if (sc->has_manage && !sc->has_amt) 1162 em_get_hw_control(sc); 1163 1164 INIT_DEBUGOUT("em_if_attach_post: end"); 1165 1166 return (0); 1167 1168err_late: 1169 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1170 return (error); 1171} 1172 1173/********************************************************************* 1174 * Device removal routine 1175 * 1176 * The detach entry point is called when the driver is being removed. 1177 * This routine stops the adapter and deallocates all the resources 1178 * that were allocated for driver operation. 1179 * 1180 * return 0 on success, positive on failure 1181 *********************************************************************/ 1182static int 1183em_if_detach(if_ctx_t ctx) 1184{ 1185 struct e1000_softc *sc = iflib_get_softc(ctx); 1186 1187 INIT_DEBUGOUT("em_if_detach: begin"); 1188 1189 e1000_phy_hw_reset(&sc->hw); 1190 1191 em_release_manageability(sc); 1192 em_release_hw_control(sc); 1193 em_free_pci_resources(ctx); 1194 free(sc->mta, M_DEVBUF); 1195 sc->mta = NULL; 1196 1197 return (0); 1198} 1199 1200/********************************************************************* 1201 * 1202 * Shutdown entry point 1203 * 1204 **********************************************************************/ 1205 1206static int 1207em_if_shutdown(if_ctx_t ctx) 1208{ 1209 return em_if_suspend(ctx); 1210} 1211 1212/* 1213 * Suspend/resume device methods. 1214 */ 1215static int 1216em_if_suspend(if_ctx_t ctx) 1217{ 1218 struct e1000_softc *sc = iflib_get_softc(ctx); 1219 1220 em_release_manageability(sc); 1221 em_release_hw_control(sc); 1222 em_enable_wakeup(ctx); 1223 return (0); 1224} 1225 1226static int 1227em_if_resume(if_ctx_t ctx) 1228{ 1229 struct e1000_softc *sc = iflib_get_softc(ctx); 1230 1231 if (sc->hw.mac.type == e1000_pch2lan) 1232 e1000_resume_workarounds_pchlan(&sc->hw); 1233 em_if_init(ctx); 1234 em_init_manageability(sc); 1235 1236 return(0); 1237} 1238 1239static int 1240em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1241{ 1242 int max_frame_size; 1243 struct e1000_softc *sc = iflib_get_softc(ctx); 1244 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1245 1246 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1247 1248 switch (sc->hw.mac.type) { 1249 case e1000_82571: 1250 case e1000_82572: 1251 case e1000_ich9lan: 1252 case e1000_ich10lan: 1253 case e1000_pch2lan: 1254 case e1000_pch_lpt: 1255 case e1000_pch_spt: 1256 case e1000_pch_cnp: 1257 case e1000_pch_tgp: 1258 case e1000_pch_adp: 1259 case e1000_pch_mtp: 1260 case e1000_82574: 1261 case e1000_82583: 1262 case e1000_80003es2lan: 1263 /* 9K Jumbo Frame size */ 1264 max_frame_size = 9234; 1265 break; 1266 case e1000_pchlan: 1267 max_frame_size = 4096; 1268 break; 1269 case e1000_82542: 1270 case e1000_ich8lan: 1271 /* Adapters that do not support jumbo frames */ 1272 max_frame_size = ETHER_MAX_LEN; 1273 break; 1274 default: 1275 if (sc->hw.mac.type >= igb_mac_min) 1276 max_frame_size = 9234; 1277 else /* lem */ 1278 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1279 } 1280 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1281 return (EINVAL); 1282 } 1283 1284 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1285 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1286 return (0); 1287} 1288 1289/********************************************************************* 1290 * Init entry point 1291 * 1292 * This routine is used in two ways. It is used by the stack as 1293 * init entry point in network interface structure. It is also used 1294 * by the driver as a hw/sw initialization routine to get to a 1295 * consistent state. 1296 * 1297 **********************************************************************/ 1298static void 1299em_if_init(if_ctx_t ctx) 1300{ 1301 struct e1000_softc *sc = iflib_get_softc(ctx); 1302 if_softc_ctx_t scctx = sc->shared; 1303 struct ifnet *ifp = iflib_get_ifp(ctx); 1304 struct em_tx_queue *tx_que; 1305 int i; 1306 1307 INIT_DEBUGOUT("em_if_init: begin"); 1308 1309 /* Get the latest mac address, User can use a LAA */ 1310 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1311 ETHER_ADDR_LEN); 1312 1313 /* Put the address into the Receive Address Array */ 1314 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1315 1316 /* 1317 * With the 82571 adapter, RAR[0] may be overwritten 1318 * when the other port is reset, we make a duplicate 1319 * in RAR[14] for that eventuality, this assures 1320 * the interface continues to function. 1321 */ 1322 if (sc->hw.mac.type == e1000_82571) { 1323 e1000_set_laa_state_82571(&sc->hw, true); 1324 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1325 E1000_RAR_ENTRIES - 1); 1326 } 1327 1328 1329 /* Initialize the hardware */ 1330 em_reset(ctx); 1331 em_if_update_admin_status(ctx); 1332 1333 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1334 struct tx_ring *txr = &tx_que->txr; 1335 1336 txr->tx_rs_cidx = txr->tx_rs_pidx; 1337 1338 /* Initialize the last processed descriptor to be the end of 1339 * the ring, rather than the start, so that we avoid an 1340 * off-by-one error when calculating how many descriptors are 1341 * done in the credits_update function. 1342 */ 1343 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1344 } 1345 1346 /* Setup VLAN support, basic and offload if available */ 1347 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1348 1349 /* Clear bad data from Rx FIFOs */ 1350 if (sc->hw.mac.type >= igb_mac_min) 1351 e1000_rx_fifo_flush_base(&sc->hw); 1352 1353 /* Configure for OS presence */ 1354 em_init_manageability(sc); 1355 1356 /* Prepare transmit descriptors and buffers */ 1357 em_initialize_transmit_unit(ctx); 1358 1359 /* Setup Multicast table */ 1360 em_if_multi_set(ctx); 1361 1362 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1363 em_initialize_receive_unit(ctx); 1364 1365 /* Set up VLAN support and filter */ 1366 em_setup_vlan_hw_support(ctx); 1367 1368 /* Don't lose promiscuous settings */ 1369 em_if_set_promisc(ctx, if_getflags(ifp)); 1370 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1371 1372 /* MSI-X configuration for 82574 */ 1373 if (sc->hw.mac.type == e1000_82574) { 1374 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1375 1376 tmp |= E1000_CTRL_EXT_PBA_CLR; 1377 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1378 /* Set the IVAR - interrupt vector routing. */ 1379 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1380 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1381 igb_configure_queues(sc); 1382 1383 /* this clears any pending interrupts */ 1384 E1000_READ_REG(&sc->hw, E1000_ICR); 1385 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1386 1387 /* AMT based hardware can now take control from firmware */ 1388 if (sc->has_manage && sc->has_amt) 1389 em_get_hw_control(sc); 1390 1391 /* Set Energy Efficient Ethernet */ 1392 if (sc->hw.mac.type >= igb_mac_min && 1393 sc->hw.phy.media_type == e1000_media_type_copper) { 1394 if (sc->hw.mac.type == e1000_i354) 1395 e1000_set_eee_i354(&sc->hw, true, true); 1396 else 1397 e1000_set_eee_i350(&sc->hw, true, true); 1398 } 1399} 1400 1401/********************************************************************* 1402 * 1403 * Fast Legacy/MSI Combined Interrupt Service routine 1404 * 1405 *********************************************************************/ 1406int 1407em_intr(void *arg) 1408{ 1409 struct e1000_softc *sc = arg; 1410 if_ctx_t ctx = sc->ctx; 1411 u32 reg_icr; 1412 1413 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1414 1415 /* Hot eject? */ 1416 if (reg_icr == 0xffffffff) 1417 return FILTER_STRAY; 1418 1419 /* Definitely not our interrupt. */ 1420 if (reg_icr == 0x0) 1421 return FILTER_STRAY; 1422 1423 /* 1424 * Starting with the 82571 chip, bit 31 should be used to 1425 * determine whether the interrupt belongs to us. 1426 */ 1427 if (sc->hw.mac.type >= e1000_82571 && 1428 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1429 return FILTER_STRAY; 1430 1431 /* 1432 * Only MSI-X interrupts have one-shot behavior by taking advantage 1433 * of the EIAC register. Thus, explicitly disable interrupts. This 1434 * also works around the MSI message reordering errata on certain 1435 * systems. 1436 */ 1437 IFDI_INTR_DISABLE(ctx); 1438 1439 /* Link status change */ 1440 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1441 em_handle_link(ctx); 1442 1443 if (reg_icr & E1000_ICR_RXO) 1444 sc->rx_overruns++; 1445 1446 return (FILTER_SCHEDULE_THREAD); 1447} 1448 1449static int 1450em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1451{ 1452 struct e1000_softc *sc = iflib_get_softc(ctx); 1453 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1454 1455 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1456 return (0); 1457} 1458 1459static int 1460em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1461{ 1462 struct e1000_softc *sc = iflib_get_softc(ctx); 1463 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1464 1465 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1466 return (0); 1467} 1468 1469static int 1470igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1471{ 1472 struct e1000_softc *sc = iflib_get_softc(ctx); 1473 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1474 1475 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1476 return (0); 1477} 1478 1479static int 1480igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1481{ 1482 struct e1000_softc *sc = iflib_get_softc(ctx); 1483 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1484 1485 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1486 return (0); 1487} 1488 1489/********************************************************************* 1490 * 1491 * MSI-X RX Interrupt Service routine 1492 * 1493 **********************************************************************/ 1494static int 1495em_msix_que(void *arg) 1496{ 1497 struct em_rx_queue *que = arg; 1498 1499 ++que->irqs; 1500 1501 return (FILTER_SCHEDULE_THREAD); 1502} 1503 1504/********************************************************************* 1505 * 1506 * MSI-X Link Fast Interrupt Service routine 1507 * 1508 **********************************************************************/ 1509static int 1510em_msix_link(void *arg) 1511{ 1512 struct e1000_softc *sc = arg; 1513 u32 reg_icr; 1514 1515 ++sc->link_irq; 1516 MPASS(sc->hw.back != NULL); 1517 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1518 1519 if (reg_icr & E1000_ICR_RXO) 1520 sc->rx_overruns++; 1521 1522 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1523 em_handle_link(sc->ctx); 1524 1525 /* Re-arm unconditionally */ 1526 if (sc->hw.mac.type >= igb_mac_min) { 1527 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1528 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1529 } else if (sc->hw.mac.type == e1000_82574) { 1530 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1531 E1000_IMS_OTHER); 1532 /* 1533 * Because we must read the ICR for this interrupt it may 1534 * clear other causes using autoclear, for this reason we 1535 * simply create a soft interrupt for all these vectors. 1536 */ 1537 if (reg_icr) 1538 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1539 } else 1540 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1541 1542 return (FILTER_HANDLED); 1543} 1544 1545static void 1546em_handle_link(void *context) 1547{ 1548 if_ctx_t ctx = context; 1549 struct e1000_softc *sc = iflib_get_softc(ctx); 1550 1551 sc->hw.mac.get_link_status = 1; 1552 iflib_admin_intr_deferred(ctx); 1553} 1554 1555/********************************************************************* 1556 * 1557 * Media Ioctl callback 1558 * 1559 * This routine is called whenever the user queries the status of 1560 * the interface using ifconfig. 1561 * 1562 **********************************************************************/ 1563static void 1564em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1565{ 1566 struct e1000_softc *sc = iflib_get_softc(ctx); 1567 u_char fiber_type = IFM_1000_SX; 1568 1569 INIT_DEBUGOUT("em_if_media_status: begin"); 1570 1571 iflib_admin_intr_deferred(ctx); 1572 1573 ifmr->ifm_status = IFM_AVALID; 1574 ifmr->ifm_active = IFM_ETHER; 1575 1576 if (!sc->link_active) { 1577 return; 1578 } 1579 1580 ifmr->ifm_status |= IFM_ACTIVE; 1581 1582 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1583 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1584 if (sc->hw.mac.type == e1000_82545) 1585 fiber_type = IFM_1000_LX; 1586 ifmr->ifm_active |= fiber_type | IFM_FDX; 1587 } else { 1588 switch (sc->link_speed) { 1589 case 10: 1590 ifmr->ifm_active |= IFM_10_T; 1591 break; 1592 case 100: 1593 ifmr->ifm_active |= IFM_100_TX; 1594 break; 1595 case 1000: 1596 ifmr->ifm_active |= IFM_1000_T; 1597 break; 1598 } 1599 if (sc->link_duplex == FULL_DUPLEX) 1600 ifmr->ifm_active |= IFM_FDX; 1601 else 1602 ifmr->ifm_active |= IFM_HDX; 1603 } 1604} 1605 1606/********************************************************************* 1607 * 1608 * Media Ioctl callback 1609 * 1610 * This routine is called when the user changes speed/duplex using 1611 * media/mediopt option with ifconfig. 1612 * 1613 **********************************************************************/ 1614static int 1615em_if_media_change(if_ctx_t ctx) 1616{ 1617 struct e1000_softc *sc = iflib_get_softc(ctx); 1618 struct ifmedia *ifm = iflib_get_media(ctx); 1619 1620 INIT_DEBUGOUT("em_if_media_change: begin"); 1621 1622 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1623 return (EINVAL); 1624 1625 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1626 case IFM_AUTO: 1627 sc->hw.mac.autoneg = DO_AUTO_NEG; 1628 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1629 break; 1630 case IFM_1000_LX: 1631 case IFM_1000_SX: 1632 case IFM_1000_T: 1633 sc->hw.mac.autoneg = DO_AUTO_NEG; 1634 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1635 break; 1636 case IFM_100_TX: 1637 sc->hw.mac.autoneg = false; 1638 sc->hw.phy.autoneg_advertised = 0; 1639 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1640 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1641 else 1642 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1643 break; 1644 case IFM_10_T: 1645 sc->hw.mac.autoneg = false; 1646 sc->hw.phy.autoneg_advertised = 0; 1647 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1648 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1649 else 1650 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1651 break; 1652 default: 1653 device_printf(sc->dev, "Unsupported media type\n"); 1654 } 1655 1656 em_if_init(ctx); 1657 1658 return (0); 1659} 1660 1661static int 1662em_if_set_promisc(if_ctx_t ctx, int flags) 1663{ 1664 struct e1000_softc *sc = iflib_get_softc(ctx); 1665 struct ifnet *ifp = iflib_get_ifp(ctx); 1666 u32 reg_rctl; 1667 int mcnt = 0; 1668 1669 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1670 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1671 if (flags & IFF_ALLMULTI) 1672 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1673 else 1674 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1675 1676 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1677 reg_rctl &= (~E1000_RCTL_MPE); 1678 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1679 1680 if (flags & IFF_PROMISC) { 1681 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1682 em_if_vlan_filter_disable(sc); 1683 /* Turn this on if you want to see bad packets */ 1684 if (em_debug_sbp) 1685 reg_rctl |= E1000_RCTL_SBP; 1686 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1687 } else { 1688 if (flags & IFF_ALLMULTI) { 1689 reg_rctl |= E1000_RCTL_MPE; 1690 reg_rctl &= ~E1000_RCTL_UPE; 1691 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1692 } 1693 if (em_if_vlan_filter_used(ctx)) 1694 em_if_vlan_filter_enable(sc); 1695 } 1696 return (0); 1697} 1698 1699static u_int 1700em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1701{ 1702 u8 *mta = arg; 1703 1704 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1705 return (0); 1706 1707 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1708 1709 return (1); 1710} 1711 1712/********************************************************************* 1713 * Multicast Update 1714 * 1715 * This routine is called whenever multicast address list is updated. 1716 * 1717 **********************************************************************/ 1718static void 1719em_if_multi_set(if_ctx_t ctx) 1720{ 1721 struct e1000_softc *sc = iflib_get_softc(ctx); 1722 struct ifnet *ifp = iflib_get_ifp(ctx); 1723 u8 *mta; /* Multicast array memory */ 1724 u32 reg_rctl = 0; 1725 int mcnt = 0; 1726 1727 IOCTL_DEBUGOUT("em_set_multi: begin"); 1728 1729 mta = sc->mta; 1730 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1731 1732 if (sc->hw.mac.type == e1000_82542 && 1733 sc->hw.revision_id == E1000_REVISION_2) { 1734 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1735 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1736 e1000_pci_clear_mwi(&sc->hw); 1737 reg_rctl |= E1000_RCTL_RST; 1738 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1739 msec_delay(5); 1740 } 1741 1742 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1743 1744 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1745 1746 if (if_getflags(ifp) & IFF_PROMISC) 1747 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1748 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1749 if_getflags(ifp) & IFF_ALLMULTI) { 1750 reg_rctl |= E1000_RCTL_MPE; 1751 reg_rctl &= ~E1000_RCTL_UPE; 1752 } else 1753 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1754 1755 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1756 1757 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1758 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1759 1760 if (sc->hw.mac.type == e1000_82542 && 1761 sc->hw.revision_id == E1000_REVISION_2) { 1762 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1763 reg_rctl &= ~E1000_RCTL_RST; 1764 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1765 msec_delay(5); 1766 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1767 e1000_pci_set_mwi(&sc->hw); 1768 } 1769} 1770 1771/********************************************************************* 1772 * Timer routine 1773 * 1774 * This routine schedules em_if_update_admin_status() to check for 1775 * link status and to gather statistics as well as to perform some 1776 * controller-specific hardware patting. 1777 * 1778 **********************************************************************/ 1779static void 1780em_if_timer(if_ctx_t ctx, uint16_t qid) 1781{ 1782 1783 if (qid != 0) 1784 return; 1785 1786 iflib_admin_intr_deferred(ctx); 1787} 1788 1789static void 1790em_if_update_admin_status(if_ctx_t ctx) 1791{ 1792 struct e1000_softc *sc = iflib_get_softc(ctx); 1793 struct e1000_hw *hw = &sc->hw; 1794 device_t dev = iflib_get_dev(ctx); 1795 u32 link_check, thstat, ctrl; 1796 1797 link_check = thstat = ctrl = 0; 1798 /* Get the cached link value or read phy for real */ 1799 switch (hw->phy.media_type) { 1800 case e1000_media_type_copper: 1801 if (hw->mac.get_link_status) { 1802 if (hw->mac.type == e1000_pch_spt) 1803 msec_delay(50); 1804 /* Do the work to read phy */ 1805 e1000_check_for_link(hw); 1806 link_check = !hw->mac.get_link_status; 1807 if (link_check) /* ESB2 fix */ 1808 e1000_cfg_on_link_up(hw); 1809 } else { 1810 link_check = true; 1811 } 1812 break; 1813 case e1000_media_type_fiber: 1814 e1000_check_for_link(hw); 1815 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1816 E1000_STATUS_LU); 1817 break; 1818 case e1000_media_type_internal_serdes: 1819 e1000_check_for_link(hw); 1820 link_check = hw->mac.serdes_has_link; 1821 break; 1822 /* VF device is type_unknown */ 1823 case e1000_media_type_unknown: 1824 e1000_check_for_link(hw); 1825 link_check = !hw->mac.get_link_status; 1826 /* FALLTHROUGH */ 1827 default: 1828 break; 1829 } 1830 1831 /* Check for thermal downshift or shutdown */ 1832 if (hw->mac.type == e1000_i350) { 1833 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1834 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1835 } 1836 1837 /* Now check for a transition */ 1838 if (link_check && (sc->link_active == 0)) { 1839 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1840 &sc->link_duplex); 1841 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1842 if ((sc->link_speed != SPEED_1000) && 1843 ((hw->mac.type == e1000_82571) || 1844 (hw->mac.type == e1000_82572))) { 1845 int tarc0; 1846 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1847 tarc0 &= ~TARC_SPEED_MODE_BIT; 1848 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1849 } 1850 if (bootverbose) 1851 device_printf(dev, "Link is up %d Mbps %s\n", 1852 sc->link_speed, 1853 ((sc->link_duplex == FULL_DUPLEX) ? 1854 "Full Duplex" : "Half Duplex")); 1855 sc->link_active = 1; 1856 sc->smartspeed = 0; 1857 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1858 E1000_CTRL_EXT_LINK_MODE_GMII && 1859 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1860 device_printf(dev, "Link: thermal downshift\n"); 1861 /* Delay Link Up for Phy update */ 1862 if (((hw->mac.type == e1000_i210) || 1863 (hw->mac.type == e1000_i211)) && 1864 (hw->phy.id == I210_I_PHY_ID)) 1865 msec_delay(I210_LINK_DELAY); 1866 /* Reset if the media type changed. */ 1867 if (hw->dev_spec._82575.media_changed && 1868 hw->mac.type >= igb_mac_min) { 1869 hw->dev_spec._82575.media_changed = false; 1870 sc->flags |= IGB_MEDIA_RESET; 1871 em_reset(ctx); 1872 } 1873 iflib_link_state_change(ctx, LINK_STATE_UP, 1874 IF_Mbps(sc->link_speed)); 1875 } else if (!link_check && (sc->link_active == 1)) { 1876 sc->link_speed = 0; 1877 sc->link_duplex = 0; 1878 sc->link_active = 0; 1879 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1880 } 1881 em_update_stats_counters(sc); 1882 1883 /* Reset LAA into RAR[0] on 82571 */ 1884 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1885 e1000_rar_set(hw, hw->mac.addr, 0); 1886 1887 if (hw->mac.type < em_mac_min) 1888 lem_smartspeed(sc); 1889} 1890 1891static void 1892em_if_watchdog_reset(if_ctx_t ctx) 1893{ 1894 struct e1000_softc *sc = iflib_get_softc(ctx); 1895 1896 /* 1897 * Just count the event; iflib(4) will already trigger a 1898 * sufficient reset of the controller. 1899 */ 1900 sc->watchdog_events++; 1901} 1902 1903/********************************************************************* 1904 * 1905 * This routine disables all traffic on the adapter by issuing a 1906 * global reset on the MAC. 1907 * 1908 **********************************************************************/ 1909static void 1910em_if_stop(if_ctx_t ctx) 1911{ 1912 struct e1000_softc *sc = iflib_get_softc(ctx); 1913 1914 INIT_DEBUGOUT("em_if_stop: begin"); 1915 1916 e1000_reset_hw(&sc->hw); 1917 if (sc->hw.mac.type >= e1000_82544) 1918 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1919 1920 e1000_led_off(&sc->hw); 1921 e1000_cleanup_led(&sc->hw); 1922} 1923 1924/********************************************************************* 1925 * 1926 * Determine hardware revision. 1927 * 1928 **********************************************************************/ 1929static void 1930em_identify_hardware(if_ctx_t ctx) 1931{ 1932 device_t dev = iflib_get_dev(ctx); 1933 struct e1000_softc *sc = iflib_get_softc(ctx); 1934 1935 /* Make sure our PCI config space has the necessary stuff set */ 1936 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1937 1938 /* Save off the information about this board */ 1939 sc->hw.vendor_id = pci_get_vendor(dev); 1940 sc->hw.device_id = pci_get_device(dev); 1941 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1942 sc->hw.subsystem_vendor_id = 1943 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1944 sc->hw.subsystem_device_id = 1945 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1946 1947 /* Do Shared Code Init and Setup */ 1948 if (e1000_set_mac_type(&sc->hw)) { 1949 device_printf(dev, "Setup init failure\n"); 1950 return; 1951 } 1952 1953 /* Are we a VF device? */ 1954 if ((sc->hw.mac.type == e1000_vfadapt) || 1955 (sc->hw.mac.type == e1000_vfadapt_i350)) 1956 sc->vf_ifp = 1; 1957 else 1958 sc->vf_ifp = 0; 1959} 1960 1961static int 1962em_allocate_pci_resources(if_ctx_t ctx) 1963{ 1964 struct e1000_softc *sc = iflib_get_softc(ctx); 1965 device_t dev = iflib_get_dev(ctx); 1966 int rid, val; 1967 1968 rid = PCIR_BAR(0); 1969 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1970 &rid, RF_ACTIVE); 1971 if (sc->memory == NULL) { 1972 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1973 return (ENXIO); 1974 } 1975 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 1976 sc->osdep.mem_bus_space_handle = 1977 rman_get_bushandle(sc->memory); 1978 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 1979 1980 /* Only older adapters use IO mapping */ 1981 if (sc->hw.mac.type < em_mac_min && 1982 sc->hw.mac.type > e1000_82543) { 1983 /* Figure our where our IO BAR is ? */ 1984 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1985 val = pci_read_config(dev, rid, 4); 1986 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1987 break; 1988 } 1989 rid += 4; 1990 /* check for 64bit BAR */ 1991 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1992 rid += 4; 1993 } 1994 if (rid >= PCIR_CIS) { 1995 device_printf(dev, "Unable to locate IO BAR\n"); 1996 return (ENXIO); 1997 } 1998 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1999 &rid, RF_ACTIVE); 2000 if (sc->ioport == NULL) { 2001 device_printf(dev, "Unable to allocate bus resource: " 2002 "ioport\n"); 2003 return (ENXIO); 2004 } 2005 sc->hw.io_base = 0; 2006 sc->osdep.io_bus_space_tag = 2007 rman_get_bustag(sc->ioport); 2008 sc->osdep.io_bus_space_handle = 2009 rman_get_bushandle(sc->ioport); 2010 } 2011 2012 sc->hw.back = &sc->osdep; 2013 2014 return (0); 2015} 2016 2017/********************************************************************* 2018 * 2019 * Set up the MSI-X Interrupt handlers 2020 * 2021 **********************************************************************/ 2022static int 2023em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2024{ 2025 struct e1000_softc *sc = iflib_get_softc(ctx); 2026 struct em_rx_queue *rx_que = sc->rx_queues; 2027 struct em_tx_queue *tx_que = sc->tx_queues; 2028 int error, rid, i, vector = 0, rx_vectors; 2029 char buf[16]; 2030 2031 /* First set up ring resources */ 2032 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2033 rid = vector + 1; 2034 snprintf(buf, sizeof(buf), "rxq%d", i); 2035 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2036 if (error) { 2037 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2038 sc->rx_num_queues = i + 1; 2039 goto fail; 2040 } 2041 2042 rx_que->msix = vector; 2043 2044 /* 2045 * Set the bit to enable interrupt 2046 * in E1000_IMS -- bits 20 and 21 2047 * are for RX0 and RX1, note this has 2048 * NOTHING to do with the MSI-X vector 2049 */ 2050 if (sc->hw.mac.type == e1000_82574) { 2051 rx_que->eims = 1 << (20 + i); 2052 sc->ims |= rx_que->eims; 2053 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2054 } else if (sc->hw.mac.type == e1000_82575) 2055 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2056 else 2057 rx_que->eims = 1 << vector; 2058 } 2059 rx_vectors = vector; 2060 2061 vector = 0; 2062 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2063 snprintf(buf, sizeof(buf), "txq%d", i); 2064 tx_que = &sc->tx_queues[i]; 2065 iflib_softirq_alloc_generic(ctx, 2066 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2067 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2068 2069 tx_que->msix = (vector % sc->rx_num_queues); 2070 2071 /* 2072 * Set the bit to enable interrupt 2073 * in E1000_IMS -- bits 22 and 23 2074 * are for TX0 and TX1, note this has 2075 * NOTHING to do with the MSI-X vector 2076 */ 2077 if (sc->hw.mac.type == e1000_82574) { 2078 tx_que->eims = 1 << (22 + i); 2079 sc->ims |= tx_que->eims; 2080 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2081 } else if (sc->hw.mac.type == e1000_82575) { 2082 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2083 } else { 2084 tx_que->eims = 1 << i; 2085 } 2086 } 2087 2088 /* Link interrupt */ 2089 rid = rx_vectors + 1; 2090 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2091 2092 if (error) { 2093 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2094 goto fail; 2095 } 2096 sc->linkvec = rx_vectors; 2097 if (sc->hw.mac.type < igb_mac_min) { 2098 sc->ivars |= (8 | rx_vectors) << 16; 2099 sc->ivars |= 0x80000000; 2100 /* Enable the "Other" interrupt type for link status change */ 2101 sc->ims |= E1000_IMS_OTHER; 2102 } 2103 2104 return (0); 2105fail: 2106 iflib_irq_free(ctx, &sc->irq); 2107 rx_que = sc->rx_queues; 2108 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2109 iflib_irq_free(ctx, &rx_que->que_irq); 2110 return (error); 2111} 2112 2113static void 2114igb_configure_queues(struct e1000_softc *sc) 2115{ 2116 struct e1000_hw *hw = &sc->hw; 2117 struct em_rx_queue *rx_que; 2118 struct em_tx_queue *tx_que; 2119 u32 tmp, ivar = 0, newitr = 0; 2120 2121 /* First turn on RSS capability */ 2122 if (hw->mac.type != e1000_82575) 2123 E1000_WRITE_REG(hw, E1000_GPIE, 2124 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2125 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2126 2127 /* Turn on MSI-X */ 2128 switch (hw->mac.type) { 2129 case e1000_82580: 2130 case e1000_i350: 2131 case e1000_i354: 2132 case e1000_i210: 2133 case e1000_i211: 2134 case e1000_vfadapt: 2135 case e1000_vfadapt_i350: 2136 /* RX entries */ 2137 for (int i = 0; i < sc->rx_num_queues; i++) { 2138 u32 index = i >> 1; 2139 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2140 rx_que = &sc->rx_queues[i]; 2141 if (i & 1) { 2142 ivar &= 0xFF00FFFF; 2143 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2144 } else { 2145 ivar &= 0xFFFFFF00; 2146 ivar |= rx_que->msix | E1000_IVAR_VALID; 2147 } 2148 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2149 } 2150 /* TX entries */ 2151 for (int i = 0; i < sc->tx_num_queues; i++) { 2152 u32 index = i >> 1; 2153 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2154 tx_que = &sc->tx_queues[i]; 2155 if (i & 1) { 2156 ivar &= 0x00FFFFFF; 2157 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2158 } else { 2159 ivar &= 0xFFFF00FF; 2160 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2161 } 2162 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2163 sc->que_mask |= tx_que->eims; 2164 } 2165 2166 /* And for the link interrupt */ 2167 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2168 sc->link_mask = 1 << sc->linkvec; 2169 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2170 break; 2171 case e1000_82576: 2172 /* RX entries */ 2173 for (int i = 0; i < sc->rx_num_queues; i++) { 2174 u32 index = i & 0x7; /* Each IVAR has two entries */ 2175 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2176 rx_que = &sc->rx_queues[i]; 2177 if (i < 8) { 2178 ivar &= 0xFFFFFF00; 2179 ivar |= rx_que->msix | E1000_IVAR_VALID; 2180 } else { 2181 ivar &= 0xFF00FFFF; 2182 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2183 } 2184 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2185 sc->que_mask |= rx_que->eims; 2186 } 2187 /* TX entries */ 2188 for (int i = 0; i < sc->tx_num_queues; i++) { 2189 u32 index = i & 0x7; /* Each IVAR has two entries */ 2190 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2191 tx_que = &sc->tx_queues[i]; 2192 if (i < 8) { 2193 ivar &= 0xFFFF00FF; 2194 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2195 } else { 2196 ivar &= 0x00FFFFFF; 2197 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2198 } 2199 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2200 sc->que_mask |= tx_que->eims; 2201 } 2202 2203 /* And for the link interrupt */ 2204 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2205 sc->link_mask = 1 << sc->linkvec; 2206 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2207 break; 2208 2209 case e1000_82575: 2210 /* enable MSI-X support*/ 2211 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2212 tmp |= E1000_CTRL_EXT_PBA_CLR; 2213 /* Auto-Mask interrupts upon ICR read. */ 2214 tmp |= E1000_CTRL_EXT_EIAME; 2215 tmp |= E1000_CTRL_EXT_IRCA; 2216 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2217 2218 /* Queues */ 2219 for (int i = 0; i < sc->rx_num_queues; i++) { 2220 rx_que = &sc->rx_queues[i]; 2221 tmp = E1000_EICR_RX_QUEUE0 << i; 2222 tmp |= E1000_EICR_TX_QUEUE0 << i; 2223 rx_que->eims = tmp; 2224 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2225 i, rx_que->eims); 2226 sc->que_mask |= rx_que->eims; 2227 } 2228 2229 /* Link */ 2230 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2231 E1000_EIMS_OTHER); 2232 sc->link_mask |= E1000_EIMS_OTHER; 2233 default: 2234 break; 2235 } 2236 2237 /* Set the starting interrupt rate */ 2238 if (em_max_interrupt_rate > 0) 2239 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2240 2241 if (hw->mac.type == e1000_82575) 2242 newitr |= newitr << 16; 2243 else 2244 newitr |= E1000_EITR_CNT_IGNR; 2245 2246 for (int i = 0; i < sc->rx_num_queues; i++) { 2247 rx_que = &sc->rx_queues[i]; 2248 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2249 } 2250 2251 return; 2252} 2253 2254static void 2255em_free_pci_resources(if_ctx_t ctx) 2256{ 2257 struct e1000_softc *sc = iflib_get_softc(ctx); 2258 struct em_rx_queue *que = sc->rx_queues; 2259 device_t dev = iflib_get_dev(ctx); 2260 2261 /* Release all MSI-X queue resources */ 2262 if (sc->intr_type == IFLIB_INTR_MSIX) 2263 iflib_irq_free(ctx, &sc->irq); 2264 2265 if (que != NULL) { 2266 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2267 iflib_irq_free(ctx, &que->que_irq); 2268 } 2269 } 2270 2271 if (sc->memory != NULL) { 2272 bus_release_resource(dev, SYS_RES_MEMORY, 2273 rman_get_rid(sc->memory), sc->memory); 2274 sc->memory = NULL; 2275 } 2276 2277 if (sc->flash != NULL) { 2278 bus_release_resource(dev, SYS_RES_MEMORY, 2279 rman_get_rid(sc->flash), sc->flash); 2280 sc->flash = NULL; 2281 } 2282 2283 if (sc->ioport != NULL) { 2284 bus_release_resource(dev, SYS_RES_IOPORT, 2285 rman_get_rid(sc->ioport), sc->ioport); 2286 sc->ioport = NULL; 2287 } 2288} 2289 2290/* Set up MSI or MSI-X */ 2291static int 2292em_setup_msix(if_ctx_t ctx) 2293{ 2294 struct e1000_softc *sc = iflib_get_softc(ctx); 2295 2296 if (sc->hw.mac.type == e1000_82574) { 2297 em_enable_vectors_82574(ctx); 2298 } 2299 return (0); 2300} 2301 2302/********************************************************************* 2303 * 2304 * Workaround for SmartSpeed on 82541 and 82547 controllers 2305 * 2306 **********************************************************************/ 2307static void 2308lem_smartspeed(struct e1000_softc *sc) 2309{ 2310 u16 phy_tmp; 2311 2312 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2313 sc->hw.mac.autoneg == 0 || 2314 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2315 return; 2316 2317 if (sc->smartspeed == 0) { 2318 /* If Master/Slave config fault is asserted twice, 2319 * we assume back-to-back */ 2320 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2321 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2322 return; 2323 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2324 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2325 e1000_read_phy_reg(&sc->hw, 2326 PHY_1000T_CTRL, &phy_tmp); 2327 if(phy_tmp & CR_1000T_MS_ENABLE) { 2328 phy_tmp &= ~CR_1000T_MS_ENABLE; 2329 e1000_write_phy_reg(&sc->hw, 2330 PHY_1000T_CTRL, phy_tmp); 2331 sc->smartspeed++; 2332 if(sc->hw.mac.autoneg && 2333 !e1000_copper_link_autoneg(&sc->hw) && 2334 !e1000_read_phy_reg(&sc->hw, 2335 PHY_CONTROL, &phy_tmp)) { 2336 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2337 MII_CR_RESTART_AUTO_NEG); 2338 e1000_write_phy_reg(&sc->hw, 2339 PHY_CONTROL, phy_tmp); 2340 } 2341 } 2342 } 2343 return; 2344 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2345 /* If still no link, perhaps using 2/3 pair cable */ 2346 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2347 phy_tmp |= CR_1000T_MS_ENABLE; 2348 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2349 if(sc->hw.mac.autoneg && 2350 !e1000_copper_link_autoneg(&sc->hw) && 2351 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2352 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2353 MII_CR_RESTART_AUTO_NEG); 2354 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2355 } 2356 } 2357 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2358 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2359 sc->smartspeed = 0; 2360} 2361 2362/********************************************************************* 2363 * 2364 * Initialize the DMA Coalescing feature 2365 * 2366 **********************************************************************/ 2367static void 2368igb_init_dmac(struct e1000_softc *sc, u32 pba) 2369{ 2370 device_t dev = sc->dev; 2371 struct e1000_hw *hw = &sc->hw; 2372 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2373 u16 hwm; 2374 u16 max_frame_size; 2375 2376 if (hw->mac.type == e1000_i211) 2377 return; 2378 2379 max_frame_size = sc->shared->isc_max_frame_size; 2380 if (hw->mac.type > e1000_82580) { 2381 2382 if (sc->dmac == 0) { /* Disabling it */ 2383 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2384 return; 2385 } else 2386 device_printf(dev, "DMA Coalescing enabled\n"); 2387 2388 /* Set starting threshold */ 2389 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2390 2391 hwm = 64 * pba - max_frame_size / 16; 2392 if (hwm < 64 * (pba - 6)) 2393 hwm = 64 * (pba - 6); 2394 reg = E1000_READ_REG(hw, E1000_FCRTC); 2395 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2396 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2397 & E1000_FCRTC_RTH_COAL_MASK); 2398 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2399 2400 2401 dmac = pba - max_frame_size / 512; 2402 if (dmac < pba - 10) 2403 dmac = pba - 10; 2404 reg = E1000_READ_REG(hw, E1000_DMACR); 2405 reg &= ~E1000_DMACR_DMACTHR_MASK; 2406 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2407 & E1000_DMACR_DMACTHR_MASK); 2408 2409 /* transition to L0x or L1 if available..*/ 2410 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2411 2412 /* Check if status is 2.5Gb backplane connection 2413 * before configuration of watchdog timer, which is 2414 * in msec values in 12.8usec intervals 2415 * watchdog timer= msec values in 32usec intervals 2416 * for non 2.5Gb connection 2417 */ 2418 if (hw->mac.type == e1000_i354) { 2419 int status = E1000_READ_REG(hw, E1000_STATUS); 2420 if ((status & E1000_STATUS_2P5_SKU) && 2421 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2422 reg |= ((sc->dmac * 5) >> 6); 2423 else 2424 reg |= (sc->dmac >> 5); 2425 } else { 2426 reg |= (sc->dmac >> 5); 2427 } 2428 2429 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2430 2431 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2432 2433 /* Set the interval before transition */ 2434 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2435 if (hw->mac.type == e1000_i350) 2436 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2437 /* 2438 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2439 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2440 */ 2441 if (hw->mac.type == e1000_i354) { 2442 int status = E1000_READ_REG(hw, E1000_STATUS); 2443 if ((status & E1000_STATUS_2P5_SKU) && 2444 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2445 reg |= 0xA; 2446 else 2447 reg |= 0x4; 2448 } else { 2449 reg |= 0x4; 2450 } 2451 2452 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2453 2454 /* free space in tx packet buffer to wake from DMA coal */ 2455 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2456 (2 * max_frame_size)) >> 6); 2457 2458 /* make low power state decision controlled by DMA coal */ 2459 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2460 reg &= ~E1000_PCIEMISC_LX_DECISION; 2461 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2462 2463 } else if (hw->mac.type == e1000_82580) { 2464 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2465 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2466 reg & ~E1000_PCIEMISC_LX_DECISION); 2467 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2468 } 2469} 2470 2471/********************************************************************* 2472 * 2473 * Initialize the hardware to a configuration as specified by the 2474 * sc structure. 2475 * 2476 **********************************************************************/ 2477static void 2478em_reset(if_ctx_t ctx) 2479{ 2480 device_t dev = iflib_get_dev(ctx); 2481 struct e1000_softc *sc = iflib_get_softc(ctx); 2482 struct ifnet *ifp = iflib_get_ifp(ctx); 2483 struct e1000_hw *hw = &sc->hw; 2484 u16 rx_buffer_size; 2485 u32 pba; 2486 2487 INIT_DEBUGOUT("em_reset: begin"); 2488 /* Let the firmware know the OS is in control */ 2489 em_get_hw_control(sc); 2490 2491 /* Set up smart power down as default off on newer adapters. */ 2492 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2493 hw->mac.type == e1000_82572)) { 2494 u16 phy_tmp = 0; 2495 2496 /* Speed up time to link by disabling smart power down. */ 2497 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2498 phy_tmp &= ~IGP02E1000_PM_SPD; 2499 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2500 } 2501 2502 /* 2503 * Packet Buffer Allocation (PBA) 2504 * Writing PBA sets the receive portion of the buffer 2505 * the remainder is used for the transmit buffer. 2506 */ 2507 switch (hw->mac.type) { 2508 /* 82547: Total Packet Buffer is 40K */ 2509 case e1000_82547: 2510 case e1000_82547_rev_2: 2511 if (hw->mac.max_frame_size > 8192) 2512 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2513 else 2514 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2515 break; 2516 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2517 case e1000_82571: 2518 case e1000_82572: 2519 case e1000_80003es2lan: 2520 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2521 break; 2522 /* 82573: Total Packet Buffer is 32K */ 2523 case e1000_82573: 2524 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2525 break; 2526 case e1000_82574: 2527 case e1000_82583: 2528 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2529 break; 2530 case e1000_ich8lan: 2531 pba = E1000_PBA_8K; 2532 break; 2533 case e1000_ich9lan: 2534 case e1000_ich10lan: 2535 /* Boost Receive side for jumbo frames */ 2536 if (hw->mac.max_frame_size > 4096) 2537 pba = E1000_PBA_14K; 2538 else 2539 pba = E1000_PBA_10K; 2540 break; 2541 case e1000_pchlan: 2542 case e1000_pch2lan: 2543 case e1000_pch_lpt: 2544 case e1000_pch_spt: 2545 case e1000_pch_cnp: 2546 case e1000_pch_tgp: 2547 case e1000_pch_adp: 2548 case e1000_pch_mtp: 2549 pba = E1000_PBA_26K; 2550 break; 2551 case e1000_82575: 2552 pba = E1000_PBA_32K; 2553 break; 2554 case e1000_82576: 2555 case e1000_vfadapt: 2556 pba = E1000_READ_REG(hw, E1000_RXPBS); 2557 pba &= E1000_RXPBS_SIZE_MASK_82576; 2558 break; 2559 case e1000_82580: 2560 case e1000_i350: 2561 case e1000_i354: 2562 case e1000_vfadapt_i350: 2563 pba = E1000_READ_REG(hw, E1000_RXPBS); 2564 pba = e1000_rxpbs_adjust_82580(pba); 2565 break; 2566 case e1000_i210: 2567 case e1000_i211: 2568 pba = E1000_PBA_34K; 2569 break; 2570 default: 2571 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2572 if (hw->mac.max_frame_size > 8192) 2573 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2574 else 2575 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2576 } 2577 2578 /* Special needs in case of Jumbo frames */ 2579 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2580 u32 tx_space, min_tx, min_rx; 2581 pba = E1000_READ_REG(hw, E1000_PBA); 2582 tx_space = pba >> 16; 2583 pba &= 0xffff; 2584 min_tx = (hw->mac.max_frame_size + 2585 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2586 min_tx = roundup2(min_tx, 1024); 2587 min_tx >>= 10; 2588 min_rx = hw->mac.max_frame_size; 2589 min_rx = roundup2(min_rx, 1024); 2590 min_rx >>= 10; 2591 if (tx_space < min_tx && 2592 ((min_tx - tx_space) < pba)) { 2593 pba = pba - (min_tx - tx_space); 2594 /* 2595 * if short on rx space, rx wins 2596 * and must trump tx adjustment 2597 */ 2598 if (pba < min_rx) 2599 pba = min_rx; 2600 } 2601 E1000_WRITE_REG(hw, E1000_PBA, pba); 2602 } 2603 2604 if (hw->mac.type < igb_mac_min) 2605 E1000_WRITE_REG(hw, E1000_PBA, pba); 2606 2607 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2608 2609 /* 2610 * These parameters control the automatic generation (Tx) and 2611 * response (Rx) to Ethernet PAUSE frames. 2612 * - High water mark should allow for at least two frames to be 2613 * received after sending an XOFF. 2614 * - Low water mark works best when it is very near the high water mark. 2615 * This allows the receiver to restart by sending XON when it has 2616 * drained a bit. Here we use an arbitrary value of 1500 which will 2617 * restart after one full frame is pulled from the buffer. There 2618 * could be several smaller frames in the buffer and if so they will 2619 * not trigger the XON until their total number reduces the buffer 2620 * by 1500. 2621 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2622 */ 2623 rx_buffer_size = (pba & 0xffff) << 10; 2624 hw->fc.high_water = rx_buffer_size - 2625 roundup2(hw->mac.max_frame_size, 1024); 2626 hw->fc.low_water = hw->fc.high_water - 1500; 2627 2628 if (sc->fc) /* locally set flow control value? */ 2629 hw->fc.requested_mode = sc->fc; 2630 else 2631 hw->fc.requested_mode = e1000_fc_full; 2632 2633 if (hw->mac.type == e1000_80003es2lan) 2634 hw->fc.pause_time = 0xFFFF; 2635 else 2636 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2637 2638 hw->fc.send_xon = true; 2639 2640 /* Device specific overrides/settings */ 2641 switch (hw->mac.type) { 2642 case e1000_pchlan: 2643 /* Workaround: no TX flow ctrl for PCH */ 2644 hw->fc.requested_mode = e1000_fc_rx_pause; 2645 hw->fc.pause_time = 0xFFFF; /* override */ 2646 if (if_getmtu(ifp) > ETHERMTU) { 2647 hw->fc.high_water = 0x3500; 2648 hw->fc.low_water = 0x1500; 2649 } else { 2650 hw->fc.high_water = 0x5000; 2651 hw->fc.low_water = 0x3000; 2652 } 2653 hw->fc.refresh_time = 0x1000; 2654 break; 2655 case e1000_pch2lan: 2656 case e1000_pch_lpt: 2657 case e1000_pch_spt: 2658 case e1000_pch_cnp: 2659 case e1000_pch_tgp: 2660 case e1000_pch_adp: 2661 case e1000_pch_mtp: 2662 hw->fc.high_water = 0x5C20; 2663 hw->fc.low_water = 0x5048; 2664 hw->fc.pause_time = 0x0650; 2665 hw->fc.refresh_time = 0x0400; 2666 /* Jumbos need adjusted PBA */ 2667 if (if_getmtu(ifp) > ETHERMTU) 2668 E1000_WRITE_REG(hw, E1000_PBA, 12); 2669 else 2670 E1000_WRITE_REG(hw, E1000_PBA, 26); 2671 break; 2672 case e1000_82575: 2673 case e1000_82576: 2674 /* 8-byte granularity */ 2675 hw->fc.low_water = hw->fc.high_water - 8; 2676 break; 2677 case e1000_82580: 2678 case e1000_i350: 2679 case e1000_i354: 2680 case e1000_i210: 2681 case e1000_i211: 2682 case e1000_vfadapt: 2683 case e1000_vfadapt_i350: 2684 /* 16-byte granularity */ 2685 hw->fc.low_water = hw->fc.high_water - 16; 2686 break; 2687 case e1000_ich9lan: 2688 case e1000_ich10lan: 2689 if (if_getmtu(ifp) > ETHERMTU) { 2690 hw->fc.high_water = 0x2800; 2691 hw->fc.low_water = hw->fc.high_water - 8; 2692 break; 2693 } 2694 /* FALLTHROUGH */ 2695 default: 2696 if (hw->mac.type == e1000_80003es2lan) 2697 hw->fc.pause_time = 0xFFFF; 2698 break; 2699 } 2700 2701 /* Issue a global reset */ 2702 e1000_reset_hw(hw); 2703 if (hw->mac.type >= igb_mac_min) { 2704 E1000_WRITE_REG(hw, E1000_WUC, 0); 2705 } else { 2706 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2707 em_disable_aspm(sc); 2708 } 2709 if (sc->flags & IGB_MEDIA_RESET) { 2710 e1000_setup_init_funcs(hw, true); 2711 e1000_get_bus_info(hw); 2712 sc->flags &= ~IGB_MEDIA_RESET; 2713 } 2714 /* and a re-init */ 2715 if (e1000_init_hw(hw) < 0) { 2716 device_printf(dev, "Hardware Initialization Failed\n"); 2717 return; 2718 } 2719 if (hw->mac.type >= igb_mac_min) 2720 igb_init_dmac(sc, pba); 2721 2722 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2723 e1000_get_phy_info(hw); 2724 e1000_check_for_link(hw); 2725} 2726 2727/* 2728 * Initialise the RSS mapping for NICs that support multiple transmit/ 2729 * receive rings. 2730 */ 2731 2732#define RSSKEYLEN 10 2733static void 2734em_initialize_rss_mapping(struct e1000_softc *sc) 2735{ 2736 uint8_t rss_key[4 * RSSKEYLEN]; 2737 uint32_t reta = 0; 2738 struct e1000_hw *hw = &sc->hw; 2739 int i; 2740 2741 /* 2742 * Configure RSS key 2743 */ 2744 arc4rand(rss_key, sizeof(rss_key), 0); 2745 for (i = 0; i < RSSKEYLEN; ++i) { 2746 uint32_t rssrk = 0; 2747 2748 rssrk = EM_RSSRK_VAL(rss_key, i); 2749 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2750 } 2751 2752 /* 2753 * Configure RSS redirect table in following fashion: 2754 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2755 */ 2756 for (i = 0; i < sizeof(reta); ++i) { 2757 uint32_t q; 2758 2759 q = (i % sc->rx_num_queues) << 7; 2760 reta |= q << (8 * i); 2761 } 2762 2763 for (i = 0; i < 32; ++i) 2764 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2765 2766 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2767 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2768 E1000_MRQC_RSS_FIELD_IPV4 | 2769 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2770 E1000_MRQC_RSS_FIELD_IPV6_EX | 2771 E1000_MRQC_RSS_FIELD_IPV6); 2772} 2773 2774static void 2775igb_initialize_rss_mapping(struct e1000_softc *sc) 2776{ 2777 struct e1000_hw *hw = &sc->hw; 2778 int i; 2779 int queue_id; 2780 u32 reta; 2781 u32 rss_key[10], mrqc, shift = 0; 2782 2783 /* XXX? */ 2784 if (hw->mac.type == e1000_82575) 2785 shift = 6; 2786 2787 /* 2788 * The redirection table controls which destination 2789 * queue each bucket redirects traffic to. 2790 * Each DWORD represents four queues, with the LSB 2791 * being the first queue in the DWORD. 2792 * 2793 * This just allocates buckets to queues using round-robin 2794 * allocation. 2795 * 2796 * NOTE: It Just Happens to line up with the default 2797 * RSS allocation method. 2798 */ 2799 2800 /* Warning FM follows */ 2801 reta = 0; 2802 for (i = 0; i < 128; i++) { 2803#ifdef RSS 2804 queue_id = rss_get_indirection_to_bucket(i); 2805 /* 2806 * If we have more queues than buckets, we'll 2807 * end up mapping buckets to a subset of the 2808 * queues. 2809 * 2810 * If we have more buckets than queues, we'll 2811 * end up instead assigning multiple buckets 2812 * to queues. 2813 * 2814 * Both are suboptimal, but we need to handle 2815 * the case so we don't go out of bounds 2816 * indexing arrays and such. 2817 */ 2818 queue_id = queue_id % sc->rx_num_queues; 2819#else 2820 queue_id = (i % sc->rx_num_queues); 2821#endif 2822 /* Adjust if required */ 2823 queue_id = queue_id << shift; 2824 2825 /* 2826 * The low 8 bits are for hash value (n+0); 2827 * The next 8 bits are for hash value (n+1), etc. 2828 */ 2829 reta = reta >> 8; 2830 reta = reta | ( ((uint32_t) queue_id) << 24); 2831 if ((i & 3) == 3) { 2832 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2833 reta = 0; 2834 } 2835 } 2836 2837 /* Now fill in hash table */ 2838 2839 /* 2840 * MRQC: Multiple Receive Queues Command 2841 * Set queuing to RSS control, number depends on the device. 2842 */ 2843 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2844 2845#ifdef RSS 2846 /* XXX ew typecasting */ 2847 rss_getkey((uint8_t *) &rss_key); 2848#else 2849 arc4rand(&rss_key, sizeof(rss_key), 0); 2850#endif 2851 for (i = 0; i < 10; i++) 2852 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2853 2854 /* 2855 * Configure the RSS fields to hash upon. 2856 */ 2857 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2858 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2859 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2860 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2861 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2862 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2863 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2864 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2865 2866 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2867} 2868 2869/********************************************************************* 2870 * 2871 * Setup networking device structure and register interface media. 2872 * 2873 **********************************************************************/ 2874static int 2875em_setup_interface(if_ctx_t ctx) 2876{ 2877 struct ifnet *ifp = iflib_get_ifp(ctx); 2878 struct e1000_softc *sc = iflib_get_softc(ctx); 2879 if_softc_ctx_t scctx = sc->shared; 2880 2881 INIT_DEBUGOUT("em_setup_interface: begin"); 2882 2883 /* Single Queue */ 2884 if (sc->tx_num_queues == 1) { 2885 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2886 if_setsendqready(ifp); 2887 } 2888 2889 /* 2890 * Specify the media types supported by this adapter and register 2891 * callbacks to update media and link information 2892 */ 2893 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2894 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 2895 u_char fiber_type = IFM_1000_SX; /* default type */ 2896 2897 if (sc->hw.mac.type == e1000_82545) 2898 fiber_type = IFM_1000_LX; 2899 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2900 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 2901 } else { 2902 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2903 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2904 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2905 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2906 if (sc->hw.phy.type != e1000_phy_ife) { 2907 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2908 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2909 } 2910 } 2911 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2912 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 2913 return (0); 2914} 2915 2916static int 2917em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2918{ 2919 struct e1000_softc *sc = iflib_get_softc(ctx); 2920 if_softc_ctx_t scctx = sc->shared; 2921 int error = E1000_SUCCESS; 2922 struct em_tx_queue *que; 2923 int i, j; 2924 2925 MPASS(sc->tx_num_queues > 0); 2926 MPASS(sc->tx_num_queues == ntxqsets); 2927 2928 /* First allocate the top level queue structs */ 2929 if (!(sc->tx_queues = 2930 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2931 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2932 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2933 return(ENOMEM); 2934 } 2935 2936 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 2937 /* Set up some basics */ 2938 2939 struct tx_ring *txr = &que->txr; 2940 txr->sc = que->sc = sc; 2941 que->me = txr->me = i; 2942 2943 /* Allocate report status array */ 2944 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2945 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2946 error = ENOMEM; 2947 goto fail; 2948 } 2949 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2950 txr->tx_rsq[j] = QIDX_INVALID; 2951 /* get the virtual and physical address of the hardware queues */ 2952 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2953 txr->tx_paddr = paddrs[i*ntxqs]; 2954 } 2955 2956 if (bootverbose) 2957 device_printf(iflib_get_dev(ctx), 2958 "allocated for %d tx_queues\n", sc->tx_num_queues); 2959 return (0); 2960fail: 2961 em_if_queues_free(ctx); 2962 return (error); 2963} 2964 2965static int 2966em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2967{ 2968 struct e1000_softc *sc = iflib_get_softc(ctx); 2969 int error = E1000_SUCCESS; 2970 struct em_rx_queue *que; 2971 int i; 2972 2973 MPASS(sc->rx_num_queues > 0); 2974 MPASS(sc->rx_num_queues == nrxqsets); 2975 2976 /* First allocate the top level queue structs */ 2977 if (!(sc->rx_queues = 2978 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2979 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2980 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2981 error = ENOMEM; 2982 goto fail; 2983 } 2984 2985 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 2986 /* Set up some basics */ 2987 struct rx_ring *rxr = &que->rxr; 2988 rxr->sc = que->sc = sc; 2989 rxr->que = que; 2990 que->me = rxr->me = i; 2991 2992 /* get the virtual and physical address of the hardware queues */ 2993 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2994 rxr->rx_paddr = paddrs[i*nrxqs]; 2995 } 2996 2997 if (bootverbose) 2998 device_printf(iflib_get_dev(ctx), 2999 "allocated for %d rx_queues\n", sc->rx_num_queues); 3000 3001 return (0); 3002fail: 3003 em_if_queues_free(ctx); 3004 return (error); 3005} 3006 3007static void 3008em_if_queues_free(if_ctx_t ctx) 3009{ 3010 struct e1000_softc *sc = iflib_get_softc(ctx); 3011 struct em_tx_queue *tx_que = sc->tx_queues; 3012 struct em_rx_queue *rx_que = sc->rx_queues; 3013 3014 if (tx_que != NULL) { 3015 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3016 struct tx_ring *txr = &tx_que->txr; 3017 if (txr->tx_rsq == NULL) 3018 break; 3019 3020 free(txr->tx_rsq, M_DEVBUF); 3021 txr->tx_rsq = NULL; 3022 } 3023 free(sc->tx_queues, M_DEVBUF); 3024 sc->tx_queues = NULL; 3025 } 3026 3027 if (rx_que != NULL) { 3028 free(sc->rx_queues, M_DEVBUF); 3029 sc->rx_queues = NULL; 3030 } 3031} 3032 3033/********************************************************************* 3034 * 3035 * Enable transmit unit. 3036 * 3037 **********************************************************************/ 3038static void 3039em_initialize_transmit_unit(if_ctx_t ctx) 3040{ 3041 struct e1000_softc *sc = iflib_get_softc(ctx); 3042 if_softc_ctx_t scctx = sc->shared; 3043 struct em_tx_queue *que; 3044 struct tx_ring *txr; 3045 struct e1000_hw *hw = &sc->hw; 3046 u32 tctl, txdctl = 0, tarc, tipg = 0; 3047 3048 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3049 3050 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3051 u64 bus_addr; 3052 caddr_t offp, endp; 3053 3054 que = &sc->tx_queues[i]; 3055 txr = &que->txr; 3056 bus_addr = txr->tx_paddr; 3057 3058 /* Clear checksum offload context. */ 3059 offp = (caddr_t)&txr->csum_flags; 3060 endp = (caddr_t)(txr + 1); 3061 bzero(offp, endp - offp); 3062 3063 /* Base and Len of TX Ring */ 3064 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3065 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3066 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3067 (u32)(bus_addr >> 32)); 3068 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3069 (u32)bus_addr); 3070 /* Init the HEAD/TAIL indices */ 3071 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3072 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3073 3074 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3075 E1000_READ_REG(hw, E1000_TDBAL(i)), 3076 E1000_READ_REG(hw, E1000_TDLEN(i))); 3077 3078 txdctl = 0; /* clear txdctl */ 3079 txdctl |= 0x1f; /* PTHRESH */ 3080 txdctl |= 1 << 8; /* HTHRESH */ 3081 txdctl |= 1 << 16;/* WTHRESH */ 3082 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3083 txdctl |= E1000_TXDCTL_GRAN; 3084 txdctl |= 1 << 25; /* LWTHRESH */ 3085 3086 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3087 } 3088 3089 /* Set the default values for the Tx Inter Packet Gap timer */ 3090 switch (hw->mac.type) { 3091 case e1000_80003es2lan: 3092 tipg = DEFAULT_82543_TIPG_IPGR1; 3093 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3094 E1000_TIPG_IPGR2_SHIFT; 3095 break; 3096 case e1000_82542: 3097 tipg = DEFAULT_82542_TIPG_IPGT; 3098 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3099 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3100 break; 3101 default: 3102 if (hw->phy.media_type == e1000_media_type_fiber || 3103 hw->phy.media_type == e1000_media_type_internal_serdes) 3104 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3105 else 3106 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3107 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3108 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3109 } 3110 3111 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3112 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3113 3114 if(hw->mac.type >= e1000_82540) 3115 E1000_WRITE_REG(hw, E1000_TADV, 3116 sc->tx_abs_int_delay.value); 3117 3118 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3119 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3120 tarc |= TARC_SPEED_MODE_BIT; 3121 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3122 } else if (hw->mac.type == e1000_80003es2lan) { 3123 /* errata: program both queues to unweighted RR */ 3124 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3125 tarc |= 1; 3126 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3127 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3128 tarc |= 1; 3129 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3130 } else if (hw->mac.type == e1000_82574) { 3131 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3132 tarc |= TARC_ERRATA_BIT; 3133 if ( sc->tx_num_queues > 1) { 3134 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3135 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3136 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3137 } else 3138 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3139 } 3140 3141 if (sc->tx_int_delay.value > 0) 3142 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3143 3144 /* Program the Transmit Control Register */ 3145 tctl = E1000_READ_REG(hw, E1000_TCTL); 3146 tctl &= ~E1000_TCTL_CT; 3147 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3148 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3149 3150 if (hw->mac.type >= e1000_82571) 3151 tctl |= E1000_TCTL_MULR; 3152 3153 /* This write will effectively turn on the transmit unit. */ 3154 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3155 3156 /* SPT and KBL errata workarounds */ 3157 if (hw->mac.type == e1000_pch_spt) { 3158 u32 reg; 3159 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3160 reg |= E1000_RCTL_RDMTS_HEX; 3161 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3162 /* i218-i219 Specification Update 1.5.4.5 */ 3163 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3164 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3165 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3166 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3167 } 3168} 3169 3170/********************************************************************* 3171 * 3172 * Enable receive unit. 3173 * 3174 **********************************************************************/ 3175#define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3176 3177static void 3178em_initialize_receive_unit(if_ctx_t ctx) 3179{ 3180 struct e1000_softc *sc = iflib_get_softc(ctx); 3181 if_softc_ctx_t scctx = sc->shared; 3182 struct ifnet *ifp = iflib_get_ifp(ctx); 3183 struct e1000_hw *hw = &sc->hw; 3184 struct em_rx_queue *que; 3185 int i; 3186 uint32_t rctl, rxcsum; 3187 3188 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3189 3190 /* 3191 * Make sure receives are disabled while setting 3192 * up the descriptor ring 3193 */ 3194 rctl = E1000_READ_REG(hw, E1000_RCTL); 3195 /* Do not disable if ever enabled on this hardware */ 3196 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3197 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3198 3199 /* Setup the Receive Control Register */ 3200 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3201 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3202 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3203 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3204 3205 /* Do not store bad packets */ 3206 rctl &= ~E1000_RCTL_SBP; 3207 3208 /* Enable Long Packet receive */ 3209 if (if_getmtu(ifp) > ETHERMTU) 3210 rctl |= E1000_RCTL_LPE; 3211 else 3212 rctl &= ~E1000_RCTL_LPE; 3213 3214 /* Strip the CRC */ 3215 if (!em_disable_crc_stripping) 3216 rctl |= E1000_RCTL_SECRC; 3217 3218 if (hw->mac.type >= e1000_82540) { 3219 E1000_WRITE_REG(hw, E1000_RADV, 3220 sc->rx_abs_int_delay.value); 3221 3222 /* 3223 * Set the interrupt throttling rate. Value is calculated 3224 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3225 */ 3226 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3227 } 3228 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3229 3230 if (hw->mac.type >= em_mac_min) { 3231 uint32_t rfctl; 3232 /* Use extended rx descriptor formats */ 3233 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3234 rfctl |= E1000_RFCTL_EXTEN; 3235 3236 /* 3237 * When using MSI-X interrupts we need to throttle 3238 * using the EITR register (82574 only) 3239 */ 3240 if (hw->mac.type == e1000_82574) { 3241 for (int i = 0; i < 4; i++) 3242 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3243 DEFAULT_ITR); 3244 /* Disable accelerated acknowledge */ 3245 rfctl |= E1000_RFCTL_ACK_DIS; 3246 } 3247 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3248 } 3249 3250 /* Set up L3 and L4 csum Rx descriptor offloads */ 3251 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3252 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3253 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3254 if (hw->mac.type > e1000_82575) 3255 rxcsum |= E1000_RXCSUM_CRCOFL; 3256 else if (hw->mac.type < em_mac_min && 3257 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3258 rxcsum |= E1000_RXCSUM_IPV6OFL; 3259 } else { 3260 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3261 if (hw->mac.type > e1000_82575) 3262 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3263 else if (hw->mac.type < em_mac_min) 3264 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3265 } 3266 3267 if (sc->rx_num_queues > 1) { 3268 /* RSS hash needed in the Rx descriptor */ 3269 rxcsum |= E1000_RXCSUM_PCSD; 3270 3271 if (hw->mac.type >= igb_mac_min) 3272 igb_initialize_rss_mapping(sc); 3273 else 3274 em_initialize_rss_mapping(sc); 3275 } 3276 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3277 3278 /* 3279 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3280 * long latencies are observed, like Lenovo X60. This 3281 * change eliminates the problem, but since having positive 3282 * values in RDTR is a known source of problems on other 3283 * platforms another solution is being sought. 3284 */ 3285 if (hw->mac.type == e1000_82573) 3286 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3287 3288 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3289 struct rx_ring *rxr = &que->rxr; 3290 /* Setup the Base and Length of the Rx Descriptor Ring */ 3291 u64 bus_addr = rxr->rx_paddr; 3292#if 0 3293 u32 rdt = sc->rx_num_queues -1; /* default */ 3294#endif 3295 3296 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3297 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3298 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3299 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3300 /* Setup the Head and Tail Descriptor Pointers */ 3301 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3302 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3303 } 3304 3305 /* 3306 * Set PTHRESH for improved jumbo performance 3307 * According to 10.2.5.11 of Intel 82574 Datasheet, 3308 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3309 * Only write to RXDCTL(1) if there is a need for different 3310 * settings. 3311 */ 3312 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3313 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3314 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3315 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3316 } else if (hw->mac.type == e1000_82574) { 3317 for (int i = 0; i < sc->rx_num_queues; i++) { 3318 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3319 rxdctl |= 0x20; /* PTHRESH */ 3320 rxdctl |= 4 << 8; /* HTHRESH */ 3321 rxdctl |= 4 << 16;/* WTHRESH */ 3322 rxdctl |= 1 << 24; /* Switch to granularity */ 3323 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3324 } 3325 } else if (hw->mac.type >= igb_mac_min) { 3326 u32 psize, srrctl = 0; 3327 3328 if (if_getmtu(ifp) > ETHERMTU) { 3329 psize = scctx->isc_max_frame_size; 3330 /* are we on a vlan? */ 3331 if (ifp->if_vlantrunk != NULL) 3332 psize += VLAN_TAG_SIZE; 3333 3334 if (sc->vf_ifp) 3335 e1000_rlpml_set_vf(hw, psize); 3336 else 3337 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3338 } 3339 3340 /* Set maximum packet buffer len */ 3341 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3342 E1000_SRRCTL_BSIZEPKT_SHIFT; 3343 3344 /* 3345 * If TX flow control is disabled and there's >1 queue defined, 3346 * enable DROP. 3347 * 3348 * This drops frames rather than hanging the RX MAC for all queues. 3349 */ 3350 if ((sc->rx_num_queues > 1) && 3351 (sc->fc == e1000_fc_none || 3352 sc->fc == e1000_fc_rx_pause)) { 3353 srrctl |= E1000_SRRCTL_DROP_EN; 3354 } 3355 /* Setup the Base and Length of the Rx Descriptor Rings */ 3356 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3357 struct rx_ring *rxr = &que->rxr; 3358 u64 bus_addr = rxr->rx_paddr; 3359 u32 rxdctl; 3360 3361#ifdef notyet 3362 /* Configure for header split? -- ignore for now */ 3363 rxr->hdr_split = igb_header_split; 3364#else 3365 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3366#endif 3367 3368 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3369 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3370 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3371 (uint32_t)(bus_addr >> 32)); 3372 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3373 (uint32_t)bus_addr); 3374 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3375 /* Enable this Queue */ 3376 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3377 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3378 rxdctl &= 0xFFF00000; 3379 rxdctl |= IGB_RX_PTHRESH; 3380 rxdctl |= IGB_RX_HTHRESH << 8; 3381 rxdctl |= IGB_RX_WTHRESH << 16; 3382 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3383 } 3384 } else if (hw->mac.type >= e1000_pch2lan) { 3385 if (if_getmtu(ifp) > ETHERMTU) 3386 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3387 else 3388 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3389 } 3390 3391 /* Make sure VLAN Filters are off */ 3392 rctl &= ~E1000_RCTL_VFE; 3393 3394 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3395 if (hw->mac.type < igb_mac_min) { 3396 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3397 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3398 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3399 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3400 else if (sc->rx_mbuf_sz > 8192) 3401 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3402 else { 3403 rctl |= E1000_RCTL_SZ_2048; 3404 rctl &= ~E1000_RCTL_BSEX; 3405 } 3406 } else 3407 rctl |= E1000_RCTL_SZ_2048; 3408 3409 /* 3410 * rctl bits 11:10 are as follows 3411 * lem: reserved 3412 * em: DTYPE 3413 * igb: reserved 3414 * and should be 00 on all of the above 3415 */ 3416 rctl &= ~0x00000C00; 3417 3418 /* Write out the settings */ 3419 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3420 3421 return; 3422} 3423 3424static void 3425em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3426{ 3427 struct e1000_softc *sc = iflib_get_softc(ctx); 3428 u32 index, bit; 3429 3430 index = (vtag >> 5) & 0x7F; 3431 bit = vtag & 0x1F; 3432 sc->shadow_vfta[index] |= (1 << bit); 3433 ++sc->num_vlans; 3434 em_if_vlan_filter_write(sc); 3435} 3436 3437static void 3438em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3439{ 3440 struct e1000_softc *sc = iflib_get_softc(ctx); 3441 u32 index, bit; 3442 3443 index = (vtag >> 5) & 0x7F; 3444 bit = vtag & 0x1F; 3445 sc->shadow_vfta[index] &= ~(1 << bit); 3446 --sc->num_vlans; 3447 em_if_vlan_filter_write(sc); 3448} 3449 3450static bool 3451em_if_vlan_filter_capable(if_ctx_t ctx) 3452{ 3453 if_t ifp = iflib_get_ifp(ctx); 3454 3455 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3456 !em_disable_crc_stripping) 3457 return (true); 3458 3459 return (false); 3460} 3461 3462static bool 3463em_if_vlan_filter_used(if_ctx_t ctx) 3464{ 3465 struct e1000_softc *sc = iflib_get_softc(ctx); 3466 3467 if (!em_if_vlan_filter_capable(ctx)) 3468 return (false); 3469 3470 for (int i = 0; i < EM_VFTA_SIZE; i++) 3471 if (sc->shadow_vfta[i] != 0) 3472 return (true); 3473 3474 return (false); 3475} 3476 3477static void 3478em_if_vlan_filter_enable(struct e1000_softc *sc) 3479{ 3480 struct e1000_hw *hw = &sc->hw; 3481 u32 reg; 3482 3483 reg = E1000_READ_REG(hw, E1000_RCTL); 3484 reg &= ~E1000_RCTL_CFIEN; 3485 reg |= E1000_RCTL_VFE; 3486 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3487} 3488 3489static void 3490em_if_vlan_filter_disable(struct e1000_softc *sc) 3491{ 3492 struct e1000_hw *hw = &sc->hw; 3493 u32 reg; 3494 3495 reg = E1000_READ_REG(hw, E1000_RCTL); 3496 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3497 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3498} 3499 3500static void 3501em_if_vlan_filter_write(struct e1000_softc *sc) 3502{ 3503 struct e1000_hw *hw = &sc->hw; 3504 3505 if (sc->vf_ifp) 3506 return; 3507 3508 /* Disable interrupts for lem-class devices during the filter change */ 3509 if (hw->mac.type < em_mac_min) 3510 em_if_intr_disable(sc->ctx); 3511 3512 for (int i = 0; i < EM_VFTA_SIZE; i++) 3513 if (sc->shadow_vfta[i] != 0) { 3514 /* XXXKB: incomplete VF support, we return early above */ 3515 if (sc->vf_ifp) 3516 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3517 else 3518 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3519 } 3520 3521 /* Re-enable interrupts for lem-class devices */ 3522 if (hw->mac.type < em_mac_min) 3523 em_if_intr_enable(sc->ctx); 3524} 3525 3526static void 3527em_setup_vlan_hw_support(if_ctx_t ctx) 3528{ 3529 struct e1000_softc *sc = iflib_get_softc(ctx); 3530 struct e1000_hw *hw = &sc->hw; 3531 struct ifnet *ifp = iflib_get_ifp(ctx); 3532 u32 reg; 3533 3534 /* XXXKB: Return early if we are a VF until VF decap and filter management 3535 * is ready and tested. 3536 */ 3537 if (sc->vf_ifp) 3538 return; 3539 3540 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3541 !em_disable_crc_stripping) { 3542 reg = E1000_READ_REG(hw, E1000_CTRL); 3543 reg |= E1000_CTRL_VME; 3544 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3545 } else { 3546 reg = E1000_READ_REG(hw, E1000_CTRL); 3547 reg &= ~E1000_CTRL_VME; 3548 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3549 } 3550 3551 /* If we aren't doing HW filtering, we're done */ 3552 if (!em_if_vlan_filter_capable(ctx)) { 3553 em_if_vlan_filter_disable(sc); 3554 return; 3555 } 3556 3557 /* 3558 * A soft reset zero's out the VFTA, so 3559 * we need to repopulate it now. 3560 */ 3561 em_if_vlan_filter_write(sc); 3562 3563 /* Enable the Filter Table */ 3564 em_if_vlan_filter_enable(sc); 3565} 3566 3567static void 3568em_if_intr_enable(if_ctx_t ctx) 3569{ 3570 struct e1000_softc *sc = iflib_get_softc(ctx); 3571 struct e1000_hw *hw = &sc->hw; 3572 u32 ims_mask = IMS_ENABLE_MASK; 3573 3574 if (sc->intr_type == IFLIB_INTR_MSIX) { 3575 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3576 ims_mask |= sc->ims; 3577 } 3578 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3579 E1000_WRITE_FLUSH(hw); 3580} 3581 3582static void 3583em_if_intr_disable(if_ctx_t ctx) 3584{ 3585 struct e1000_softc *sc = iflib_get_softc(ctx); 3586 struct e1000_hw *hw = &sc->hw; 3587 3588 if (sc->intr_type == IFLIB_INTR_MSIX) 3589 E1000_WRITE_REG(hw, EM_EIAC, 0); 3590 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3591 E1000_WRITE_FLUSH(hw); 3592} 3593 3594static void 3595igb_if_intr_enable(if_ctx_t ctx) 3596{ 3597 struct e1000_softc *sc = iflib_get_softc(ctx); 3598 struct e1000_hw *hw = &sc->hw; 3599 u32 mask; 3600 3601 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3602 mask = (sc->que_mask | sc->link_mask); 3603 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3604 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3605 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3606 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3607 } else 3608 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3609 E1000_WRITE_FLUSH(hw); 3610} 3611 3612static void 3613igb_if_intr_disable(if_ctx_t ctx) 3614{ 3615 struct e1000_softc *sc = iflib_get_softc(ctx); 3616 struct e1000_hw *hw = &sc->hw; 3617 3618 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3619 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3620 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3621 } 3622 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3623 E1000_WRITE_FLUSH(hw); 3624} 3625 3626/* 3627 * Bit of a misnomer, what this really means is 3628 * to enable OS management of the system... aka 3629 * to disable special hardware management features 3630 */ 3631static void 3632em_init_manageability(struct e1000_softc *sc) 3633{ 3634 /* A shared code workaround */ 3635#define E1000_82542_MANC2H E1000_MANC2H 3636 if (sc->has_manage) { 3637 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3638 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3639 3640 /* disable hardware interception of ARP */ 3641 manc &= ~(E1000_MANC_ARP_EN); 3642 3643 /* enable receiving management packets to the host */ 3644 manc |= E1000_MANC_EN_MNG2HOST; 3645#define E1000_MNG2HOST_PORT_623 (1 << 5) 3646#define E1000_MNG2HOST_PORT_664 (1 << 6) 3647 manc2h |= E1000_MNG2HOST_PORT_623; 3648 manc2h |= E1000_MNG2HOST_PORT_664; 3649 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3650 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3651 } 3652} 3653 3654/* 3655 * Give control back to hardware management 3656 * controller if there is one. 3657 */ 3658static void 3659em_release_manageability(struct e1000_softc *sc) 3660{ 3661 if (sc->has_manage) { 3662 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3663 3664 /* re-enable hardware interception of ARP */ 3665 manc |= E1000_MANC_ARP_EN; 3666 manc &= ~E1000_MANC_EN_MNG2HOST; 3667 3668 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3669 } 3670} 3671 3672/* 3673 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3674 * For ASF and Pass Through versions of f/w this means 3675 * that the driver is loaded. For AMT version type f/w 3676 * this means that the network i/f is open. 3677 */ 3678static void 3679em_get_hw_control(struct e1000_softc *sc) 3680{ 3681 u32 ctrl_ext, swsm; 3682 3683 if (sc->vf_ifp) 3684 return; 3685 3686 if (sc->hw.mac.type == e1000_82573) { 3687 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3688 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3689 swsm | E1000_SWSM_DRV_LOAD); 3690 return; 3691 } 3692 /* else */ 3693 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3694 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3695 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3696} 3697 3698/* 3699 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3700 * For ASF and Pass Through versions of f/w this means that 3701 * the driver is no longer loaded. For AMT versions of the 3702 * f/w this means that the network i/f is closed. 3703 */ 3704static void 3705em_release_hw_control(struct e1000_softc *sc) 3706{ 3707 u32 ctrl_ext, swsm; 3708 3709 if (!sc->has_manage) 3710 return; 3711 3712 if (sc->hw.mac.type == e1000_82573) { 3713 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3714 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3715 swsm & ~E1000_SWSM_DRV_LOAD); 3716 return; 3717 } 3718 /* else */ 3719 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3720 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3721 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3722 return; 3723} 3724 3725static int 3726em_is_valid_ether_addr(u8 *addr) 3727{ 3728 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3729 3730 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3731 return (false); 3732 } 3733 3734 return (true); 3735} 3736 3737/* 3738** Parse the interface capabilities with regard 3739** to both system management and wake-on-lan for 3740** later use. 3741*/ 3742static void 3743em_get_wakeup(if_ctx_t ctx) 3744{ 3745 struct e1000_softc *sc = iflib_get_softc(ctx); 3746 device_t dev = iflib_get_dev(ctx); 3747 u16 eeprom_data = 0, device_id, apme_mask; 3748 3749 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3750 apme_mask = EM_EEPROM_APME; 3751 3752 switch (sc->hw.mac.type) { 3753 case e1000_82542: 3754 case e1000_82543: 3755 break; 3756 case e1000_82544: 3757 e1000_read_nvm(&sc->hw, 3758 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3759 apme_mask = EM_82544_APME; 3760 break; 3761 case e1000_82546: 3762 case e1000_82546_rev_3: 3763 if (sc->hw.bus.func == 1) { 3764 e1000_read_nvm(&sc->hw, 3765 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3766 break; 3767 } else 3768 e1000_read_nvm(&sc->hw, 3769 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3770 break; 3771 case e1000_82573: 3772 case e1000_82583: 3773 sc->has_amt = true; 3774 /* FALLTHROUGH */ 3775 case e1000_82571: 3776 case e1000_82572: 3777 case e1000_80003es2lan: 3778 if (sc->hw.bus.func == 1) { 3779 e1000_read_nvm(&sc->hw, 3780 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3781 break; 3782 } else 3783 e1000_read_nvm(&sc->hw, 3784 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3785 break; 3786 case e1000_ich8lan: 3787 case e1000_ich9lan: 3788 case e1000_ich10lan: 3789 case e1000_pchlan: 3790 case e1000_pch2lan: 3791 case e1000_pch_lpt: 3792 case e1000_pch_spt: 3793 case e1000_82575: /* listing all igb devices */ 3794 case e1000_82576: 3795 case e1000_82580: 3796 case e1000_i350: 3797 case e1000_i354: 3798 case e1000_i210: 3799 case e1000_i211: 3800 case e1000_vfadapt: 3801 case e1000_vfadapt_i350: 3802 apme_mask = E1000_WUC_APME; 3803 sc->has_amt = true; 3804 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 3805 break; 3806 default: 3807 e1000_read_nvm(&sc->hw, 3808 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3809 break; 3810 } 3811 if (eeprom_data & apme_mask) 3812 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3813 /* 3814 * We have the eeprom settings, now apply the special cases 3815 * where the eeprom may be wrong or the board won't support 3816 * wake on lan on a particular port 3817 */ 3818 device_id = pci_get_device(dev); 3819 switch (device_id) { 3820 case E1000_DEV_ID_82546GB_PCIE: 3821 sc->wol = 0; 3822 break; 3823 case E1000_DEV_ID_82546EB_FIBER: 3824 case E1000_DEV_ID_82546GB_FIBER: 3825 /* Wake events only supported on port A for dual fiber 3826 * regardless of eeprom setting */ 3827 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3828 E1000_STATUS_FUNC_1) 3829 sc->wol = 0; 3830 break; 3831 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3832 /* if quad port adapter, disable WoL on all but port A */ 3833 if (global_quad_port_a != 0) 3834 sc->wol = 0; 3835 /* Reset for multiple quad port adapters */ 3836 if (++global_quad_port_a == 4) 3837 global_quad_port_a = 0; 3838 break; 3839 case E1000_DEV_ID_82571EB_FIBER: 3840 /* Wake events only supported on port A for dual fiber 3841 * regardless of eeprom setting */ 3842 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3843 E1000_STATUS_FUNC_1) 3844 sc->wol = 0; 3845 break; 3846 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3847 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3848 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3849 /* if quad port adapter, disable WoL on all but port A */ 3850 if (global_quad_port_a != 0) 3851 sc->wol = 0; 3852 /* Reset for multiple quad port adapters */ 3853 if (++global_quad_port_a == 4) 3854 global_quad_port_a = 0; 3855 break; 3856 } 3857 return; 3858} 3859 3860 3861/* 3862 * Enable PCI Wake On Lan capability 3863 */ 3864static void 3865em_enable_wakeup(if_ctx_t ctx) 3866{ 3867 struct e1000_softc *sc = iflib_get_softc(ctx); 3868 device_t dev = iflib_get_dev(ctx); 3869 if_t ifp = iflib_get_ifp(ctx); 3870 int error = 0; 3871 u32 pmc, ctrl, ctrl_ext, rctl; 3872 u16 status; 3873 3874 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3875 return; 3876 3877 /* 3878 * Determine type of Wakeup: note that wol 3879 * is set with all bits on by default. 3880 */ 3881 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3882 sc->wol &= ~E1000_WUFC_MAG; 3883 3884 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3885 sc->wol &= ~E1000_WUFC_EX; 3886 3887 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3888 sc->wol &= ~E1000_WUFC_MC; 3889 else { 3890 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 3891 rctl |= E1000_RCTL_MPE; 3892 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 3893 } 3894 3895 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3896 goto pme; 3897 3898 /* Advertise the wakeup capability */ 3899 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 3900 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3901 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 3902 3903 /* Keep the laser running on Fiber adapters */ 3904 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3905 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3906 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3907 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3908 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 3909 } 3910 3911 if ((sc->hw.mac.type == e1000_ich8lan) || 3912 (sc->hw.mac.type == e1000_pchlan) || 3913 (sc->hw.mac.type == e1000_ich9lan) || 3914 (sc->hw.mac.type == e1000_ich10lan)) 3915 e1000_suspend_workarounds_ich8lan(&sc->hw); 3916 3917 if ( sc->hw.mac.type >= e1000_pchlan) { 3918 error = em_enable_phy_wakeup(sc); 3919 if (error) 3920 goto pme; 3921 } else { 3922 /* Enable wakeup by the MAC */ 3923 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 3924 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 3925 } 3926 3927 if (sc->hw.phy.type == e1000_phy_igp_3) 3928 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 3929 3930pme: 3931 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3932 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3933 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3934 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3935 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3936 3937 return; 3938} 3939 3940/* 3941 * WOL in the newer chipset interfaces (pchlan) 3942 * require thing to be copied into the phy 3943 */ 3944static int 3945em_enable_phy_wakeup(struct e1000_softc *sc) 3946{ 3947 struct e1000_hw *hw = &sc->hw; 3948 u32 mreg, ret = 0; 3949 u16 preg; 3950 3951 /* copy MAC RARs to PHY RARs */ 3952 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3953 3954 /* copy MAC MTA to PHY MTA */ 3955 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3956 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3957 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3958 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3959 (u16)((mreg >> 16) & 0xFFFF)); 3960 } 3961 3962 /* configure PHY Rx Control register */ 3963 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3964 mreg = E1000_READ_REG(hw, E1000_RCTL); 3965 if (mreg & E1000_RCTL_UPE) 3966 preg |= BM_RCTL_UPE; 3967 if (mreg & E1000_RCTL_MPE) 3968 preg |= BM_RCTL_MPE; 3969 preg &= ~(BM_RCTL_MO_MASK); 3970 if (mreg & E1000_RCTL_MO_3) 3971 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3972 << BM_RCTL_MO_SHIFT); 3973 if (mreg & E1000_RCTL_BAM) 3974 preg |= BM_RCTL_BAM; 3975 if (mreg & E1000_RCTL_PMCF) 3976 preg |= BM_RCTL_PMCF; 3977 mreg = E1000_READ_REG(hw, E1000_CTRL); 3978 if (mreg & E1000_CTRL_RFCE) 3979 preg |= BM_RCTL_RFCE; 3980 e1000_write_phy_reg(hw, BM_RCTL, preg); 3981 3982 /* enable PHY wakeup in MAC register */ 3983 E1000_WRITE_REG(hw, E1000_WUC, 3984 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3985 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 3986 3987 /* configure and enable PHY wakeup in PHY registers */ 3988 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 3989 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3990 3991 /* activate PHY wakeup */ 3992 ret = hw->phy.ops.acquire(hw); 3993 if (ret) { 3994 printf("Could not acquire PHY\n"); 3995 return ret; 3996 } 3997 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3998 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3999 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4000 if (ret) { 4001 printf("Could not read PHY page 769\n"); 4002 goto out; 4003 } 4004 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4005 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4006 if (ret) 4007 printf("Could not set PHY Host Wakeup bit\n"); 4008out: 4009 hw->phy.ops.release(hw); 4010 4011 return ret; 4012} 4013 4014static void 4015em_if_led_func(if_ctx_t ctx, int onoff) 4016{ 4017 struct e1000_softc *sc = iflib_get_softc(ctx); 4018 4019 if (onoff) { 4020 e1000_setup_led(&sc->hw); 4021 e1000_led_on(&sc->hw); 4022 } else { 4023 e1000_led_off(&sc->hw); 4024 e1000_cleanup_led(&sc->hw); 4025 } 4026} 4027 4028/* 4029 * Disable the L0S and L1 LINK states 4030 */ 4031static void 4032em_disable_aspm(struct e1000_softc *sc) 4033{ 4034 int base, reg; 4035 u16 link_cap,link_ctrl; 4036 device_t dev = sc->dev; 4037 4038 switch (sc->hw.mac.type) { 4039 case e1000_82573: 4040 case e1000_82574: 4041 case e1000_82583: 4042 break; 4043 default: 4044 return; 4045 } 4046 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4047 return; 4048 reg = base + PCIER_LINK_CAP; 4049 link_cap = pci_read_config(dev, reg, 2); 4050 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4051 return; 4052 reg = base + PCIER_LINK_CTL; 4053 link_ctrl = pci_read_config(dev, reg, 2); 4054 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4055 pci_write_config(dev, reg, link_ctrl, 2); 4056 return; 4057} 4058 4059/********************************************************************** 4060 * 4061 * Update the board statistics counters. 4062 * 4063 **********************************************************************/ 4064static void 4065em_update_stats_counters(struct e1000_softc *sc) 4066{ 4067 u64 prev_xoffrxc = sc->stats.xoffrxc; 4068 4069 if(sc->hw.phy.media_type == e1000_media_type_copper || 4070 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4071 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4072 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4073 } 4074 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4075 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4076 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4077 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4078 4079 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4080 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4081 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4082 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4083 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4084 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4085 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4086 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4087 /* 4088 ** For watchdog management we need to know if we have been 4089 ** paused during the last interval, so capture that here. 4090 */ 4091 if (sc->stats.xoffrxc != prev_xoffrxc) 4092 sc->shared->isc_pause_frames = 1; 4093 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4094 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4095 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4096 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4097 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4098 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4099 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4100 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4101 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4102 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4103 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4104 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4105 4106 /* For the 64-bit byte counters the low dword must be read first. */ 4107 /* Both registers clear on the read of the high dword */ 4108 4109 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4110 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4111 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4112 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4113 4114 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4115 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4116 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4117 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4118 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4119 4120 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4121 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4122 4123 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4124 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4125 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4126 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4127 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4128 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4129 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4130 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4131 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4132 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4133 4134 /* Interrupt Counts */ 4135 4136 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4137 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4138 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4139 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4140 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4141 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4142 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4143 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4144 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4145 4146 if (sc->hw.mac.type >= e1000_82543) { 4147 sc->stats.algnerrc += 4148 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4149 sc->stats.rxerrc += 4150 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4151 sc->stats.tncrs += 4152 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4153 sc->stats.cexterr += 4154 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4155 sc->stats.tsctc += 4156 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4157 sc->stats.tsctfc += 4158 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4159 } 4160} 4161 4162static uint64_t 4163em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4164{ 4165 struct e1000_softc *sc = iflib_get_softc(ctx); 4166 struct ifnet *ifp = iflib_get_ifp(ctx); 4167 4168 switch (cnt) { 4169 case IFCOUNTER_COLLISIONS: 4170 return (sc->stats.colc); 4171 case IFCOUNTER_IERRORS: 4172 return (sc->dropped_pkts + sc->stats.rxerrc + 4173 sc->stats.crcerrs + sc->stats.algnerrc + 4174 sc->stats.ruc + sc->stats.roc + 4175 sc->stats.mpc + sc->stats.cexterr); 4176 case IFCOUNTER_OERRORS: 4177 return (sc->stats.ecol + sc->stats.latecol + 4178 sc->watchdog_events); 4179 default: 4180 return (if_get_counter_default(ifp, cnt)); 4181 } 4182} 4183 4184/* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4185 * @ctx: iflib context 4186 * @event: event code to check 4187 * 4188 * Defaults to returning true for unknown events. 4189 * 4190 * @returns true if iflib needs to reinit the interface 4191 */ 4192static bool 4193em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4194{ 4195 switch (event) { 4196 case IFLIB_RESTART_VLAN_CONFIG: 4197 return (false); 4198 default: 4199 return (true); 4200 } 4201} 4202 4203/* Export a single 32-bit register via a read-only sysctl. */ 4204static int 4205em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4206{ 4207#ifndef __HAIKU__ 4208 struct e1000_softc *sc; 4209 u_int val; 4210 4211 sc = oidp->oid_arg1; 4212 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4213 return (sysctl_handle_int(oidp, &val, 0, req)); 4214#endif 4215} 4216 4217/* 4218 * Add sysctl variables, one per statistic, to the system. 4219 */ 4220static void 4221em_add_hw_stats(struct e1000_softc *sc) 4222{ 4223#ifndef __HAIKU__ 4224 device_t dev = iflib_get_dev(sc->ctx); 4225 struct em_tx_queue *tx_que = sc->tx_queues; 4226 struct em_rx_queue *rx_que = sc->rx_queues; 4227 4228 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4229 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4230 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4231 struct e1000_hw_stats *stats = &sc->stats; 4232 4233 struct sysctl_oid *stat_node, *queue_node, *int_node; 4234 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4235 4236#define QUEUE_NAME_LEN 32 4237 char namebuf[QUEUE_NAME_LEN]; 4238 4239 /* Driver Statistics */ 4240 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4241 CTLFLAG_RD, &sc->dropped_pkts, 4242 "Driver dropped packets"); 4243 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4244 CTLFLAG_RD, &sc->link_irq, 4245 "Link MSI-X IRQ Handled"); 4246 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4247 CTLFLAG_RD, &sc->rx_overruns, 4248 "RX overruns"); 4249 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4250 CTLFLAG_RD, &sc->watchdog_events, 4251 "Watchdog timeouts"); 4252 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4253 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4254 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4255 "Device Control Register"); 4256 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4257 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4258 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4259 "Receiver Control Register"); 4260 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4261 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4262 "Flow Control High Watermark"); 4263 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4264 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4265 "Flow Control Low Watermark"); 4266 4267 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4268 struct tx_ring *txr = &tx_que->txr; 4269 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4270 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4271 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4272 queue_list = SYSCTL_CHILDREN(queue_node); 4273 4274 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4275 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4276 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4277 "Transmit Descriptor Head"); 4278 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4279 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4280 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4281 "Transmit Descriptor Tail"); 4282 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4283 CTLFLAG_RD, &txr->tx_irq, 4284 "Queue MSI-X Transmit Interrupts"); 4285 } 4286 4287 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4288 struct rx_ring *rxr = &rx_que->rxr; 4289 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4290 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4291 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4292 queue_list = SYSCTL_CHILDREN(queue_node); 4293 4294 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4295 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4296 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4297 "Receive Descriptor Head"); 4298 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4299 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4300 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4301 "Receive Descriptor Tail"); 4302 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4303 CTLFLAG_RD, &rxr->rx_irq, 4304 "Queue MSI-X Receive Interrupts"); 4305 } 4306 4307 /* MAC stats get their own sub node */ 4308 4309 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4310 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4311 stat_list = SYSCTL_CHILDREN(stat_node); 4312 4313 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4314 CTLFLAG_RD, &stats->ecol, 4315 "Excessive collisions"); 4316 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4317 CTLFLAG_RD, &stats->scc, 4318 "Single collisions"); 4319 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4320 CTLFLAG_RD, &stats->mcc, 4321 "Multiple collisions"); 4322 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4323 CTLFLAG_RD, &stats->latecol, 4324 "Late collisions"); 4325 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4326 CTLFLAG_RD, &stats->colc, 4327 "Collision Count"); 4328 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4329 CTLFLAG_RD, &sc->stats.symerrs, 4330 "Symbol Errors"); 4331 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4332 CTLFLAG_RD, &sc->stats.sec, 4333 "Sequence Errors"); 4334 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4335 CTLFLAG_RD, &sc->stats.dc, 4336 "Defer Count"); 4337 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4338 CTLFLAG_RD, &sc->stats.mpc, 4339 "Missed Packets"); 4340 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4341 CTLFLAG_RD, &sc->stats.rnbc, 4342 "Receive No Buffers"); 4343 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4344 CTLFLAG_RD, &sc->stats.ruc, 4345 "Receive Undersize"); 4346 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4347 CTLFLAG_RD, &sc->stats.rfc, 4348 "Fragmented Packets Received "); 4349 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4350 CTLFLAG_RD, &sc->stats.roc, 4351 "Oversized Packets Received"); 4352 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4353 CTLFLAG_RD, &sc->stats.rjc, 4354 "Recevied Jabber"); 4355 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4356 CTLFLAG_RD, &sc->stats.rxerrc, 4357 "Receive Errors"); 4358 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4359 CTLFLAG_RD, &sc->stats.crcerrs, 4360 "CRC errors"); 4361 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4362 CTLFLAG_RD, &sc->stats.algnerrc, 4363 "Alignment Errors"); 4364 /* On 82575 these are collision counts */ 4365 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4366 CTLFLAG_RD, &sc->stats.cexterr, 4367 "Collision/Carrier extension errors"); 4368 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4369 CTLFLAG_RD, &sc->stats.xonrxc, 4370 "XON Received"); 4371 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4372 CTLFLAG_RD, &sc->stats.xontxc, 4373 "XON Transmitted"); 4374 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4375 CTLFLAG_RD, &sc->stats.xoffrxc, 4376 "XOFF Received"); 4377 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4378 CTLFLAG_RD, &sc->stats.xofftxc, 4379 "XOFF Transmitted"); 4380 4381 /* Packet Reception Stats */ 4382 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4383 CTLFLAG_RD, &sc->stats.tpr, 4384 "Total Packets Received "); 4385 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4386 CTLFLAG_RD, &sc->stats.gprc, 4387 "Good Packets Received"); 4388 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4389 CTLFLAG_RD, &sc->stats.bprc, 4390 "Broadcast Packets Received"); 4391 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4392 CTLFLAG_RD, &sc->stats.mprc, 4393 "Multicast Packets Received"); 4394 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4395 CTLFLAG_RD, &sc->stats.prc64, 4396 "64 byte frames received "); 4397 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4398 CTLFLAG_RD, &sc->stats.prc127, 4399 "65-127 byte frames received"); 4400 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4401 CTLFLAG_RD, &sc->stats.prc255, 4402 "128-255 byte frames received"); 4403 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4404 CTLFLAG_RD, &sc->stats.prc511, 4405 "256-511 byte frames received"); 4406 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4407 CTLFLAG_RD, &sc->stats.prc1023, 4408 "512-1023 byte frames received"); 4409 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4410 CTLFLAG_RD, &sc->stats.prc1522, 4411 "1023-1522 byte frames received"); 4412 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4413 CTLFLAG_RD, &sc->stats.gorc, 4414 "Good Octets Received"); 4415 4416 /* Packet Transmission Stats */ 4417 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4418 CTLFLAG_RD, &sc->stats.gotc, 4419 "Good Octets Transmitted"); 4420 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4421 CTLFLAG_RD, &sc->stats.tpt, 4422 "Total Packets Transmitted"); 4423 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4424 CTLFLAG_RD, &sc->stats.gptc, 4425 "Good Packets Transmitted"); 4426 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4427 CTLFLAG_RD, &sc->stats.bptc, 4428 "Broadcast Packets Transmitted"); 4429 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4430 CTLFLAG_RD, &sc->stats.mptc, 4431 "Multicast Packets Transmitted"); 4432 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4433 CTLFLAG_RD, &sc->stats.ptc64, 4434 "64 byte frames transmitted "); 4435 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4436 CTLFLAG_RD, &sc->stats.ptc127, 4437 "65-127 byte frames transmitted"); 4438 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4439 CTLFLAG_RD, &sc->stats.ptc255, 4440 "128-255 byte frames transmitted"); 4441 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4442 CTLFLAG_RD, &sc->stats.ptc511, 4443 "256-511 byte frames transmitted"); 4444 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4445 CTLFLAG_RD, &sc->stats.ptc1023, 4446 "512-1023 byte frames transmitted"); 4447 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4448 CTLFLAG_RD, &sc->stats.ptc1522, 4449 "1024-1522 byte frames transmitted"); 4450 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4451 CTLFLAG_RD, &sc->stats.tsctc, 4452 "TSO Contexts Transmitted"); 4453 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4454 CTLFLAG_RD, &sc->stats.tsctfc, 4455 "TSO Contexts Failed"); 4456 4457 4458 /* Interrupt Stats */ 4459 4460 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4461 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4462 int_list = SYSCTL_CHILDREN(int_node); 4463 4464 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4465 CTLFLAG_RD, &sc->stats.iac, 4466 "Interrupt Assertion Count"); 4467 4468 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4469 CTLFLAG_RD, &sc->stats.icrxptc, 4470 "Interrupt Cause Rx Pkt Timer Expire Count"); 4471 4472 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4473 CTLFLAG_RD, &sc->stats.icrxatc, 4474 "Interrupt Cause Rx Abs Timer Expire Count"); 4475 4476 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4477 CTLFLAG_RD, &sc->stats.ictxptc, 4478 "Interrupt Cause Tx Pkt Timer Expire Count"); 4479 4480 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4481 CTLFLAG_RD, &sc->stats.ictxatc, 4482 "Interrupt Cause Tx Abs Timer Expire Count"); 4483 4484 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4485 CTLFLAG_RD, &sc->stats.ictxqec, 4486 "Interrupt Cause Tx Queue Empty Count"); 4487 4488 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4489 CTLFLAG_RD, &sc->stats.ictxqmtc, 4490 "Interrupt Cause Tx Queue Min Thresh Count"); 4491 4492 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4493 CTLFLAG_RD, &sc->stats.icrxdmtc, 4494 "Interrupt Cause Rx Desc Min Thresh Count"); 4495 4496 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4497 CTLFLAG_RD, &sc->stats.icrxoc, 4498 "Interrupt Cause Receiver Overrun Count"); 4499#endif 4500} 4501 4502static void 4503em_fw_version_locked(if_ctx_t ctx) 4504{ 4505 struct e1000_softc *sc = iflib_get_softc(ctx); 4506 struct e1000_hw *hw = &sc->hw; 4507 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4508 uint16_t eep = 0; 4509 4510 /* 4511 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4512 * NVM locking model, so we do it in em_if_attach_pre() and store the 4513 * info in the softc 4514 */ 4515 ASSERT_CTX_LOCK_HELD(hw); 4516 4517 *fw_ver = (struct e1000_fw_version){0}; 4518 4519 if (hw->mac.type >= igb_mac_min) { 4520 /* 4521 * Use the Shared Code for igb(4) 4522 */ 4523 e1000_get_fw_version(hw, fw_ver); 4524 } else { 4525 /* 4526 * Otherwise, EEPROM version should be present on (almost?) all 4527 * devices here 4528 */ 4529 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4530 INIT_DEBUGOUT("can't get EEPROM version"); 4531 return; 4532 } 4533 4534 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4535 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4536 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4537 } 4538} 4539 4540static void 4541em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4542{ 4543 const char *space = ""; 4544 4545 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4546 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4547 fw_ver->eep_minor, fw_ver->eep_build); 4548 space = " "; 4549 } 4550 4551 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4552 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4553 space, fw_ver->invm_major, fw_ver->invm_minor, 4554 fw_ver->invm_img_type); 4555 space = " "; 4556 } 4557 4558 if (fw_ver->or_valid) { 4559 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4560 space, fw_ver->or_major, fw_ver->or_build, 4561 fw_ver->or_patch); 4562 space = " "; 4563 } 4564 4565 if (fw_ver->etrack_id) 4566 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4567} 4568 4569static void 4570em_print_fw_version(struct e1000_softc *sc ) 4571{ 4572 device_t dev = sc->dev; 4573 struct sbuf *buf; 4574 int error = 0; 4575 4576 buf = sbuf_new_auto(); 4577 if (!buf) { 4578 device_printf(dev, "Could not allocate sbuf for output.\n"); 4579 return; 4580 } 4581 4582 em_sbuf_fw_version(&sc->fw_ver, buf); 4583 4584 error = sbuf_finish(buf); 4585 if (error) 4586 device_printf(dev, "Error finishing sbuf: %d\n", error); 4587 else if (sbuf_len(buf)) 4588 device_printf(dev, "%s\n", sbuf_data(buf)); 4589 4590 sbuf_delete(buf); 4591} 4592 4593static int 4594em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4595{ 4596 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4597 device_t dev = sc->dev; 4598 struct sbuf *buf; 4599 int error = 0; 4600 4601 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4602 if (!buf) { 4603 device_printf(dev, "Could not allocate sbuf for output.\n"); 4604 return (ENOMEM); 4605 } 4606 4607 em_sbuf_fw_version(&sc->fw_ver, buf); 4608 4609 error = sbuf_finish(buf); 4610 if (error) 4611 device_printf(dev, "Error finishing sbuf: %d\n", error); 4612 4613 sbuf_delete(buf); 4614 4615 return (0); 4616} 4617 4618/********************************************************************** 4619 * 4620 * This routine provides a way to dump out the adapter eeprom, 4621 * often a useful debug/service tool. This only dumps the first 4622 * 32 words, stuff that matters is in that extent. 4623 * 4624 **********************************************************************/ 4625static int 4626em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4627{ 4628 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4629 int error; 4630 int result; 4631 4632 result = -1; 4633 error = sysctl_handle_int(oidp, &result, 0, req); 4634 4635 if (error || !req->newptr) 4636 return (error); 4637 4638 /* 4639 * This value will cause a hex dump of the 4640 * first 32 16-bit words of the EEPROM to 4641 * the screen. 4642 */ 4643 if (result == 1) 4644 em_print_nvm_info(sc); 4645 4646 return (error); 4647} 4648 4649static void 4650em_print_nvm_info(struct e1000_softc *sc) 4651{ 4652 struct e1000_hw *hw = &sc->hw; 4653 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4654 u16 eeprom_data; 4655 int i, j, row = 0; 4656 4657 /* Its a bit crude, but it gets the job done */ 4658 printf("\nInterface EEPROM Dump:\n"); 4659 printf("Offset\n0x0000 "); 4660 4661 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4662 sx_xlock(iflib_ctx_lock); 4663 ASSERT_CTX_LOCK_HELD(hw); 4664 for (i = 0, j = 0; i < 32; i++, j++) { 4665 if (j == 8) { /* Make the offset block */ 4666 j = 0; ++row; 4667 printf("\n0x00%x0 ",row); 4668 } 4669 e1000_read_nvm(hw, i, 1, &eeprom_data); 4670 printf("%04x ", eeprom_data); 4671 } 4672 sx_xunlock(iflib_ctx_lock); 4673 printf("\n"); 4674} 4675 4676static int 4677em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4678{ 4679#ifndef __HAIKU__ 4680 struct em_int_delay_info *info; 4681 struct e1000_softc *sc; 4682 u32 regval; 4683 int error, usecs, ticks; 4684 4685 info = (struct em_int_delay_info *) arg1; 4686 usecs = info->value; 4687 error = sysctl_handle_int(oidp, &usecs, 0, req); 4688 if (error != 0 || req->newptr == NULL) 4689 return (error); 4690 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4691 return (EINVAL); 4692 info->value = usecs; 4693 ticks = EM_USECS_TO_TICKS(usecs); 4694 if (info->offset == E1000_ITR) /* units are 256ns here */ 4695 ticks *= 4; 4696 4697 sc = info->sc; 4698 4699 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4700 regval = (regval & ~0xffff) | (ticks & 0xffff); 4701 /* Handle a few special cases. */ 4702 switch (info->offset) { 4703 case E1000_RDTR: 4704 break; 4705 case E1000_TIDV: 4706 if (ticks == 0) { 4707 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4708 /* Don't write 0 into the TIDV register. */ 4709 regval++; 4710 } else 4711 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4712 break; 4713 } 4714 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4715 return (0); 4716#endif 4717} 4718 4719static void 4720em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4721 const char *description, struct em_int_delay_info *info, 4722 int offset, int value) 4723{ 4724 info->sc = sc; 4725 info->offset = offset; 4726 info->value = value; 4727 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4728 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4729 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4730 info, 0, em_sysctl_int_delay, "I", description); 4731} 4732 4733/* 4734 * Set flow control using sysctl: 4735 * Flow control values: 4736 * 0 - off 4737 * 1 - rx pause 4738 * 2 - tx pause 4739 * 3 - full 4740 */ 4741static int 4742em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4743{ 4744 int error; 4745 static int input = 3; /* default is full */ 4746 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4747 4748 error = sysctl_handle_int(oidp, &input, 0, req); 4749 4750 if ((error) || (req->newptr == NULL)) 4751 return (error); 4752 4753 if (input == sc->fc) /* no change? */ 4754 return (error); 4755 4756 switch (input) { 4757 case e1000_fc_rx_pause: 4758 case e1000_fc_tx_pause: 4759 case e1000_fc_full: 4760 case e1000_fc_none: 4761 sc->hw.fc.requested_mode = input; 4762 sc->fc = input; 4763 break; 4764 default: 4765 /* Do nothing */ 4766 return (error); 4767 } 4768 4769 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4770 e1000_force_mac_fc(&sc->hw); 4771 return (error); 4772} 4773 4774/* 4775 * Manage Energy Efficient Ethernet: 4776 * Control values: 4777 * 0/1 - enabled/disabled 4778 */ 4779static int 4780em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4781{ 4782 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4783 int error, value; 4784 4785 value = sc->hw.dev_spec.ich8lan.eee_disable; 4786 error = sysctl_handle_int(oidp, &value, 0, req); 4787 if (error || req->newptr == NULL) 4788 return (error); 4789 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4790 em_if_init(sc->ctx); 4791 4792 return (0); 4793} 4794 4795static int 4796em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4797{ 4798 struct e1000_softc *sc; 4799 int error; 4800 int result; 4801 4802 result = -1; 4803 error = sysctl_handle_int(oidp, &result, 0, req); 4804 4805 if (error || !req->newptr) 4806 return (error); 4807 4808 if (result == 1) { 4809 sc = (struct e1000_softc *) arg1; 4810 em_print_debug_info(sc); 4811 } 4812 4813 return (error); 4814} 4815 4816static int 4817em_get_rs(SYSCTL_HANDLER_ARGS) 4818{ 4819 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4820 int error; 4821 int result; 4822 4823 result = 0; 4824 error = sysctl_handle_int(oidp, &result, 0, req); 4825 4826 if (error || !req->newptr || result != 1) 4827 return (error); 4828 em_dump_rs(sc); 4829 4830 return (error); 4831} 4832 4833static void 4834em_if_debug(if_ctx_t ctx) 4835{ 4836 em_dump_rs(iflib_get_softc(ctx)); 4837} 4838 4839/* 4840 * This routine is meant to be fluid, add whatever is 4841 * needed for debugging a problem. -jfv 4842 */ 4843static void 4844em_print_debug_info(struct e1000_softc *sc) 4845{ 4846 device_t dev = iflib_get_dev(sc->ctx); 4847 struct ifnet *ifp = iflib_get_ifp(sc->ctx); 4848 struct tx_ring *txr = &sc->tx_queues->txr; 4849 struct rx_ring *rxr = &sc->rx_queues->rxr; 4850 4851 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4852 printf("Interface is RUNNING "); 4853 else 4854 printf("Interface is NOT RUNNING\n"); 4855 4856 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4857 printf("and INACTIVE\n"); 4858 else 4859 printf("and ACTIVE\n"); 4860 4861 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 4862 device_printf(dev, "TX Queue %d ------\n", i); 4863 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4864 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 4865 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 4866 4867 } 4868 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 4869 device_printf(dev, "RX Queue %d ------\n", j); 4870 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4871 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 4872 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 4873 } 4874} 4875 4876/* 4877 * 82574 only: 4878 * Write a new value to the EEPROM increasing the number of MSI-X 4879 * vectors from 3 to 5, for proper multiqueue support. 4880 */ 4881static void 4882em_enable_vectors_82574(if_ctx_t ctx) 4883{ 4884 struct e1000_softc *sc = iflib_get_softc(ctx); 4885 struct e1000_hw *hw = &sc->hw; 4886 device_t dev = iflib_get_dev(ctx); 4887 u16 edata; 4888 4889 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4890 if (bootverbose) 4891 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4892 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4893 device_printf(dev, "Writing to eeprom: increasing " 4894 "reported MSI-X vectors from 3 to 5...\n"); 4895 edata &= ~(EM_NVM_MSIX_N_MASK); 4896 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4897 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4898 e1000_update_nvm_checksum(hw); 4899 device_printf(dev, "Writing to eeprom: done\n"); 4900 } 4901} 4902