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33******************************************************************************/
34/*$FreeBSD$*/
35
36#ifndef _E1000_VF_H_
37#define _E1000_VF_H_
38
39#include "e1000_osdep.h"
40#include "e1000_regs.h"
41#include "e1000_defines.h"
42
43struct e1000_hw;
44
45#define E1000_DEV_ID_82576_VF		0x10CA
46#define E1000_DEV_ID_I350_VF		0x1520
47
48#define E1000_VF_INIT_TIMEOUT		200 /* Num of retries to clear RSTI */
49
50/* Additional Descriptor Control definitions */
51#define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
52#define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
53
54/* SRRCTL bit definitions */
55#define E1000_SRRCTL(_n)	((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
56				 (0x0C00C + ((_n) * 0x40)))
57#define E1000_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
58#define E1000_SRRCTL_BSIZEHDRSIZE_MASK		0x00000F00
59#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
60#define E1000_SRRCTL_DESCTYPE_LEGACY		0x00000000
61#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
62#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT		0x04000000
63#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS	0x0A000000
64#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION	0x06000000
65#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
66#define E1000_SRRCTL_DESCTYPE_MASK		0x0E000000
67#define E1000_SRRCTL_DROP_EN			0x80000000
68
69#define E1000_SRRCTL_BSIZEPKT_MASK	0x0000007F
70#define E1000_SRRCTL_BSIZEHDR_MASK	0x00003F00
71
72/* Interrupt Defines */
73#define E1000_EICR		0x01580 /* Ext. Interrupt Cause Read - R/clr */
74#define E1000_EITR(_n)		(0x01680 + ((_n) << 2))
75#define E1000_EICS		0x01520 /* Ext. Intr Cause Set -W0 */
76#define E1000_EIMS		0x01524 /* Ext. Intr Mask Set/Read -RW */
77#define E1000_EIMC		0x01528 /* Ext. Intr Mask Clear -WO */
78#define E1000_EIAC		0x0152C /* Ext. Intr Auto Clear -RW */
79#define E1000_EIAM		0x01530 /* Ext. Intr Ack Auto Clear Mask -RW */
80#define E1000_IVAR0		0x01700 /* Intr Vector Alloc (array) -RW */
81#define E1000_IVAR_MISC		0x01740 /* IVAR for "other" causes -RW */
82#define E1000_IVAR_VALID	0x80
83
84/* Receive Descriptor - Advanced */
85union e1000_adv_rx_desc {
86	struct {
87		u64 pkt_addr; /* Packet buffer address */
88		u64 hdr_addr; /* Header buffer address */
89	} read;
90	struct {
91		struct {
92			union {
93				u32 data;
94				struct {
95					/* RSS type, Packet type */
96					u16 pkt_info;
97					/* Split Header, header buffer len */
98					u16 hdr_info;
99				} hs_rss;
100			} lo_dword;
101			union {
102				u32 rss; /* RSS Hash */
103				struct {
104					u16 ip_id; /* IP id */
105					u16 csum; /* Packet Checksum */
106				} csum_ip;
107			} hi_dword;
108		} lower;
109		struct {
110			u32 status_error; /* ext status/error */
111			u16 length; /* Packet length */
112			u16 vlan; /* VLAN tag */
113		} upper;
114	} wb;  /* writeback */
115};
116
117#define E1000_RXDADV_HDRBUFLEN_MASK	0x7FE0
118#define E1000_RXDADV_HDRBUFLEN_SHIFT	5
119
120/* Transmit Descriptor - Advanced */
121union e1000_adv_tx_desc {
122	struct {
123		u64 buffer_addr;    /* Address of descriptor's data buf */
124		u32 cmd_type_len;
125		u32 olinfo_status;
126	} read;
127	struct {
128		u64 rsvd;       /* Reserved */
129		u32 nxtseq_seed;
130		u32 status;
131	} wb;
132};
133
134/* Adv Transmit Descriptor Config Masks */
135#define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
136#define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
137#define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
138#define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
139#define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
140#define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
141#define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
142#define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
143#define E1000_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
144
145/* Context descriptors */
146struct e1000_adv_tx_context_desc {
147	u32 vlan_macip_lens;
148	u32 seqnum_seed;
149	u32 type_tucmd_mlhl;
150	u32 mss_l4len_idx;
151};
152
153#define E1000_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
154#define E1000_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type: 1=IPv4 */
155#define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet TYPE of TCP */
156#define E1000_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
157#define E1000_ADVTXD_MSS_SHIFT		16  /* Adv ctxt MSS shift */
158
159enum e1000_mac_type {
160	e1000_undefined = 0,
161	e1000_vfadapt,
162	e1000_vfadapt_i350,
163	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
164};
165
166struct e1000_vf_stats {
167	u64 base_gprc;
168	u64 base_gptc;
169	u64 base_gorc;
170	u64 base_gotc;
171	u64 base_mprc;
172	u64 base_gotlbc;
173	u64 base_gptlbc;
174	u64 base_gorlbc;
175	u64 base_gprlbc;
176
177	u32 last_gprc;
178	u32 last_gptc;
179	u32 last_gorc;
180	u32 last_gotc;
181	u32 last_mprc;
182	u32 last_gotlbc;
183	u32 last_gptlbc;
184	u32 last_gorlbc;
185	u32 last_gprlbc;
186
187	u64 gprc;
188	u64 gptc;
189	u64 gorc;
190	u64 gotc;
191	u64 mprc;
192	u64 gotlbc;
193	u64 gptlbc;
194	u64 gorlbc;
195	u64 gprlbc;
196};
197
198#include "e1000_mbx.h"
199
200struct e1000_mac_operations {
201	/* Function pointers for the MAC. */
202	s32  (*init_params)(struct e1000_hw *);
203	s32  (*check_for_link)(struct e1000_hw *);
204	void (*clear_vfta)(struct e1000_hw *);
205	s32  (*get_bus_info)(struct e1000_hw *);
206	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
207	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
208	s32  (*reset_hw)(struct e1000_hw *);
209	s32  (*init_hw)(struct e1000_hw *);
210	s32  (*setup_link)(struct e1000_hw *);
211	void (*write_vfta)(struct e1000_hw *, u32, u32);
212	int  (*rar_set)(struct e1000_hw *, u8*, u32);
213	s32  (*read_mac_addr)(struct e1000_hw *);
214};
215
216struct e1000_mac_info {
217	struct e1000_mac_operations ops;
218	u8 addr[6];
219	u8 perm_addr[6];
220
221	enum e1000_mac_type type;
222
223	u16 mta_reg_count;
224	u16 rar_entry_count;
225
226	bool get_link_status;
227};
228
229struct e1000_mbx_operations {
230	s32 (*init_params)(struct e1000_hw *hw);
231	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
232	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
233	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
234	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
235	s32 (*check_for_msg)(struct e1000_hw *, u16);
236	s32 (*check_for_ack)(struct e1000_hw *, u16);
237	s32 (*check_for_rst)(struct e1000_hw *, u16);
238};
239
240struct e1000_mbx_stats {
241	u32 msgs_tx;
242	u32 msgs_rx;
243
244	u32 acks;
245	u32 reqs;
246	u32 rsts;
247};
248
249struct e1000_mbx_info {
250	struct e1000_mbx_operations ops;
251	struct e1000_mbx_stats stats;
252	u32 timeout;
253	u32 usec_delay;
254	u16 size;
255};
256
257struct e1000_dev_spec_vf {
258	u32 vf_number;
259	u32 v2p_mailbox;
260};
261
262struct e1000_hw {
263	void *back;
264
265	u8 *hw_addr;
266	u8 *flash_address;
267	unsigned long io_base;
268
269	struct e1000_mac_info  mac;
270	struct e1000_mbx_info mbx;
271
272	union {
273		struct e1000_dev_spec_vf vf;
274	} dev_spec;
275
276	u16 device_id;
277	u16 subsystem_vendor_id;
278	u16 subsystem_device_id;
279	u16 vendor_id;
280
281	u8  revision_id;
282};
283
284enum e1000_promisc_type {
285	e1000_promisc_disabled = 0,   /* all promisc modes disabled */
286	e1000_promisc_unicast = 1,    /* unicast promiscuous enabled */
287	e1000_promisc_multicast = 2,  /* multicast promiscuous enabled */
288	e1000_promisc_enabled = 3,    /* both uni and multicast promisc */
289	e1000_num_promisc_types
290};
291
292/* These functions must be implemented by drivers */
293s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
294void e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
295void e1000_rlpml_set_vf(struct e1000_hw *, u16);
296s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
297#endif /* _E1000_VF_H_ */
298