1/******************************************************************************
2  SPDX-License-Identifier: BSD-3-Clause
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4  Copyright (c) 2001-2020, Intel Corporation
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33******************************************************************************/
34/*$FreeBSD$*/
35
36#ifndef _E1000_MANAGE_H_
37#define _E1000_MANAGE_H_
38
39bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
40bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
41s32  e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
42s32  e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
43				     u16 length, u16 offset, u8 *sum);
44s32  e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
45				     struct e1000_host_mng_command_header *hdr);
46s32  e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
47				       u8 *buffer, u16 length);
48bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
49u8 e1000_calculate_checksum(u8 *buffer, u32 length);
50s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);
51s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);
52
53enum e1000_mng_mode {
54	e1000_mng_mode_none = 0,
55	e1000_mng_mode_asf,
56	e1000_mng_mode_pt,
57	e1000_mng_mode_ipmi,
58	e1000_mng_mode_host_if_only
59};
60
61#define E1000_FACTPS_MNGCG			0x20000000
62
63#define E1000_FWSM_MODE_MASK			0xE
64#define E1000_FWSM_MODE_SHIFT			1
65#define E1000_FWSM_FW_VALID			0x00008000
66#define E1000_FWSM_HI_EN_ONLY_MODE		0x4
67
68#define E1000_MNG_IAMT_MODE			0x3
69#define E1000_MNG_DHCP_COOKIE_LENGTH		0x10
70#define E1000_MNG_DHCP_COOKIE_OFFSET		0x6F0
71#define E1000_MNG_DHCP_COMMAND_TIMEOUT		10
72#define E1000_MNG_DHCP_TX_PAYLOAD_CMD		64
73#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING	0x1
74#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN	0x2
75
76#define E1000_VFTA_ENTRY_SHIFT			5
77#define E1000_VFTA_ENTRY_MASK			0x7F
78#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK		0x1F
79
80#define E1000_HI_MAX_BLOCK_BYTE_LENGTH		1792 /* Num of bytes in range */
81#define E1000_HI_MAX_BLOCK_DWORD_LENGTH		448 /* Num of dwords in range */
82#define E1000_HI_COMMAND_TIMEOUT		500 /* Process HI cmd limit */
83#define E1000_HI_FW_BASE_ADDRESS		0x10000
84#define E1000_HI_FW_MAX_LENGTH			(64 * 1024) /* Num of bytes */
85#define E1000_HI_FW_BLOCK_DWORD_LENGTH		256 /* Num of DWORDs per page */
86#define E1000_HICR_MEMORY_BASE_EN		0x200 /* MB Enable bit - RO */
87#define E1000_HICR_EN			0x01  /* Enable bit - RO */
88/* Driver sets this bit when done to put command in RAM */
89#define E1000_HICR_C			0x02
90#define E1000_HICR_SV			0x04  /* Status Validity */
91#define E1000_HICR_FW_RESET_ENABLE	0x40
92#define E1000_HICR_FW_RESET		0x80
93
94/* Intel(R) Active Management Technology signature */
95#define E1000_IAMT_SIGNATURE		0x544D4149
96
97#endif
98