1/*- 2SPDX-License-Identifier: BSD-3-Clause 3 4Copyright (c) 1999-2001, Intel Corporation 5 6All rights reserved. 7 8Redistribution and use in source and binary forms, with or without 9modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright notice, 15 this list of conditions and the following disclaimer in the documentation 16 and/or other materials provided with the distribution. 17 18 3. Neither the name of Intel Corporation nor the names of its contributors 19 may be used to endorse or promote products derived from this software 20 without specific prior written permission. 21 22THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 23AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 28PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 29LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 31EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32*/ 33/* 34 * $FreeBSD: releng/12.0/sys/dev/fxp/rcvbundl.h 326022 2017-11-20 19:36:21Z pfg $ 35 */ 36/* 37rcvbundl.h 38 39Author: Patrick J Luhmann (PJL) 40Date: 05/30/2000 41Version: 3.28 42 43This file contains the loadable micro code arrays to implement receive bundling on the 44D101 A-step, D101 B-step, D101M (B-step only), D101S, D102 B-step, 45D102 B-step with TCO work around, D102 C-step and D102 E-step. 46 47Each controller has its own specific micro code array. The array for one controller 48is totally incompatible with any other controller, and if used will most likely 49cause the controller to lock up and stop responding to the driver. Each micro 50code array has its own parameter offsets (described below), and they each have 51their own version number (which should not be confused with the version of the 52rcvbundl.h file given above). 53 54*/ 55 56 57 58/************************************************************************* 59* CPUSaver parameters 60* 61* All CPUSaver parameters are 16-bit literals that are part of a 62* "move immediate value" instruction. By changing the value of 63* the literal in the instruction before the code is loaded, the 64* driver can change algorithm. 65* 66* CPUSAVER_DWORD - This is the location of the instruction that loads 67* the dead-man timer with its initial value. By writing a 16-bit 68* value to the low word of this instruction, the driver can change 69* the timer value. The current default is either x600 or x800; 70* experiments show that the value probably should stay within the 71* range of x200 - x1000. 72* 73* CPUSAVER_BUNDLE_MAX_DWORD - This is the location of the instruction 74* that sets the maximum number of frames that will be bundled. In 75* some situations, such as the TCP windowing algorithm, it may be 76* better to limit the growth of the bundle size than let it go as 77* high as it can, because that could cause too much added latency. 78* The default is six, because this is the number of packets in the 79* default TCP window size. A value of 1 would make CPUSaver indicate 80* an interrupt for every frame received. If you do not want to put 81* a limit on the bundle size, set this value to xFFFF. 82* 83* CPUSAVER_MIN_SIZE_DWORD - This is the location of the instruction 84* that contains a bit-mask describing the minimum size frame that 85* will be bundled. The default masks the lower 7 bits, which means 86* that any frame less than 128 bytes in length will not be bundled, 87* but will instead immediately generate an interrupt. This does 88* not affect the current bundle in any way. Any frame that is 128 89* bytes or large will be bundled normally. This feature is meant 90* to provide immediate indication of ACK frames in a TCP environment. 91* Customers were seeing poor performance when a machine with CPUSaver 92* enabled was sending but not receiving. The delay introduced when 93* the ACKs were received was enough to reduce total throughput, because 94* the sender would sit idle until the ACK was finally seen. 95* 96* The current default is 0xFF80, which masks out the lower 7 bits. 97* This means that any frame which is x7F (127) bytes or smaller 98* will cause an immediate interrupt. Because this value must be a 99* bit mask, there are only a few valid values that can be used. To 100* turn this feature off, the driver can write the value xFFFF to the 101* lower word of this instruction (in the same way that the other 102* parameters are used). Likewise, a value of 0xF800 (2047) would 103* cause an interrupt to be generated for every frame, because all 104* standard Ethernet frames are <= 2047 bytes in length. 105*************************************************************************/ 106 107 108 109/********************************************************/ 110/* CPUSaver micro code for the D101A */ 111/********************************************************/ 112 113/* Version 2.0 */ 114 115/* This value is the same for both A and B step of 558. */ 116#define D101_CPUSAVER_DWORD 72 117 118 119#define D101_A_RCVBUNDLE_UCODE \ 120{\ 1210x03B301BB, \ 1220x0046FFFF, \ 1230xFFFFFFFF, \ 1240x051DFFFF, \ 1250xFFFFFFFF, \ 1260xFFFFFFFF, \ 1270x000C0001, \ 1280x00101212, \ 1290x000C0008, \ 1300x003801BC, \ 1310x00000000, \ 1320x00124818, \ 1330x000C1000, \ 1340x00220809, \ 1350x00010200, \ 1360x00124818, \ 1370x000CFFFC, \ 1380x003803B5, \ 1390x00000000, \ 1400x00000000, \ 1410x00000000, \ 1420x00000000, \ 1430x0010009C, \ 1440x0024B81D, \ 1450x00130836, \ 1460x000C0001, \ 1470x0026081C, \ 1480x0020C81B, \ 1490x00130824, \ 1500x00222819, \ 1510x00101213, \ 1520x00041000, \ 1530x003A03B3, \ 1540x00010200, \ 1550x00101B13, \ 1560x00238081, \ 1570x00213049, \ 1580x0038003B, \ 1590x00000000, \ 1600x00000000, \ 1610x00000000, \ 1620x00000000, \ 1630x00000000, \ 1640x00000000, \ 1650x00000000, \ 1660x00000000, \ 1670x00000000, \ 1680x00000000, \ 1690x00000000, \ 1700x00000000, \ 1710x00000000, \ 1720x00000000, \ 1730x00000000, \ 1740x00000000, \ 1750x0010009C, \ 1760x0024B83E, \ 1770x00130826, \ 1780x000C0001, \ 1790x0026083B, \ 1800x00010200, \ 1810x00134824, \ 1820x000C0001, \ 1830x00101213, \ 1840x00041000, \ 1850x0038051E, \ 1860x00101313, \ 1870x00010400, \ 1880x00380521, \ 1890x00050600, \ 1900x00100824, \ 1910x00101310, \ 1920x00041000, \ 1930x00080600, \ 1940x00101B10, \ 1950x0038051E, \ 1960x00000000, \ 1970x00000000, \ 1980x00000000, \ 1990x00000000, \ 2000x00000000, \ 2010x00000000, \ 2020x00000000, \ 2030x00000000, \ 2040x00000000, \ 2050x00000000, \ 2060x00000000, \ 2070x00000000, \ 2080x00000000, \ 2090x00000000, \ 2100x00000000, \ 2110x00000000, \ 2120x00000000, \ 2130x00000000, \ 2140x00000000, \ 2150x00000000, \ 2160x00000000, \ 2170x00000000, \ 2180x00000000, \ 2190x00000000, \ 2200x00000000, \ 2210x00000000, \ 2220x00000000, \ 223} 224 225 226/********************************************************/ 227/* CPUSaver micro code for the D101B */ 228/********************************************************/ 229 230/* Version 2.0 */ 231 232#define D101_B0_RCVBUNDLE_UCODE \ 233{\ 2340x03B401BC, \ 2350x0047FFFF, \ 2360xFFFFFFFF, \ 2370x051EFFFF, \ 2380xFFFFFFFF, \ 2390xFFFFFFFF, \ 2400x000C0001, \ 2410x00101B92, \ 2420x000C0008, \ 2430x003801BD, \ 2440x00000000, \ 2450x00124818, \ 2460x000C1000, \ 2470x00220809, \ 2480x00010200, \ 2490x00124818, \ 2500x000CFFFC, \ 2510x003803B6, \ 2520x00000000, \ 2530x00000000, \ 2540x00000000, \ 2550x00000000, \ 2560x0010009C, \ 2570x0024B81D, \ 2580x0013082F, \ 2590x000C0001, \ 2600x0026081C, \ 2610x0020C81B, \ 2620x00130837, \ 2630x00222819, \ 2640x00101B93, \ 2650x00041000, \ 2660x003A03B4, \ 2670x00010200, \ 2680x00101793, \ 2690x00238082, \ 2700x0021304A, \ 2710x0038003C, \ 2720x00000000, \ 2730x00000000, \ 2740x00000000, \ 2750x00000000, \ 2760x00000000, \ 2770x00000000, \ 2780x00000000, \ 2790x00000000, \ 2800x00000000, \ 2810x00000000, \ 2820x00000000, \ 2830x00000000, \ 2840x00000000, \ 2850x00000000, \ 2860x00000000, \ 2870x00000000, \ 2880x0010009C, \ 2890x0024B83E, \ 2900x00130826, \ 2910x000C0001, \ 2920x0026083B, \ 2930x00010200, \ 2940x00134837, \ 2950x000C0001, \ 2960x00101B93, \ 2970x00041000, \ 2980x0038051F, \ 2990x00101313, \ 3000x00010400, \ 3010x00380522, \ 3020x00050600, \ 3030x00100837, \ 3040x00101310, \ 3050x00041000, \ 3060x00080600, \ 3070x00101790, \ 3080x0038051F, \ 3090x00000000, \ 3100x00000000, \ 3110x00000000, \ 3120x00000000, \ 3130x00000000, \ 3140x00000000, \ 3150x00000000, \ 3160x00000000, \ 3170x00000000, \ 3180x00000000, \ 3190x00000000, \ 3200x00000000, \ 3210x00000000, \ 3220x00000000, \ 3230x00000000, \ 3240x00000000, \ 3250x00000000, \ 3260x00000000, \ 3270x00000000, \ 3280x00000000, \ 3290x00000000, \ 3300x00000000, \ 3310x00000000, \ 3320x00000000, \ 3330x00000000, \ 3340x00000000, \ 3350x00000000, \ 336} 337 338 339/********************************************************/ 340/* CPUSaver micro code for the D101M (B-step only) */ 341/********************************************************/ 342 343/* Version 2.10 */ 344 345/* Parameter values for the D101M B-step */ 346#define D101M_CPUSAVER_DWORD 78 347#define D101M_CPUSAVER_BUNDLE_MAX_DWORD 65 348#define D101M_CPUSAVER_MIN_SIZE_DWORD 126 349 350 351#define D101M_B_RCVBUNDLE_UCODE \ 352{\ 3530x00550215, \ 3540xFFFF0437, \ 3550xFFFFFFFF, \ 3560x06A70789, \ 3570xFFFFFFFF, \ 3580x0558FFFF, \ 3590x000C0001, \ 3600x00101312, \ 3610x000C0008, \ 3620x00380216, \ 3630x0010009C, \ 3640x00204056, \ 3650x002380CC, \ 3660x00380056, \ 3670x0010009C, \ 3680x00244C0B, \ 3690x00000800, \ 3700x00124818, \ 3710x00380438, \ 3720x00000000, \ 3730x00140000, \ 3740x00380555, \ 3750x00308000, \ 3760x00100662, \ 3770x00100561, \ 3780x000E0408, \ 3790x00134861, \ 3800x000C0002, \ 3810x00103093, \ 3820x00308000, \ 3830x00100624, \ 3840x00100561, \ 3850x000E0408, \ 3860x00100861, \ 3870x000C007E, \ 3880x00222C21, \ 3890x000C0002, \ 3900x00103093, \ 3910x00380C7A, \ 3920x00080000, \ 3930x00103090, \ 3940x00380C7A, \ 3950x00000000, \ 3960x00000000, \ 3970x00000000, \ 3980x00000000, \ 3990x0010009C, \ 4000x00244C2D, \ 4010x00010004, \ 4020x00041000, \ 4030x003A0437, \ 4040x00044010, \ 4050x0038078A, \ 4060x00000000, \ 4070x00100099, \ 4080x00206C7A, \ 4090x0010009C, \ 4100x00244C48, \ 4110x00130824, \ 4120x000C0001, \ 4130x00101213, \ 4140x00260C75, \ 4150x00041000, \ 4160x00010004, \ 4170x00130826, \ 4180x000C0006, \ 4190x002206A8, \ 4200x0013C926, \ 4210x00101313, \ 4220x003806A8, \ 4230x00000000, \ 4240x00000000, \ 4250x00000000, \ 4260x00000000, \ 4270x00000000, \ 4280x00000000, \ 4290x00000000, \ 4300x00000000, \ 4310x00080600, \ 4320x00101B10, \ 4330x00050004, \ 4340x00100826, \ 4350x00101210, \ 4360x00380C34, \ 4370x00000000, \ 4380x00000000, \ 4390x0021155B, \ 4400x00100099, \ 4410x00206559, \ 4420x0010009C, \ 4430x00244559, \ 4440x00130836, \ 4450x000C0000, \ 4460x00220C62, \ 4470x000C0001, \ 4480x00101B13, \ 4490x00229C0E, \ 4500x00210C0E, \ 4510x00226C0E, \ 4520x00216C0E, \ 4530x0022FC0E, \ 4540x00215C0E, \ 4550x00214C0E, \ 4560x00380555, \ 4570x00010004, \ 4580x00041000, \ 4590x00278C67, \ 4600x00040800, \ 4610x00018100, \ 4620x003A0437, \ 4630x00130826, \ 4640x000C0001, \ 4650x00220559, \ 4660x00101313, \ 4670x00380559, \ 4680x00000000, \ 4690x00000000, \ 4700x00000000, \ 4710x00000000, \ 4720x00000000, \ 4730x00000000, \ 4740x00000000, \ 4750x00000000, \ 4760x00130831, \ 4770x0010090B, \ 4780x00124813, \ 4790x000CFF80, \ 4800x002606AB, \ 4810x00041000, \ 4820x003806A8, \ 4830x00000000, \ 4840x00000000, \ 4850x00000000, \ 4860x00000000, \ 487} 488 489 490/********************************************************/ 491/* CPUSaver micro code for the D101S */ 492/********************************************************/ 493 494/* Version 1.20 */ 495 496/* Parameter values for the D101S */ 497#define D101S_CPUSAVER_DWORD 78 498#define D101S_CPUSAVER_BUNDLE_MAX_DWORD 67 499#define D101S_CPUSAVER_MIN_SIZE_DWORD 129 500 501 502#define D101S_RCVBUNDLE_UCODE \ 503{\ 5040x00550242, \ 5050xFFFF047E, \ 5060xFFFFFFFF, \ 5070x06FF0818, \ 5080xFFFFFFFF, \ 5090x05A6FFFF, \ 5100x000C0001, \ 5110x00101312, \ 5120x000C0008, \ 5130x00380243, \ 5140x0010009C, \ 5150x00204056, \ 5160x002380D0, \ 5170x00380056, \ 5180x0010009C, \ 5190x00244F8B, \ 5200x00000800, \ 5210x00124818, \ 5220x0038047F, \ 5230x00000000, \ 5240x00140000, \ 5250x003805A3, \ 5260x00308000, \ 5270x00100610, \ 5280x00100561, \ 5290x000E0408, \ 5300x00134861, \ 5310x000C0002, \ 5320x00103093, \ 5330x00308000, \ 5340x00100624, \ 5350x00100561, \ 5360x000E0408, \ 5370x00100861, \ 5380x000C007E, \ 5390x00222FA1, \ 5400x000C0002, \ 5410x00103093, \ 5420x00380F90, \ 5430x00080000, \ 5440x00103090, \ 5450x00380F90, \ 5460x00000000, \ 5470x00000000, \ 5480x00000000, \ 5490x00000000, \ 5500x0010009C, \ 5510x00244FAD, \ 5520x00010004, \ 5530x00041000, \ 5540x003A047E, \ 5550x00044010, \ 5560x00380819, \ 5570x00000000, \ 5580x00100099, \ 5590x00206FFD, \ 5600x0010009A, \ 5610x0020AFFD, \ 5620x0010009C, \ 5630x00244FC8, \ 5640x00130824, \ 5650x000C0001, \ 5660x00101213, \ 5670x00260FF8, \ 5680x00041000, \ 5690x00010004, \ 5700x00130826, \ 5710x000C0006, \ 5720x00220700, \ 5730x0013C926, \ 5740x00101313, \ 5750x00380700, \ 5760x00000000, \ 5770x00000000, \ 5780x00000000, \ 5790x00000000, \ 5800x00000000, \ 5810x00000000, \ 5820x00080600, \ 5830x00101B10, \ 5840x00050004, \ 5850x00100826, \ 5860x00101210, \ 5870x00380FB6, \ 5880x00000000, \ 5890x00000000, \ 5900x002115A9, \ 5910x00100099, \ 5920x002065A7, \ 5930x0010009A, \ 5940x0020A5A7, \ 5950x0010009C, \ 5960x002445A7, \ 5970x00130836, \ 5980x000C0000, \ 5990x00220FE4, \ 6000x000C0001, \ 6010x00101B13, \ 6020x00229F8E, \ 6030x00210F8E, \ 6040x00226F8E, \ 6050x00216F8E, \ 6060x0022FF8E, \ 6070x00215F8E, \ 6080x00214F8E, \ 6090x003805A3, \ 6100x00010004, \ 6110x00041000, \ 6120x00278FE9, \ 6130x00040800, \ 6140x00018100, \ 6150x003A047E, \ 6160x00130826, \ 6170x000C0001, \ 6180x002205A7, \ 6190x00101313, \ 6200x003805A7, \ 6210x00000000, \ 6220x00000000, \ 6230x00000000, \ 6240x00000000, \ 6250x00000000, \ 6260x00000000, \ 6270x00000000, \ 6280x00000000, \ 6290x00000000, \ 6300x00130831, \ 6310x0010090B, \ 6320x00124813, \ 6330x000CFF80, \ 6340x00260703, \ 6350x00041000, \ 6360x00380700, \ 6370x00000000, \ 638} 639 640 641/********************************************************/ 642/* CPUSaver micro code for the D102 B-step */ 643/********************************************************/ 644 645/* Version 2.0 */ 646 647/* 648 This version of CPUSaver is different from all others in 649 a different way. It combines the CPUSaver algorithm with 650 fixes for bugs in the B-step hardware (specifically, bugs 651 with Inline Receive). 652 Thus, when CPUSaver is disabled, this micro code image will 653 still need to be loaded. Before this happens, the hit addresses 654 for the CPUSaver algorithm must be set to 0x1FFFF. The hit 655 addresses for CPUSaver are (starting with 0, and remember that 656 657*/ 658 659/* Parameter values for the D102 B-step */ 660#define D102_B_CPUSAVER_DWORD 91 661#define D102_B_CPUSAVER_BUNDLE_MAX_DWORD 115 662#define D102_B_CPUSAVER_MIN_SIZE_DWORD 70 663 664 665#define D102_B_RCVBUNDLE_UCODE \ 666{\ 6670x006F0276, \ 6680x02BF0E93, \ 6690x1FFF0ED9, \ 6700x0D2508FA, \ 6710x04D21FFF, \ 6720x0EA10892, \ 6730x00300001, \ 6740x0140D871, \ 6750x00300008, \ 6760x00E00277, \ 6770x01406C57, \ 6780x00816073, \ 6790x008700FA, \ 6800x00E00070, \ 6810x00E00E94, \ 6820x00200004, \ 6830x01410000, \ 6840x014B6F6F, \ 6850x0030FFFF, \ 6860x01486F72, \ 6870x00E81F9B, \ 6880x00E00EA3, \ 6890x003C0040, \ 6900x00380920, \ 6910x00C02000, \ 6920x0150ED38, \ 6930x0150EE39, \ 6940x0150EF3A, \ 6950x003C0040, \ 6960x01506F0D, \ 6970x01600E72, \ 6980x00380AE0, \ 6990x00E002C0, \ 7000x00300001, \ 7010x014C0000, \ 7020x008404DC, \ 7030x014C6F72, \ 7040x00E01F9D, \ 7050x01406C51, \ 7060x0080DFC2, \ 7070x01406C52, \ 7080x00815FC2, \ 7090x01406C57, \ 7100x00917FD5, \ 7110x00E01FE6, \ 7120x00000000, \ 7130x01406C57, \ 7140x00919FAD, \ 7150x00038800, \ 7160x00300000, \ 7170x00E81FF2, \ 7180x014D6FC4, \ 7190x00E008FB, \ 7200x00000000, \ 7210x00822D30, \ 7220x01406C51, \ 7230x0080CD26, \ 7240x01406C52, \ 7250x00814D26, \ 7260x01406C57, \ 7270x00916D26, \ 7280x014C6FD7, \ 7290x00300000, \ 7300x00841FDB, \ 7310x00300001, \ 7320x0140D772, \ 7330x00E012B3, \ 7340x014C6F91, \ 7350x0150710B, \ 7360x01496F72, \ 7370x0030FF80, \ 7380x00940EDD, \ 7390x00102000, \ 7400x00E00EDA, \ 7410x01406C57, \ 7420x00917FFD, \ 7430x00001000, \ 7440x00E01FFD, \ 7450x00138800, \ 7460x00300001, \ 7470x00E81FF2, \ 7480x00202500, \ 7490x00E81F9B, \ 7500x01600EC5, \ 7510x00E00893, \ 7520x00000000, \ 7530x01406CD5, \ 7540x0091EEA3, \ 7550x00904EA3, \ 7560x00901F89, \ 7570x00E00EA3, \ 7580x00200600, \ 7590x0140D76F, \ 7600x00138400, \ 7610x01406FD8, \ 7620x0140D96F, \ 7630x00E01FE6, \ 7640x00038400, \ 7650x00102000, \ 7660x00971FE0, \ 7670x00101000, \ 7680x00050200, \ 7690x00E804D2, \ 7700x014C6FD8, \ 7710x00300001, \ 7720x00840D26, \ 7730x0140D872, \ 7740x00E00D26, \ 7750x014C6FD9, \ 7760x00300001, \ 7770x0140D972, \ 7780x00941FBD, \ 7790x00102000, \ 7800x00038400, \ 7810x014C6FD8, \ 7820x00300006, \ 7830x00840EDA, \ 7840x014F71D8, \ 7850x0140D872, \ 7860x00E00EDA, \ 7870x00340020, \ 7880x014C6FED, \ 7890x01603472, \ 7900x016035EE, \ 7910x016036EF, \ 7920x00300004, \ 7930x01611C71, \ 7940x00300014, \ 7950x00200A00, \ 7960x00E810B9, \ 7970x00600000, \ 7980x01496F50, \ 7990x00E004D3, \ 8000x00000000, \ 801} 802 803 804 805 806/********************************************************/ 807/* TCO micro code for the D102 B-step */ 808/********************************************************/ 809 810/* Version 2.0 */ 811 812/* 813 This version is a fix to TCO bug. This version can be loaded instead 814 the CPUSaver version by modifing the registry key "LoadTcoUCodeInsteadOfCpuSaver" 815 816*/ 817 818 819#define D102_B_TCO_UCODE \ 820{\ 8210x1FFF0ED3, \ 8220x02BF0E93, \ 8230x1FFF1FFF, \ 8240x1FFF08FA, \ 8250x1FFF1FFF, \ 8260x0EA10892, \ 8270x00906ED8, \ 8280x01406C55, \ 8290x00E00ED4, \ 8300x00000000, \ 8310x00000000, \ 8320x00000000, \ 8330x00000000, \ 8340x00000000, \ 8350x00E00E94, \ 8360x00200004, \ 8370x01410000, \ 8380x014B6F6F, \ 8390x0030FFFF, \ 8400x01486F72, \ 8410x00E81F9B, \ 8420x00E00EA3, \ 8430x003C0040, \ 8440x00380920, \ 8450x00C02000, \ 8460x0150ED38, \ 8470x0150EE39, \ 8480x0150EF3A, \ 8490x003C0040, \ 8500x01506F0D, \ 8510x01600E72, \ 8520x00380AE0, \ 8530x00E002C0, \ 8540x00300001, \ 8550x014C0000, \ 8560x008404DC, \ 8570x014C6F72, \ 8580x00E01F9D, \ 8590x00000000, \ 8600x00000000, \ 8610x00000000, \ 8620x00000000, \ 8630x00000000, \ 8640x00000000, \ 8650x00000000, \ 8660x00000000, \ 8670x01406C57, \ 8680x00919FAD, \ 8690x00038800, \ 8700x00300000, \ 8710x00E81FD5, \ 8720x014D6FC4, \ 8730x00E008FB, \ 8740x00000000, \ 8750x00000000, \ 8760x00000000, \ 8770x00000000, \ 8780x00000000, \ 8790x00000000, \ 8800x00000000, \ 8810x00000000, \ 8820x00000000, \ 8830x00000000, \ 8840x00000000, \ 8850x00000000, \ 8860x00000000, \ 8870x00000000, \ 8880x00000000, \ 8890x00000000, \ 8900x00000000, \ 8910x00000000, \ 8920x00000000, \ 8930x00000000, \ 8940x00000000, \ 8950x00000000, \ 8960x00000000, \ 8970x00000000, \ 8980x00000000, \ 8990x00138800, \ 9000x00300001, \ 9010x00E81FD5, \ 9020x00202500, \ 9030x00E81F9B, \ 9040x01600EC5, \ 9050x00E00893, \ 9060x00000000, \ 9070x01406CD5, \ 9080x0091EEA3, \ 9090x00904EA3, \ 9100x00901F89, \ 9110x00E00EA3, \ 9120x00340020, \ 9130x014C6FED, \ 9140x01603472, \ 9150x016035EE, \ 9160x016036EF, \ 9170x00300004, \ 9180x01611C71, \ 9190x00300014, \ 9200x00200A00, \ 9210x00E810B9, \ 9220x00600000, \ 9230x00000000, \ 9240x00000000, \ 9250x00000000, \ 9260x00000000, \ 9270x00000000, \ 9280x00000000, \ 9290x00000000, \ 9300x00000000, \ 9310x00000000, \ 9320x00000000, \ 9330x00000000, \ 9340x00000000, \ 9350x00000000, \ 9360x00000000, \ 9370x00000000, \ 9380x00000000, \ 9390x00000000, \ 9400x00000000, \ 9410x00000000, \ 9420x00000000, \ 9430x00000000, \ 9440x00000000, \ 9450x00000000, \ 9460x00000000, \ 9470x00000000, \ 9480x00000000, \ 9490x00000000, \ 9500x00000000, \ 9510x00000000, \ 9520x00000000, \ 9530x00000000, \ 9540x00000000, \ 955} 956 957 958 959/********************************************************/ 960/* Micro code for the D102 C-step */ 961/********************************************************/ 962 963/* Parameter values for the D102 C-step */ 964#define D102_C_CPUSAVER_DWORD 46 965#define D102_C_CPUSAVER_BUNDLE_MAX_DWORD 54 966#define D102_C_CPUSAVER_MIN_SIZE_DWORD 133 /* not implemented */ 967 968 969 970 971 972#if 0 973// this uCode include the CPU Saver and the TCO work around 974//for IP fregments. 975#endif 976#define D102_C_RCVBUNDLE_UCODE \ 977{ \ 9780x00700279, \ 9790x0E6104E2, \ 9800x02BF0CAE, \ 9810x1519150C, \ 9820x1FFF0E5B, \ 9830x1FFF1FFF, \ 9840x00E014D8, \ 9850x00000000, \ 9860x00000000, \ 9870x00000000, \ 9880x00E014DC, \ 9890x00000000, \ 9900x00000000, \ 9910x00000000, \ 9920x00E014F4, \ 9930x00000000, \ 9940x00000000, \ 9950x00000000, \ 9960x00000000, \ 9970x00000000, \ 9980x00000000, \ 9990x00000000, \ 10000x00E014E0, \ 10010x00000000, \ 10020x00000000, \ 10030x00000000, \ 10040x00000000, \ 10050x00000000, \ 10060x00000000, \ 10070x00000000, \ 10080x00000000, \ 10090x00000000, \ 10100x00000000, \ 10110x00000000, \ 10120x00000000, \ 10130x00000000, \ 10140x00000000, \ 10150x00000000, \ 10160x00E014E7, \ 10170x00000000, \ 10180x00000000, \ 10190x00000000, \ 10200x00141000, \ 10210x015D6F0D, \ 10220x00E002C0, \ 10230x00000000, \ 10240x00200600, \ 10250x00E0150D, \ 10260x00000000, \ 10270x00000000, \ 10280x00000000, \ 10290x00000000, \ 10300x00000000, \ 10310x00000000, \ 10320x00300006, \ 10330x00E0151A, \ 10340x00000000, \ 10350x00000000, \ 10360x00000000, \ 10370x00000000, \ 10380x00000000, \ 10390x00000000, \ 10400x00000000, \ 10410x00000000, \ 10420x00000000, \ 10430x00000000, \ 10440x00000000, \ 10450x00000000, \ 10460x00000000, \ 10470x00000000, \ 10480x00906E65, \ 10490x00800E60, \ 10500x00E00E5D, \ 10510x00000000, \ 10520x00000000, \ 10530x00000000, \ 10540x00000000, \ 10550x00000000, \ 10560x00000000, \ 10570x00000000, \ 10580x00000000, \ 10590x00000000, \ 10600x00000000, \ 10610x00000000, \ 10620x00000000, \ 10630x00000000, \ 10640x00000000, \ 10650x00000000, \ 10660x00000000, \ 10670x00000000, \ 10680x00000000, \ 10690x00000000, \ 10700x00000000, \ 10710x00000000, \ 10720x00000000, \ 10730x00000000, \ 10740x00000000, \ 10750x00000000, \ 10760x00000000, \ 10770x00000000, \ 10780x00000000, \ 10790x00000000, \ 10800x00000000, \ 10810x00000000, \ 10820x00000000, \ 10830x00000000, \ 10840x00000000, \ 10850x00000000, \ 10860x00000000, \ 10870x00000000, \ 10880x00000000, \ 10890x00000000, \ 10900x00000000, \ 10910x00000000, \ 10920x00000000, \ 10930x00000000, \ 10940x00000000, \ 10950x00000000, \ 10960x00000000, \ 10970x00000000, \ 10980x00000000, \ 10990x00000000, \ 11000x00000000, \ 11010x00000000, \ 11020x00000000, \ 11030x00000000, \ 11040x00000000, \ 11050x00000000, \ 11060x00000000, \ 11070x00000000, \ 11080x00000000, \ 11090x00000000, \ 11100x00000000, \ 11110x00000000, \ 1112} 1113 1114/********************************************************/ 1115/* Micro code for the D102 E-step */ 1116/********************************************************/ 1117 1118/* Parameter values for the D102 E-step */ 1119#define D102_E_CPUSAVER_DWORD 42 1120#define D102_E_CPUSAVER_BUNDLE_MAX_DWORD 54 1121#define D102_E_CPUSAVER_MIN_SIZE_DWORD 46 1122 1123#define D102_E_RCVBUNDLE_UCODE \ 1124{\ 11250x007D028F, \ 11260x0E4204F9, \ 11270x14ED0C85, \ 11280x14FA14E9, \ 11290x0EF70E36, \ 11300x1FFF1FFF, \ 11310x00E014B9, \ 11320x00000000, \ 11330x00000000, \ 11340x00000000, \ 11350x00E014BD, \ 11360x00000000, \ 11370x00000000, \ 11380x00000000, \ 11390x00E014D5, \ 11400x00000000, \ 11410x00000000, \ 11420x00000000, \ 11430x00000000, \ 11440x00000000, \ 11450x00000000, \ 11460x00000000, \ 11470x00E014C1, \ 11480x00000000, \ 11490x00000000, \ 11500x00000000, \ 11510x00000000, \ 11520x00000000, \ 11530x00000000, \ 11540x00000000, \ 11550x00000000, \ 11560x00000000, \ 11570x00000000, \ 11580x00000000, \ 11590x00000000, \ 11600x00000000, \ 11610x00000000, \ 11620x00000000, \ 11630x00E014C8, \ 11640x00000000, \ 11650x00000000, \ 11660x00000000, \ 11670x00200600, \ 11680x00E014EE, \ 11690x00000000, \ 11700x00000000, \ 11710x0030FF80, \ 11720x00940E46, \ 11730x00038200, \ 11740x00102000, \ 11750x00E00E43, \ 11760x00000000, \ 11770x00000000, \ 11780x00000000, \ 11790x00300006, \ 11800x00E014FB, \ 11810x00000000, \ 11820x00000000, \ 11830x00000000, \ 11840x00000000, \ 11850x00000000, \ 11860x00000000, \ 11870x00000000, \ 11880x00000000, \ 11890x00000000, \ 11900x00000000, \ 11910x00000000, \ 11920x00000000, \ 11930x00000000, \ 11940x00000000, \ 11950x00906E41, \ 11960x00800E3C, \ 11970x00E00E39, \ 11980x00000000, \ 11990x00906EFD, \ 12000x00900EFD, \ 12010x00E00EF8, \ 12020x00000000, \ 12030x00000000, \ 12040x00000000, \ 12050x00000000, \ 12060x00000000, \ 12070x00000000, \ 12080x00000000, \ 12090x00000000, \ 12100x00000000, \ 12110x00000000, \ 12120x00000000, \ 12130x00000000, \ 12140x00000000, \ 12150x00000000, \ 12160x00000000, \ 12170x00000000, \ 12180x00000000, \ 12190x00000000, \ 12200x00000000, \ 12210x00000000, \ 12220x00000000, \ 12230x00000000, \ 12240x00000000, \ 12250x00000000, \ 12260x00000000, \ 12270x00000000, \ 12280x00000000, \ 12290x00000000, \ 12300x00000000, \ 12310x00000000, \ 12320x00000000, \ 12330x00000000, \ 12340x00000000, \ 12350x00000000, \ 12360x00000000, \ 12370x00000000, \ 12380x00000000, \ 12390x00000000, \ 12400x00000000, \ 12410x00000000, \ 12420x00000000, \ 12430x00000000, \ 12440x00000000, \ 12450x00000000, \ 12460x00000000, \ 12470x00000000, \ 12480x00000000, \ 12490x00000000, \ 12500x00000000, \ 12510x00000000, \ 12520x00000000, \ 12530x00000000, \ 12540x00000000, \ 12550x00000000, \ 12560x00000000, \ 12570x00000000, \ 12580x00000000, \ 1259} 1260