1/*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <sys/cdefs.h> 8__FBSDID("$FreeBSD$"); 9 10#include "igc_api.h" 11 12static void igc_config_collision_dist_generic(struct igc_hw *hw); 13 14/** 15 * igc_init_mac_ops_generic - Initialize MAC function pointers 16 * @hw: pointer to the HW structure 17 * 18 * Setups up the function pointers to no-op functions 19 **/ 20void igc_init_mac_ops_generic(struct igc_hw *hw) 21{ 22 struct igc_mac_info *mac = &hw->mac; 23 DEBUGFUNC("igc_init_mac_ops_generic"); 24 25 /* General Setup */ 26 mac->ops.init_params = igc_null_ops_generic; 27 mac->ops.config_collision_dist = igc_config_collision_dist_generic; 28 mac->ops.rar_set = igc_rar_set_generic; 29} 30 31/** 32 * igc_null_ops_generic - No-op function, returns 0 33 * @hw: pointer to the HW structure 34 **/ 35s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw) 36{ 37 DEBUGFUNC("igc_null_ops_generic"); 38 return IGC_SUCCESS; 39} 40 41/** 42 * igc_null_mac_generic - No-op function, return void 43 * @hw: pointer to the HW structure 44 **/ 45void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw) 46{ 47 DEBUGFUNC("igc_null_mac_generic"); 48 return; 49} 50 51/** 52 * igc_null_link_info - No-op function, return 0 53 * @hw: pointer to the HW structure 54 * @s: dummy variable 55 * @d: dummy variable 56 **/ 57s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw, 58 u16 IGC_UNUSEDARG *s, u16 IGC_UNUSEDARG *d) 59{ 60 DEBUGFUNC("igc_null_link_info"); 61 return IGC_SUCCESS; 62} 63 64/** 65 * igc_null_mng_mode - No-op function, return false 66 * @hw: pointer to the HW structure 67 **/ 68bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw) 69{ 70 DEBUGFUNC("igc_null_mng_mode"); 71 return false; 72} 73 74/** 75 * igc_null_update_mc - No-op function, return void 76 * @hw: pointer to the HW structure 77 * @h: dummy variable 78 * @a: dummy variable 79 **/ 80void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw, 81 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 82{ 83 DEBUGFUNC("igc_null_update_mc"); 84 return; 85} 86 87/** 88 * igc_null_write_vfta - No-op function, return void 89 * @hw: pointer to the HW structure 90 * @a: dummy variable 91 * @b: dummy variable 92 **/ 93void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw, 94 u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b) 95{ 96 DEBUGFUNC("igc_null_write_vfta"); 97 return; 98} 99 100/** 101 * igc_null_rar_set - No-op function, return 0 102 * @hw: pointer to the HW structure 103 * @h: dummy variable 104 * @a: dummy variable 105 **/ 106int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw, 107 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 108{ 109 DEBUGFUNC("igc_null_rar_set"); 110 return IGC_SUCCESS; 111} 112 113/** 114 * igc_set_lan_id_single_port - Set LAN id for a single port device 115 * @hw: pointer to the HW structure 116 * 117 * Sets the LAN function id to zero for a single port device. 118 **/ 119void igc_set_lan_id_single_port(struct igc_hw *hw) 120{ 121 struct igc_bus_info *bus = &hw->bus; 122 123 bus->func = 0; 124} 125 126/** 127 * igc_clear_vfta_generic - Clear VLAN filter table 128 * @hw: pointer to the HW structure 129 * 130 * Clears the register array which contains the VLAN filter table by 131 * setting all the values to 0. 132 **/ 133void igc_clear_vfta_generic(struct igc_hw *hw) 134{ 135 u32 offset; 136 137 DEBUGFUNC("igc_clear_vfta_generic"); 138 139 for (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) { 140 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0); 141 IGC_WRITE_FLUSH(hw); 142 } 143} 144 145/** 146 * igc_write_vfta_generic - Write value to VLAN filter table 147 * @hw: pointer to the HW structure 148 * @offset: register offset in VLAN filter table 149 * @value: register value written to VLAN filter table 150 * 151 * Writes value at the given offset in the register array which stores 152 * the VLAN filter table. 153 **/ 154void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value) 155{ 156 DEBUGFUNC("igc_write_vfta_generic"); 157 158 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value); 159 IGC_WRITE_FLUSH(hw); 160} 161 162/** 163 * igc_init_rx_addrs_generic - Initialize receive address's 164 * @hw: pointer to the HW structure 165 * @rar_count: receive address registers 166 * 167 * Setup the receive address registers by setting the base receive address 168 * register to the devices MAC address and clearing all the other receive 169 * address registers to 0. 170 **/ 171void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count) 172{ 173 u32 i; 174 u8 mac_addr[ETH_ADDR_LEN] = {0}; 175 176 DEBUGFUNC("igc_init_rx_addrs_generic"); 177 178 /* Setup the receive address */ 179 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 180 181 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 182 183 /* Zero out the other (rar_entry_count - 1) receive addresses */ 184 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 185 for (i = 1; i < rar_count; i++) 186 hw->mac.ops.rar_set(hw, mac_addr, i); 187} 188 189/** 190 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr 191 * @hw: pointer to the HW structure 192 * 193 * Checks the nvm for an alternate MAC address. An alternate MAC address 194 * can be setup by pre-boot software and must be treated like a permanent 195 * address and must override the actual permanent MAC address. If an 196 * alternate MAC address is found it is programmed into RAR0, replacing 197 * the permanent address that was installed into RAR0 by the Si on reset. 198 * This function will return SUCCESS unless it encounters an error while 199 * reading the EEPROM. 200 **/ 201s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw) 202{ 203 u32 i; 204 s32 ret_val; 205 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 206 u8 alt_mac_addr[ETH_ADDR_LEN]; 207 208 DEBUGFUNC("igc_check_alt_mac_addr_generic"); 209 210 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 211 if (ret_val) 212 return ret_val; 213 214 215 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 216 &nvm_alt_mac_addr_offset); 217 if (ret_val) { 218 DEBUGOUT("NVM Read Error\n"); 219 return ret_val; 220 } 221 222 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 223 (nvm_alt_mac_addr_offset == 0x0000)) 224 /* There is no Alternate MAC Address */ 225 return IGC_SUCCESS; 226 227 if (hw->bus.func == IGC_FUNC_1) 228 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1; 229 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 230 offset = nvm_alt_mac_addr_offset + (i >> 1); 231 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 232 if (ret_val) { 233 DEBUGOUT("NVM Read Error\n"); 234 return ret_val; 235 } 236 237 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 238 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 239 } 240 241 /* if multicast bit is set, the alternate address will not be used */ 242 if (alt_mac_addr[0] & 0x01) { 243 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 244 return IGC_SUCCESS; 245 } 246 247 /* We have a valid alternate MAC address, and we want to treat it the 248 * same as the normal permanent MAC address stored by the HW into the 249 * RAR. Do this by mapping this address into RAR0. 250 */ 251 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 252 253 return IGC_SUCCESS; 254} 255 256/** 257 * igc_rar_set_generic - Set receive address register 258 * @hw: pointer to the HW structure 259 * @addr: pointer to the receive address 260 * @index: receive address array register 261 * 262 * Sets the receive address array register at index to the address passed 263 * in by addr. 264 **/ 265int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index) 266{ 267 u32 rar_low, rar_high; 268 269 DEBUGFUNC("igc_rar_set_generic"); 270 271 /* HW expects these in little endian so we reverse the byte order 272 * from network order (big endian) to little endian 273 */ 274 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 275 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 276 277 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 278 279 /* If MAC address zero, no need to set the AV bit */ 280 if (rar_low || rar_high) 281 rar_high |= IGC_RAH_AV; 282 283 /* Some bridges will combine consecutive 32-bit writes into 284 * a single burst write, which will malfunction on some parts. 285 * The flushes avoid this. 286 */ 287 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low); 288 IGC_WRITE_FLUSH(hw); 289 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high); 290 IGC_WRITE_FLUSH(hw); 291 292 return IGC_SUCCESS; 293} 294 295/** 296 * igc_hash_mc_addr_generic - Generate a multicast hash value 297 * @hw: pointer to the HW structure 298 * @mc_addr: pointer to a multicast address 299 * 300 * Generates a multicast address hash value which is used to determine 301 * the multicast filter table array address and new table value. 302 **/ 303u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr) 304{ 305 u32 hash_value, hash_mask; 306 u8 bit_shift = 0; 307 308 DEBUGFUNC("igc_hash_mc_addr_generic"); 309 310 /* Register count multiplied by bits per register */ 311 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 312 313 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 314 * where 0xFF would still fall within the hash mask. 315 */ 316 while (hash_mask >> bit_shift != 0xFF) 317 bit_shift++; 318 319 /* The portion of the address that is used for the hash table 320 * is determined by the mc_filter_type setting. 321 * The algorithm is such that there is a total of 8 bits of shifting. 322 * The bit_shift for a mc_filter_type of 0 represents the number of 323 * left-shifts where the MSB of mc_addr[5] would still fall within 324 * the hash_mask. Case 0 does this exactly. Since there are a total 325 * of 8 bits of shifting, then mc_addr[4] will shift right the 326 * remaining number of bits. Thus 8 - bit_shift. The rest of the 327 * cases are a variation of this algorithm...essentially raising the 328 * number of bits to shift mc_addr[5] left, while still keeping the 329 * 8-bit shifting total. 330 * 331 * For example, given the following Destination MAC Address and an 332 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 333 * we can see that the bit_shift for case 0 is 4. These are the hash 334 * values resulting from each mc_filter_type... 335 * [0] [1] [2] [3] [4] [5] 336 * 01 AA 00 12 34 56 337 * LSB MSB 338 * 339 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 340 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 341 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 342 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 343 */ 344 switch (hw->mac.mc_filter_type) { 345 default: 346 case 0: 347 break; 348 case 1: 349 bit_shift += 1; 350 break; 351 case 2: 352 bit_shift += 2; 353 break; 354 case 3: 355 bit_shift += 4; 356 break; 357 } 358 359 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 360 (((u16) mc_addr[5]) << bit_shift))); 361 362 return hash_value; 363} 364 365/** 366 * igc_update_mc_addr_list_generic - Update Multicast addresses 367 * @hw: pointer to the HW structure 368 * @mc_addr_list: array of multicast addresses to program 369 * @mc_addr_count: number of multicast addresses to program 370 * 371 * Updates entire Multicast Table Array. 372 * The caller must have a packed mc_addr_list of multicast addresses. 373 **/ 374void igc_update_mc_addr_list_generic(struct igc_hw *hw, 375 u8 *mc_addr_list, u32 mc_addr_count) 376{ 377 u32 hash_value, hash_bit, hash_reg; 378 int i; 379 380 DEBUGFUNC("igc_update_mc_addr_list_generic"); 381 382 /* clear mta_shadow */ 383 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 384 385 /* update mta_shadow from mc_addr_list */ 386 for (i = 0; (u32) i < mc_addr_count; i++) { 387 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list); 388 389 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 390 hash_bit = hash_value & 0x1F; 391 392 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 393 mc_addr_list += (ETH_ADDR_LEN); 394 } 395 396 /* replace the entire MTA table */ 397 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 398 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]); 399 IGC_WRITE_FLUSH(hw); 400} 401 402/** 403 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters 404 * @hw: pointer to the HW structure 405 * 406 * Clears the base hardware counters by reading the counter registers. 407 **/ 408void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw) 409{ 410 DEBUGFUNC("igc_clear_hw_cntrs_base_generic"); 411 412 IGC_READ_REG(hw, IGC_CRCERRS); 413 IGC_READ_REG(hw, IGC_MPC); 414 IGC_READ_REG(hw, IGC_SCC); 415 IGC_READ_REG(hw, IGC_ECOL); 416 IGC_READ_REG(hw, IGC_MCC); 417 IGC_READ_REG(hw, IGC_LATECOL); 418 IGC_READ_REG(hw, IGC_COLC); 419 IGC_READ_REG(hw, IGC_RERC); 420 IGC_READ_REG(hw, IGC_DC); 421 IGC_READ_REG(hw, IGC_RLEC); 422 IGC_READ_REG(hw, IGC_XONRXC); 423 IGC_READ_REG(hw, IGC_XONTXC); 424 IGC_READ_REG(hw, IGC_XOFFRXC); 425 IGC_READ_REG(hw, IGC_XOFFTXC); 426 IGC_READ_REG(hw, IGC_FCRUC); 427 IGC_READ_REG(hw, IGC_GPRC); 428 IGC_READ_REG(hw, IGC_BPRC); 429 IGC_READ_REG(hw, IGC_MPRC); 430 IGC_READ_REG(hw, IGC_GPTC); 431 IGC_READ_REG(hw, IGC_GORCL); 432 IGC_READ_REG(hw, IGC_GORCH); 433 IGC_READ_REG(hw, IGC_GOTCL); 434 IGC_READ_REG(hw, IGC_GOTCH); 435 IGC_READ_REG(hw, IGC_RNBC); 436 IGC_READ_REG(hw, IGC_RUC); 437 IGC_READ_REG(hw, IGC_RFC); 438 IGC_READ_REG(hw, IGC_ROC); 439 IGC_READ_REG(hw, IGC_RJC); 440 IGC_READ_REG(hw, IGC_TORL); 441 IGC_READ_REG(hw, IGC_TORH); 442 IGC_READ_REG(hw, IGC_TOTL); 443 IGC_READ_REG(hw, IGC_TOTH); 444 IGC_READ_REG(hw, IGC_TPR); 445 IGC_READ_REG(hw, IGC_TPT); 446 IGC_READ_REG(hw, IGC_MPTC); 447 IGC_READ_REG(hw, IGC_BPTC); 448 IGC_READ_REG(hw, IGC_TLPIC); 449 IGC_READ_REG(hw, IGC_RLPIC); 450 IGC_READ_REG(hw, IGC_RXDMTC); 451} 452 453/** 454 * igc_check_for_copper_link_generic - Check for link (Copper) 455 * @hw: pointer to the HW structure 456 * 457 * Checks to see of the link status of the hardware has changed. If a 458 * change in link status has been detected, then we read the PHY registers 459 * to get the current speed/duplex if link exists. 460 **/ 461s32 igc_check_for_copper_link_generic(struct igc_hw *hw) 462{ 463 struct igc_mac_info *mac = &hw->mac; 464 s32 ret_val; 465 bool link = false; 466 467 DEBUGFUNC("igc_check_for_copper_link"); 468 469 /* We only want to go out to the PHY registers to see if Auto-Neg 470 * has completed and/or if our link status has changed. The 471 * get_link_status flag is set upon receiving a Link Status 472 * Change or Rx Sequence Error interrupt. 473 */ 474 if (!mac->get_link_status) 475 return IGC_SUCCESS; 476 477 /* First we want to see if the MII Status Register reports 478 * link. If so, then we want to get the current speed/duplex 479 * of the PHY. 480 */ 481 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 482 if (ret_val) 483 return ret_val; 484 485 if (!link) 486 return IGC_SUCCESS; /* No link detected */ 487 488 mac->get_link_status = false; 489 490 /* Check if there was DownShift, must be checked 491 * immediately after link-up 492 */ 493 igc_check_downshift_generic(hw); 494 495 /* If we are forcing speed/duplex, then we simply return since 496 * we have already determined whether we have link or not. 497 */ 498 if (!mac->autoneg) 499 return -IGC_ERR_CONFIG; 500 501 /* Auto-Neg is enabled. Auto Speed Detection takes care 502 * of MAC speed/duplex configuration. So we only need to 503 * configure Collision Distance in the MAC. 504 */ 505 mac->ops.config_collision_dist(hw); 506 507 /* Configure Flow Control now that Auto-Neg has completed. 508 * First, we need to restore the desired flow control 509 * settings because we may have had to re-autoneg with a 510 * different link partner. 511 */ 512 ret_val = igc_config_fc_after_link_up_generic(hw); 513 if (ret_val) 514 DEBUGOUT("Error configuring flow control\n"); 515 516 return ret_val; 517} 518 519/** 520 * igc_setup_link_generic - Setup flow control and link settings 521 * @hw: pointer to the HW structure 522 * 523 * Determines which flow control settings to use, then configures flow 524 * control. Calls the appropriate media-specific link configuration 525 * function. Assuming the adapter has a valid link partner, a valid link 526 * should be established. Assumes the hardware has previously been reset 527 * and the transmitter and receiver are not enabled. 528 **/ 529s32 igc_setup_link_generic(struct igc_hw *hw) 530{ 531 s32 ret_val; 532 533 DEBUGFUNC("igc_setup_link_generic"); 534 535 /* In the case of the phy reset being blocked, we already have a link. 536 * We do not need to set it up again. 537 */ 538 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 539 return IGC_SUCCESS; 540 541 /* If requested flow control is set to default, set flow control 542 * for both 'rx' and 'tx' pause frames. 543 */ 544 if (hw->fc.requested_mode == igc_fc_default) { 545 hw->fc.requested_mode = igc_fc_full; 546 } 547 548 /* Save off the requested flow control mode for use later. Depending 549 * on the link partner's capabilities, we may or may not use this mode. 550 */ 551 hw->fc.current_mode = hw->fc.requested_mode; 552 553 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 554 hw->fc.current_mode); 555 556 /* Call the necessary media_type subroutine to configure the link. */ 557 ret_val = hw->mac.ops.setup_physical_interface(hw); 558 if (ret_val) 559 return ret_val; 560 561 /* Initialize the flow control address, type, and PAUSE timer 562 * registers to their default values. This is done even if flow 563 * control is disabled, because it does not hurt anything to 564 * initialize these registers. 565 */ 566 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 567 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE); 568 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 569 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); 570 571 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time); 572 573 return igc_set_fc_watermarks_generic(hw); 574} 575 576/** 577 * igc_config_collision_dist_generic - Configure collision distance 578 * @hw: pointer to the HW structure 579 * 580 * Configures the collision distance to the default value and is used 581 * during link setup. 582 **/ 583static void igc_config_collision_dist_generic(struct igc_hw *hw) 584{ 585 u32 tctl; 586 587 DEBUGFUNC("igc_config_collision_dist_generic"); 588 589 tctl = IGC_READ_REG(hw, IGC_TCTL); 590 591 tctl &= ~IGC_TCTL_COLD; 592 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT; 593 594 IGC_WRITE_REG(hw, IGC_TCTL, tctl); 595 IGC_WRITE_FLUSH(hw); 596} 597 598/** 599 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks 600 * @hw: pointer to the HW structure 601 * 602 * Sets the flow control high/low threshold (watermark) registers. If 603 * flow control XON frame transmission is enabled, then set XON frame 604 * transmission as well. 605 **/ 606s32 igc_set_fc_watermarks_generic(struct igc_hw *hw) 607{ 608 u32 fcrtl = 0, fcrth = 0; 609 610 DEBUGFUNC("igc_set_fc_watermarks_generic"); 611 612 /* Set the flow control receive threshold registers. Normally, 613 * these registers will be set to a default threshold that may be 614 * adjusted later by the driver's runtime code. However, if the 615 * ability to transmit pause frames is not enabled, then these 616 * registers will be set to 0. 617 */ 618 if (hw->fc.current_mode & igc_fc_tx_pause) { 619 /* We need to set up the Receive Threshold high and low water 620 * marks as well as (optionally) enabling the transmission of 621 * XON frames. 622 */ 623 fcrtl = hw->fc.low_water; 624 if (hw->fc.send_xon) 625 fcrtl |= IGC_FCRTL_XONE; 626 627 fcrth = hw->fc.high_water; 628 } 629 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl); 630 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth); 631 632 return IGC_SUCCESS; 633} 634 635/** 636 * igc_force_mac_fc_generic - Force the MAC's flow control settings 637 * @hw: pointer to the HW structure 638 * 639 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 640 * device control register to reflect the adapter settings. TFCE and RFCE 641 * need to be explicitly set by software when a copper PHY is used because 642 * autonegotiation is managed by the PHY rather than the MAC. Software must 643 * also configure these bits when link is forced on a fiber connection. 644 **/ 645s32 igc_force_mac_fc_generic(struct igc_hw *hw) 646{ 647 u32 ctrl; 648 649 DEBUGFUNC("igc_force_mac_fc_generic"); 650 651 ctrl = IGC_READ_REG(hw, IGC_CTRL); 652 653 /* Because we didn't get link via the internal auto-negotiation 654 * mechanism (we either forced link or we got link via PHY 655 * auto-neg), we have to manually enable/disable transmit an 656 * receive flow control. 657 * 658 * The "Case" statement below enables/disable flow control 659 * according to the "hw->fc.current_mode" parameter. 660 * 661 * The possible values of the "fc" parameter are: 662 * 0: Flow control is completely disabled 663 * 1: Rx flow control is enabled (we can receive pause 664 * frames but not send pause frames). 665 * 2: Tx flow control is enabled (we can send pause frames 666 * frames but we do not receive pause frames). 667 * 3: Both Rx and Tx flow control (symmetric) is enabled. 668 * other: No other values should be possible at this point. 669 */ 670 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 671 672 switch (hw->fc.current_mode) { 673 case igc_fc_none: 674 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); 675 break; 676 case igc_fc_rx_pause: 677 ctrl &= (~IGC_CTRL_TFCE); 678 ctrl |= IGC_CTRL_RFCE; 679 break; 680 case igc_fc_tx_pause: 681 ctrl &= (~IGC_CTRL_RFCE); 682 ctrl |= IGC_CTRL_TFCE; 683 break; 684 case igc_fc_full: 685 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); 686 break; 687 default: 688 DEBUGOUT("Flow control param set incorrectly\n"); 689 return -IGC_ERR_CONFIG; 690 } 691 692 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 693 694 return IGC_SUCCESS; 695} 696 697/** 698 * igc_config_fc_after_link_up_generic - Configures flow control after link 699 * @hw: pointer to the HW structure 700 * 701 * Checks the status of auto-negotiation after link up to ensure that the 702 * speed and duplex were not forced. If the link needed to be forced, then 703 * flow control needs to be forced also. If auto-negotiation is enabled 704 * and did not fail, then we configure flow control based on our link 705 * partner. 706 **/ 707s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw) 708{ 709 struct igc_mac_info *mac = &hw->mac; 710 s32 ret_val = IGC_SUCCESS; 711 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 712 u16 speed, duplex; 713 714 DEBUGFUNC("igc_config_fc_after_link_up_generic"); 715 716 if (ret_val) { 717 DEBUGOUT("Error forcing flow control settings\n"); 718 return ret_val; 719 } 720 721 /* Check for the case where we have copper media and auto-neg is 722 * enabled. In this case, we need to check and see if Auto-Neg 723 * has completed, and if so, how the PHY and link partner has 724 * flow control configured. 725 */ 726 if (mac->autoneg) { 727 /* Read the MII Status Register and check to see if AutoNeg 728 * has completed. We read this twice because this reg has 729 * some "sticky" (latched) bits. 730 */ 731 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 732 if (ret_val) 733 return ret_val; 734 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 735 if (ret_val) 736 return ret_val; 737 738 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 739 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 740 return ret_val; 741 } 742 743 /* The AutoNeg process has completed, so we now need to 744 * read both the Auto Negotiation Advertisement 745 * Register (Address 4) and the Auto_Negotiation Base 746 * Page Ability Register (Address 5) to determine how 747 * flow control was negotiated. 748 */ 749 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 750 &mii_nway_adv_reg); 751 if (ret_val) 752 return ret_val; 753 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 754 &mii_nway_lp_ability_reg); 755 if (ret_val) 756 return ret_val; 757 758 /* Two bits in the Auto Negotiation Advertisement Register 759 * (Address 4) and two bits in the Auto Negotiation Base 760 * Page Ability Register (Address 5) determine flow control 761 * for both the PHY and the link partner. The following 762 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 763 * 1999, describes these PAUSE resolution bits and how flow 764 * control is determined based upon these settings. 765 * NOTE: DC = Don't Care 766 * 767 * LOCAL DEVICE | LINK PARTNER 768 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 769 *-------|---------|-------|---------|-------------------- 770 * 0 | 0 | DC | DC | igc_fc_none 771 * 0 | 1 | 0 | DC | igc_fc_none 772 * 0 | 1 | 1 | 0 | igc_fc_none 773 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 774 * 1 | 0 | 0 | DC | igc_fc_none 775 * 1 | DC | 1 | DC | igc_fc_full 776 * 1 | 1 | 0 | 0 | igc_fc_none 777 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 778 * 779 * Are both PAUSE bits set to 1? If so, this implies 780 * Symmetric Flow Control is enabled at both ends. The 781 * ASM_DIR bits are irrelevant per the spec. 782 * 783 * For Symmetric Flow Control: 784 * 785 * LOCAL DEVICE | LINK PARTNER 786 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 787 *-------|---------|-------|---------|-------------------- 788 * 1 | DC | 1 | DC | IGC_fc_full 789 * 790 */ 791 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 792 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 793 /* Now we need to check if the user selected Rx ONLY 794 * of pause frames. In this case, we had to advertise 795 * FULL flow control because we could not advertise Rx 796 * ONLY. Hence, we must now check to see if we need to 797 * turn OFF the TRANSMISSION of PAUSE frames. 798 */ 799 if (hw->fc.requested_mode == igc_fc_full) { 800 hw->fc.current_mode = igc_fc_full; 801 DEBUGOUT("Flow Control = FULL.\n"); 802 } else { 803 hw->fc.current_mode = igc_fc_rx_pause; 804 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 805 } 806 } 807 /* For receiving PAUSE frames ONLY. 808 * 809 * LOCAL DEVICE | LINK PARTNER 810 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 811 *-------|---------|-------|---------|-------------------- 812 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 813 */ 814 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 815 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 816 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 817 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 818 hw->fc.current_mode = igc_fc_tx_pause; 819 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 820 } 821 /* For transmitting PAUSE frames ONLY. 822 * 823 * LOCAL DEVICE | LINK PARTNER 824 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 825 *-------|---------|-------|---------|-------------------- 826 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 827 */ 828 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 829 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 830 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 831 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 832 hw->fc.current_mode = igc_fc_rx_pause; 833 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 834 } else { 835 /* Per the IEEE spec, at this point flow control 836 * should be disabled. 837 */ 838 hw->fc.current_mode = igc_fc_none; 839 DEBUGOUT("Flow Control = NONE.\n"); 840 } 841 842 /* Now we need to do one last check... If we auto- 843 * negotiated to HALF DUPLEX, flow control should not be 844 * enabled per IEEE 802.3 spec. 845 */ 846 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 847 if (ret_val) { 848 DEBUGOUT("Error getting link speed and duplex\n"); 849 return ret_val; 850 } 851 852 if (duplex == HALF_DUPLEX) 853 hw->fc.current_mode = igc_fc_none; 854 855 /* Now we call a subroutine to actually force the MAC 856 * controller to use the correct flow control settings. 857 */ 858 ret_val = igc_force_mac_fc_generic(hw); 859 if (ret_val) { 860 DEBUGOUT("Error forcing flow control settings\n"); 861 return ret_val; 862 } 863 } 864 865 return IGC_SUCCESS; 866} 867 868/** 869 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 870 * @hw: pointer to the HW structure 871 * @speed: stores the current speed 872 * @duplex: stores the current duplex 873 * 874 * Read the status register for the current speed/duplex and store the current 875 * speed and duplex for copper connections. 876 **/ 877s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed, 878 u16 *duplex) 879{ 880 u32 status; 881 882 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic"); 883 884 status = IGC_READ_REG(hw, IGC_STATUS); 885 if (status & IGC_STATUS_SPEED_1000) { 886 /* For I225, STATUS will indicate 1G speed in both 1 Gbps 887 * and 2.5 Gbps link modes. An additional bit is used 888 * to differentiate between 1 Gbps and 2.5 Gbps. 889 */ 890 if ((hw->mac.type == igc_i225) && 891 (status & IGC_STATUS_SPEED_2500)) { 892 *speed = SPEED_2500; 893 DEBUGOUT("2500 Mbs, "); 894 } else { 895 *speed = SPEED_1000; 896 DEBUGOUT("1000 Mbs, "); 897 } 898 } else if (status & IGC_STATUS_SPEED_100) { 899 *speed = SPEED_100; 900 DEBUGOUT("100 Mbs, "); 901 } else { 902 *speed = SPEED_10; 903 DEBUGOUT("10 Mbs, "); 904 } 905 906 if (status & IGC_STATUS_FD) { 907 *duplex = FULL_DUPLEX; 908 DEBUGOUT("Full Duplex\n"); 909 } else { 910 *duplex = HALF_DUPLEX; 911 DEBUGOUT("Half Duplex\n"); 912 } 913 914 return IGC_SUCCESS; 915} 916 917/** 918 * igc_get_hw_semaphore_generic - Acquire hardware semaphore 919 * @hw: pointer to the HW structure 920 * 921 * Acquire the HW semaphore to access the PHY or NVM 922 **/ 923s32 igc_get_hw_semaphore_generic(struct igc_hw *hw) 924{ 925 u32 swsm; 926 s32 timeout = hw->nvm.word_size + 1; 927 s32 i = 0; 928 929 DEBUGFUNC("igc_get_hw_semaphore_generic"); 930 931 /* Get the SW semaphore */ 932 while (i < timeout) { 933 swsm = IGC_READ_REG(hw, IGC_SWSM); 934 if (!(swsm & IGC_SWSM_SMBI)) 935 break; 936 937 usec_delay(50); 938 i++; 939 } 940 941 if (i == timeout) { 942 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 943 return -IGC_ERR_NVM; 944 } 945 946 /* Get the FW semaphore. */ 947 for (i = 0; i < timeout; i++) { 948 swsm = IGC_READ_REG(hw, IGC_SWSM); 949 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); 950 951 /* Semaphore acquired if bit latched */ 952 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) 953 break; 954 955 usec_delay(50); 956 } 957 958 if (i == timeout) { 959 /* Release semaphores */ 960 igc_put_hw_semaphore_generic(hw); 961 DEBUGOUT("Driver can't access the NVM\n"); 962 return -IGC_ERR_NVM; 963 } 964 965 return IGC_SUCCESS; 966} 967 968/** 969 * igc_put_hw_semaphore_generic - Release hardware semaphore 970 * @hw: pointer to the HW structure 971 * 972 * Release hardware semaphore used to access the PHY or NVM 973 **/ 974void igc_put_hw_semaphore_generic(struct igc_hw *hw) 975{ 976 u32 swsm; 977 978 DEBUGFUNC("igc_put_hw_semaphore_generic"); 979 980 swsm = IGC_READ_REG(hw, IGC_SWSM); 981 982 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI); 983 984 IGC_WRITE_REG(hw, IGC_SWSM, swsm); 985} 986 987/** 988 * igc_get_auto_rd_done_generic - Check for auto read completion 989 * @hw: pointer to the HW structure 990 * 991 * Check EEPROM for Auto Read done bit. 992 **/ 993s32 igc_get_auto_rd_done_generic(struct igc_hw *hw) 994{ 995 s32 i = 0; 996 997 DEBUGFUNC("igc_get_auto_rd_done_generic"); 998 999 while (i < AUTO_READ_DONE_TIMEOUT) { 1000 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD) 1001 break; 1002 msec_delay(1); 1003 i++; 1004 } 1005 1006 if (i == AUTO_READ_DONE_TIMEOUT) { 1007 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1008 return -IGC_ERR_RESET; 1009 } 1010 1011 return IGC_SUCCESS; 1012} 1013 1014/** 1015 * igc_disable_pcie_master_generic - Disables PCI-express master access 1016 * @hw: pointer to the HW structure 1017 * 1018 * Returns IGC_SUCCESS if successful, else returns -10 1019 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1020 * the master requests to be disabled. 1021 * 1022 * Disables PCI-Express master access and verifies there are no pending 1023 * requests. 1024 **/ 1025s32 igc_disable_pcie_master_generic(struct igc_hw *hw) 1026{ 1027 u32 ctrl; 1028 s32 timeout = MASTER_DISABLE_TIMEOUT; 1029 1030 DEBUGFUNC("igc_disable_pcie_master_generic"); 1031 1032 ctrl = IGC_READ_REG(hw, IGC_CTRL); 1033 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; 1034 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 1035 1036 while (timeout) { 1037 if (!(IGC_READ_REG(hw, IGC_STATUS) & 1038 IGC_STATUS_GIO_MASTER_ENABLE)) 1039 break; 1040 usec_delay(100); 1041 timeout--; 1042 } 1043 1044 if (!timeout) { 1045 DEBUGOUT("Master requests are pending.\n"); 1046 return -IGC_ERR_MASTER_REQUESTS_PENDING; 1047 } 1048 1049 return IGC_SUCCESS; 1050} 1051