1/*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 *     Dave Airlie <airlied@redhat.com>
8 *     Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This header is BSD licensed so anyone can use the definitions
11 * to implement compatible drivers/servers:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of IBM nor the names of its contributors
22 *    may be used to endorse or promote products derived from this software
23 *    without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 */
37
38#ifndef VIRTIO_GPU_HW_H
39#define VIRTIO_GPU_HW_H
40
41#include <sys/types.h>
42
43#define __u8 uint8_t
44#define __u32 uint32_t
45#define __le16 uint16_t
46#define __le32 uint32_t
47#define __le64 uint64_t
48
49/*
50 * VIRTIO_GPU_CMD_CTX_*
51 * VIRTIO_GPU_CMD_*_3D
52 */
53#define VIRTIO_GPU_F_VIRGL               (1ULL << 0)
54
55/*
56 * VIRTIO_GPU_CMD_GET_EDID
57 */
58#define VIRTIO_GPU_F_EDID                (1ULL << 1)
59/*
60 * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID
61 */
62#define VIRTIO_GPU_F_RESOURCE_UUID       (1ULL << 2)
63
64/*
65 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
66 */
67#define VIRTIO_GPU_F_RESOURCE_BLOB       (1ULL << 3)
68
69enum virtio_gpu_ctrl_type {
70	VIRTIO_GPU_UNDEFINED = 0,
71
72	/* 2d commands */
73	VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
74	VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
75	VIRTIO_GPU_CMD_RESOURCE_UNREF,
76	VIRTIO_GPU_CMD_SET_SCANOUT,
77	VIRTIO_GPU_CMD_RESOURCE_FLUSH,
78	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
79	VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
80	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
81	VIRTIO_GPU_CMD_GET_CAPSET_INFO,
82	VIRTIO_GPU_CMD_GET_CAPSET,
83	VIRTIO_GPU_CMD_GET_EDID,
84	VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
85	VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
86	VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
87
88	/* 3d commands */
89	VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
90	VIRTIO_GPU_CMD_CTX_DESTROY,
91	VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
92	VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
93	VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
94	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
95	VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
96	VIRTIO_GPU_CMD_SUBMIT_3D,
97	VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
98	VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
99
100	/* cursor commands */
101	VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
102	VIRTIO_GPU_CMD_MOVE_CURSOR,
103
104	/* success responses */
105	VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
106	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
107	VIRTIO_GPU_RESP_OK_CAPSET_INFO,
108	VIRTIO_GPU_RESP_OK_CAPSET,
109	VIRTIO_GPU_RESP_OK_EDID,
110	VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
111	VIRTIO_GPU_RESP_OK_MAP_INFO,
112
113	/* error responses */
114	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
115	VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
116	VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
117	VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
118	VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
119	VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
120};
121
122enum virtio_gpu_shm_id {
123	VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
124	/*
125	 * VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB
126	 * VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB
127	 */
128	VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
129};
130
131#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
132
133struct virtio_gpu_ctrl_hdr {
134	__le32 type;
135	__le32 flags;
136	__le64 fence_id;
137	__le32 ctx_id;
138	__le32 padding;
139} _PACKED;
140
141/* data passed in the cursor vq */
142
143struct virtio_gpu_cursor_pos {
144	__le32 scanout_id;
145	__le32 x;
146	__le32 y;
147	__le32 padding;
148} _PACKED;
149
150/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
151struct virtio_gpu_update_cursor {
152	struct virtio_gpu_ctrl_hdr hdr;
153	struct virtio_gpu_cursor_pos pos;  /* update & move */
154	__le32 resource_id;           /* update only */
155	__le32 hot_x;                 /* update only */
156	__le32 hot_y;                 /* update only */
157	__le32 padding;
158} _PACKED;
159
160/* data passed in the control vq, 2d related */
161
162struct virtio_gpu_rect {
163	__le32 x;
164	__le32 y;
165	__le32 width;
166	__le32 height;
167} _PACKED;
168
169/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
170struct virtio_gpu_resource_unref {
171	struct virtio_gpu_ctrl_hdr hdr;
172	__le32 resource_id;
173	__le32 padding;
174} _PACKED;
175
176/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
177struct virtio_gpu_resource_create_2d {
178	struct virtio_gpu_ctrl_hdr hdr;
179	__le32 resource_id;
180	__le32 format;
181	__le32 width;
182	__le32 height;
183} _PACKED;
184
185/* VIRTIO_GPU_CMD_SET_SCANOUT */
186struct virtio_gpu_set_scanout {
187	struct virtio_gpu_ctrl_hdr hdr;
188	struct virtio_gpu_rect r;
189	__le32 scanout_id;
190	__le32 resource_id;
191} _PACKED;
192
193/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
194struct virtio_gpu_resource_flush {
195	struct virtio_gpu_ctrl_hdr hdr;
196	struct virtio_gpu_rect r;
197	__le32 resource_id;
198	__le32 padding;
199} _PACKED;
200
201/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
202struct virtio_gpu_transfer_to_host_2d {
203	struct virtio_gpu_ctrl_hdr hdr;
204	struct virtio_gpu_rect r;
205	__le64 offset;
206	__le32 resource_id;
207	__le32 padding;
208} _PACKED;
209
210struct virtio_gpu_mem_entry {
211	__le64 addr;
212	__le32 length;
213	__le32 padding;
214} _PACKED;
215
216/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
217struct virtio_gpu_resource_attach_backing {
218	struct virtio_gpu_ctrl_hdr hdr;
219	__le32 resource_id;
220	__le32 nr_entries;
221} _PACKED;
222
223/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
224struct virtio_gpu_resource_detach_backing {
225	struct virtio_gpu_ctrl_hdr hdr;
226	__le32 resource_id;
227	__le32 padding;
228} _PACKED;
229
230/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
231#define VIRTIO_GPU_MAX_SCANOUTS 16
232struct virtio_gpu_resp_display_info {
233	struct virtio_gpu_ctrl_hdr hdr;
234	struct virtio_gpu_display_one {
235		struct virtio_gpu_rect r;
236		__le32 enabled;
237		__le32 flags;
238	} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
239} _PACKED;
240
241/* data passed in the control vq, 3d related */
242
243struct virtio_gpu_box {
244	__le32 x, y, z;
245	__le32 w, h, d;
246} _PACKED;
247
248/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
249struct virtio_gpu_transfer_host_3d {
250	struct virtio_gpu_ctrl_hdr hdr;
251	struct virtio_gpu_box box;
252	__le64 offset;
253	__le32 resource_id;
254	__le32 level;
255	__le32 stride;
256	__le32 layer_stride;
257} _PACKED;
258
259/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
260#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
261struct virtio_gpu_resource_create_3d {
262	struct virtio_gpu_ctrl_hdr hdr;
263	__le32 resource_id;
264	__le32 target;
265	__le32 format;
266	__le32 bind;
267	__le32 width;
268	__le32 height;
269	__le32 depth;
270	__le32 array_size;
271	__le32 last_level;
272	__le32 nr_samples;
273	__le32 flags;
274	__le32 padding;
275} _PACKED;
276
277/* VIRTIO_GPU_CMD_CTX_CREATE */
278struct virtio_gpu_ctx_create {
279	struct virtio_gpu_ctrl_hdr hdr;
280	__le32 nlen;
281	__le32 padding;
282	char debug_name[64];
283} _PACKED;
284
285/* VIRTIO_GPU_CMD_CTX_DESTROY */
286struct virtio_gpu_ctx_destroy {
287	struct virtio_gpu_ctrl_hdr hdr;
288} _PACKED;
289
290/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
291struct virtio_gpu_ctx_resource {
292	struct virtio_gpu_ctrl_hdr hdr;
293	__le32 resource_id;
294	__le32 padding;
295} _PACKED;
296
297/* VIRTIO_GPU_CMD_SUBMIT_3D */
298struct virtio_gpu_cmd_submit {
299	struct virtio_gpu_ctrl_hdr hdr;
300	__le32 size;
301	__le32 padding;
302} _PACKED;
303
304#define VIRTIO_GPU_CAPSET_VIRGL 1
305#define VIRTIO_GPU_CAPSET_VIRGL2 2
306
307/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
308struct virtio_gpu_get_capset_info {
309	struct virtio_gpu_ctrl_hdr hdr;
310	__le32 capset_index;
311	__le32 padding;
312} _PACKED;
313
314/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
315struct virtio_gpu_resp_capset_info {
316	struct virtio_gpu_ctrl_hdr hdr;
317	__le32 capset_id;
318	__le32 capset_max_version;
319	__le32 capset_max_size;
320	__le32 padding;
321} _PACKED;
322
323/* VIRTIO_GPU_CMD_GET_CAPSET */
324struct virtio_gpu_get_capset {
325	struct virtio_gpu_ctrl_hdr hdr;
326	__le32 capset_id;
327	__le32 capset_version;
328} _PACKED;
329
330/* VIRTIO_GPU_RESP_OK_CAPSET */
331struct virtio_gpu_resp_capset {
332	struct virtio_gpu_ctrl_hdr hdr;
333	__u8 capset_data[];
334} _PACKED;
335
336/* VIRTIO_GPU_CMD_GET_EDID */
337struct virtio_gpu_cmd_get_edid {
338	struct virtio_gpu_ctrl_hdr hdr;
339	__le32 scanout;
340	__le32 padding;
341} _PACKED;
342
343/* VIRTIO_GPU_RESP_OK_EDID */
344struct virtio_gpu_resp_edid {
345	struct virtio_gpu_ctrl_hdr hdr;
346	__le32 size;
347	__le32 padding;
348	__u8 edid[1024];
349} _PACKED;
350
351#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
352
353struct virtio_gpu_config {
354	__le32 events_read;
355	__le32 events_clear;
356	__le32 num_scanouts;
357	__le32 num_capsets;
358} _PACKED;
359
360/* simple formats for fbcon/X use */
361enum virtio_gpu_formats {
362	VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM  = 1,
363	VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM  = 2,
364	VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM  = 3,
365	VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM  = 4,
366
367	VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM  = 67,
368	VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM  = 68,
369
370	VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM  = 121,
371	VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM  = 134,
372};
373
374/* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
375struct virtio_gpu_resource_assign_uuid {
376	struct virtio_gpu_ctrl_hdr hdr;
377	__le32 resource_id;
378	__le32 padding;
379} _PACKED;
380
381/* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
382struct virtio_gpu_resp_resource_uuid {
383	struct virtio_gpu_ctrl_hdr hdr;
384	__u8 uuid[16];
385} _PACKED;
386
387/* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
388struct virtio_gpu_resource_create_blob {
389	struct virtio_gpu_ctrl_hdr hdr;
390	__le32 resource_id;
391#define VIRTIO_GPU_BLOB_MEM_GUEST             0x0001
392#define VIRTIO_GPU_BLOB_MEM_HOST3D            0x0002
393#define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST      0x0003
394
395#define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE     0x0001
396#define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE    0x0002
397#define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
398	/* zero is invalid blob mem */
399	__le32 blob_mem;
400	__le32 blob_flags;
401	__le32 nr_entries;
402	__le64 blob_id;
403	__le64 size;
404	/*
405	 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow
406	 */
407} _PACKED;
408
409/* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
410struct virtio_gpu_set_scanout_blob {
411	struct virtio_gpu_ctrl_hdr hdr;
412	struct virtio_gpu_rect r;
413	__le32 scanout_id;
414	__le32 resource_id;
415	__le32 width;
416	__le32 height;
417	__le32 format;
418	__le32 padding;
419	__le32 strides[4];
420	__le32 offsets[4];
421} _PACKED;
422
423/* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
424struct virtio_gpu_resource_map_blob {
425	struct virtio_gpu_ctrl_hdr hdr;
426	__le32 resource_id;
427	__le32 padding;
428	__le64 offset;
429} _PACKED;
430
431/* VIRTIO_GPU_RESP_OK_MAP_INFO */
432#define VIRTIO_GPU_MAP_CACHE_MASK     0x0f
433#define VIRTIO_GPU_MAP_CACHE_NONE     0x00
434#define VIRTIO_GPU_MAP_CACHE_CACHED   0x01
435#define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
436#define VIRTIO_GPU_MAP_CACHE_WC       0x03
437struct virtio_gpu_resp_map_info {
438	struct virtio_gpu_ctrl_hdr hdr;
439	__u32 map_info;
440	__u32 padding;
441} _PACKED;
442
443/* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
444struct virtio_gpu_resource_unmap_blob {
445	struct virtio_gpu_ctrl_hdr hdr;
446	__le32 resource_id;
447	__le32 padding;
448} _PACKED;
449
450#endif
451