1/* 2 * Copyright 2013-2022 Haiku, Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5#ifndef BOOT_ARCH_CPU_H 6#define BOOT_ARCH_CPU_H 7 8 9#include <SupportDefs.h> 10#include <boot/vfs.h> 11 12 13#ifdef __cplusplus 14extern "C" { 15#endif 16 17status_t boot_arch_cpu_init(void); 18void arch_ucode_load(BootVolume& volume); 19 20bigtime_t system_time(); 21void spin(bigtime_t microseconds); 22 23 24static inline uint32 25cpu_read_CPSR(void) 26{ 27 uint32 res; 28 asm volatile("MRS %0, CPSR": "=r" (res)); 29 return res; 30} 31 32 33static inline uint32 34mmu_read_SCTLR(void) 35{ 36 uint32 res; 37 asm volatile("MRC p15, 0, %0, c1, c0, 0": "=r" (res)); 38 return res; 39} 40 41 42static inline uint32 43mmu_read_TTBR0(void) 44{ 45 uint32 res; 46 asm volatile("MRC p15, 0, %0, c2, c0, 0": "=r" (res)); 47 return res; 48} 49 50 51static inline uint32 52mmu_read_TTBR1(void) 53{ 54 uint32 res; 55 asm volatile("MRC p15, 0, %0, c2, c0, 1": "=r" (res)); 56 return res; 57} 58 59 60static inline uint32 61mmu_read_TTBCR(void) 62{ 63 uint32 res; 64 asm volatile("MRC p15, 0, %0, c2, c0, 2": "=r" (res)); 65 return res; 66} 67 68 69static inline uint32 70mmu_read_DACR(void) 71{ 72 uint32 res; 73 asm volatile("MRC p15, 0, %0, c3, c0, 0": "=r" (res)); 74 return res; 75} 76 77 78#ifdef __cplusplus 79} 80#endif 81 82 83#endif /* BOOT_ARCH_CPU_H */ 84