1/* 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 24/****************************************************************************/ 25/*Portion I: Definitions shared between VBIOS and Driver */ 26/****************************************************************************/ 27 28#ifndef _ATOMBIOS_H 29#define _ATOMBIOS_H 30 31// Types for Haiku 32#include "atombios-types.h" 33 34#define ATOM_VERSION_MAJOR 0x00020000 35#define ATOM_VERSION_MINOR 0x00000002 36 37#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 38 39/* Endianness should be specified before inclusion, 40 * default to little endian 41 */ 42#ifndef ATOM_BIG_ENDIAN 43#error Endian not specified 44#endif 45 46#ifdef _H2INC 47 #ifndef ULONG 48 typedef unsigned long ULONG; 49 #endif 50 51 #ifndef UCHAR 52 typedef unsigned char UCHAR; 53 #endif 54 55 #ifndef USHORT 56 typedef unsigned short USHORT; 57 #endif 58#endif 59 60#define ATOM_DAC_A 0 61#define ATOM_DAC_B 1 62#define ATOM_EXT_DAC 2 63 64#define ATOM_CRTC1 0 65#define ATOM_CRTC2 1 66#define ATOM_CRTC3 2 67#define ATOM_CRTC4 3 68#define ATOM_CRTC5 4 69#define ATOM_CRTC6 5 70 71#define ATOM_UNDERLAY_PIPE0 16 72#define ATOM_UNDERLAY_PIPE1 17 73 74#define ATOM_CRTC_INVALID 0xFF 75 76#define ATOM_DIGA 0 77#define ATOM_DIGB 1 78 79#define ATOM_PPLL1 0 80#define ATOM_PPLL2 1 81#define ATOM_DCPLL 2 82#define ATOM_PPLL0 2 83#define ATOM_PPLL3 3 84 85#define ATOM_PHY_PLL0 4 86#define ATOM_PHY_PLL1 5 87 88#define ATOM_EXT_PLL1 8 89#define ATOM_GCK_DFS 8 90#define ATOM_EXT_PLL2 9 91#define ATOM_FCH_CLK 9 92#define ATOM_EXT_CLOCK 10 93#define ATOM_DP_DTO 11 94 95#define ATOM_COMBOPHY_PLL0 20 96#define ATOM_COMBOPHY_PLL1 21 97#define ATOM_COMBOPHY_PLL2 22 98#define ATOM_COMBOPHY_PLL3 23 99#define ATOM_COMBOPHY_PLL4 24 100#define ATOM_COMBOPHY_PLL5 25 101 102#define ATOM_PPLL_INVALID 0xFF 103 104#define ENCODER_REFCLK_SRC_P1PLL 0 105#define ENCODER_REFCLK_SRC_P2PLL 1 106#define ENCODER_REFCLK_SRC_DCPLL 2 107#define ENCODER_REFCLK_SRC_EXTCLK 3 108#define ENCODER_REFCLK_SRC_INVALID 0xFF 109 110#define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication 111#define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication 112#define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode 113#define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios 114 115#define ATOM_DISABLE 0 116#define ATOM_ENABLE 1 117#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 118#define ATOM_LCD_BLON (ATOM_ENABLE+2) 119#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 120#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 121#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 122#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 123#define ATOM_INIT (ATOM_DISABLE+7) 124#define ATOM_GET_STATUS (ATOM_DISABLE+8) 125 126#define ATOM_BLANKING 1 127#define ATOM_BLANKING_OFF 0 128 129 130#define ATOM_CRT1 0 131#define ATOM_CRT2 1 132 133#define ATOM_TV_NTSC 1 134#define ATOM_TV_NTSCJ 2 135#define ATOM_TV_PAL 3 136#define ATOM_TV_PALM 4 137#define ATOM_TV_PALCN 5 138#define ATOM_TV_PALN 6 139#define ATOM_TV_PAL60 7 140#define ATOM_TV_SECAM 8 141#define ATOM_TV_CV 16 142 143#define ATOM_DAC1_PS2 1 144#define ATOM_DAC1_CV 2 145#define ATOM_DAC1_NTSC 3 146#define ATOM_DAC1_PAL 4 147 148#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 149#define ATOM_DAC2_CV ATOM_DAC1_CV 150#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 151#define ATOM_DAC2_PAL ATOM_DAC1_PAL 152 153#define ATOM_PM_ON 0 154#define ATOM_PM_STANDBY 1 155#define ATOM_PM_SUSPEND 2 156#define ATOM_PM_OFF 3 157 158// For ATOM_LVDS_INFO_V12 159// Bit0:{=0:single, =1:dual}, 160// Bit1 {=0:666RGB, =1:888RGB}, 161// Bit2:3:{Grey level} 162// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 163#define ATOM_PANEL_MISC_DUAL 0x00000001 164#define ATOM_PANEL_MISC_888RGB 0x00000002 165#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 166#define ATOM_PANEL_MISC_FPDI 0x00000010 167#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 168#define ATOM_PANEL_MISC_SPATIAL 0x00000020 169#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 170#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 171 172#define MEMTYPE_DDR1 "DDR1" 173#define MEMTYPE_DDR2 "DDR2" 174#define MEMTYPE_DDR3 "DDR3" 175#define MEMTYPE_DDR4 "DDR4" 176 177#define ASIC_BUS_TYPE_PCI "PCI" 178#define ASIC_BUS_TYPE_AGP "AGP" 179#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 180 181//Maximum size of that FireGL flag string 182#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 183#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 184 185#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 186#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 187 188#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 189#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 190 191#define HW_ASSISTED_I2C_STATUS_FAILURE 2 192#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 193 194#pragma pack(1) // BIOS data must use byte alignment 195 196// Define offset to location of ROM header. 197#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 198#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 199 200#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 201#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0! 202#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 203#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 204 205/****************************************************************************/ 206// Common header for all tables (Data table, Command table). 207// Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 208// And the pointer actually points to this header. 209/****************************************************************************/ 210 211typedef struct _ATOM_COMMON_TABLE_HEADER 212{ 213 USHORT usStructureSize; 214 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible 215 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware 216 //Image can't be updated, while Driver needs to carry the new table! 217}ATOM_COMMON_TABLE_HEADER; 218 219/****************************************************************************/ 220// Structure stores the ROM header. 221/****************************************************************************/ 222typedef struct _ATOM_ROM_HEADER 223{ 224 ATOM_COMMON_TABLE_HEADER sHeader; 225 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 226 //atombios should init it as "ATOM", don't change the position 227 USHORT usBiosRuntimeSegmentAddress; 228 USHORT usProtectedModeInfoOffset; 229 USHORT usConfigFilenameOffset; 230 USHORT usCRC_BlockOffset; 231 USHORT usBIOS_BootupMessageOffset; 232 USHORT usInt10Offset; 233 USHORT usPciBusDevInitCode; 234 USHORT usIoBaseAddress; 235 USHORT usSubsystemVendorID; 236 USHORT usSubsystemID; 237 USHORT usPCI_InfoOffset; 238 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 239 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 240 UCHAR ucExtendedFunctionCode; 241 UCHAR ucReserved; 242}ATOM_ROM_HEADER; 243 244 245typedef struct _ATOM_ROM_HEADER_V2_1 246{ 247 ATOM_COMMON_TABLE_HEADER sHeader; 248 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 249 //atombios should init it as "ATOM", don't change the position 250 USHORT usBiosRuntimeSegmentAddress; 251 USHORT usProtectedModeInfoOffset; 252 USHORT usConfigFilenameOffset; 253 USHORT usCRC_BlockOffset; 254 USHORT usBIOS_BootupMessageOffset; 255 USHORT usInt10Offset; 256 USHORT usPciBusDevInitCode; 257 USHORT usIoBaseAddress; 258 USHORT usSubsystemVendorID; 259 USHORT usSubsystemID; 260 USHORT usPCI_InfoOffset; 261 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 262 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 263 UCHAR ucExtendedFunctionCode; 264 UCHAR ucReserved; 265 ULONG ulPSPDirTableOffset; 266}ATOM_ROM_HEADER_V2_1; 267 268 269//==============================Command Table Portion==================================== 270 271 272/****************************************************************************/ 273// Structures used in Command.mtb 274/****************************************************************************/ 275typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 276 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 277 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 278 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 279 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 280 USHORT DIGxEncoderControl; //Only used by Bios 281 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 282 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 283 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 284 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 285 USHORT GPIOPinControl; //Atomic Table, only used by Bios 286 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 287 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 288 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 289 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 290 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 291 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 292 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 293 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 294 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 295 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 296 USHORT SetUniphyInstance; //Atomic Table, only used by Bios 297 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 298 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 299 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 300 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 301 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 302 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 303 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 304 USHORT GetConditionalGoldenSetting; //Only used by Bios 305 USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1 306 USHORT PatchMCSetting; //only used by BIOS 307 USHORT MC_SEQ_Control; //only used by BIOS 308 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting 309 USHORT EnableScaler; //Atomic Table, used only by Bios 310 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 311 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 312 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 313 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 314 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 315 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 316 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 317 USHORT GetSMUClockInfo; //Atomic Table, used only by Bios 318 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 319 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 320 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 321 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 322 USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK 323 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 324 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 325 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 326 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 327 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 328 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 329 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 330 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 331 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 332 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 333 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 334 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 335 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 336 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 337 USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 338 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 339 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 340 USHORT MemoryTraining; //Atomic Table, used only by Bios 341 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 342 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 343 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 344 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 345 USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1 346 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 347 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 348 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 349 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 350 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 351 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 352 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 353 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 354 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 355 USHORT DPEncoderService; //Function Table,only used by Bios 356 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 357}ATOM_MASTER_LIST_OF_COMMAND_TABLES; 358 359// For backward compatible 360#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 361#define DPTranslatorControl DIG2EncoderControl 362#define UNIPHYTransmitterControl DIG1TransmitterControl 363#define LVTMATransmitterControl DIG2TransmitterControl 364#define SetCRTC_DPM_State GetConditionalGoldenSetting 365#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance 366#define HPDInterruptService ReadHWAssistedI2CStatus 367#define EnableVGA_Access GetSCLKOverMCLKRatio 368#define EnableYUV GetDispObjectInfo 369#define DynamicClockGating EnableDispPowerGating 370#define SetupHWAssistedI2CStatus ComputeMemoryClockParam 371#define DAC2OutputControl ReadEfuseValue 372 373#define TMDSAEncoderControl PatchMCSetting 374#define LVDSEncoderControl MC_SEQ_Control 375#define LCD1OutputControl HW_Misc_Operation 376#define TV1OutputControl Gfx_Harvesting 377#define TVEncoderControl SMC_Init 378#define EnableHW_IconCursor SetDCEClock 379#define SetCRTC_Replication GetSMUClockInfo 380 381#define MemoryRefreshConversion Gfx_Init 382 383typedef struct _ATOM_MASTER_COMMAND_TABLE 384{ 385 ATOM_COMMON_TABLE_HEADER sHeader; 386 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 387}ATOM_MASTER_COMMAND_TABLE; 388 389/****************************************************************************/ 390// Structures used in every command table 391/****************************************************************************/ 392typedef struct _ATOM_TABLE_ATTRIBUTE 393{ 394#if ATOM_BIG_ENDIAN 395 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 396 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 397 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 398#else 399 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 400 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 401 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 402#endif 403}ATOM_TABLE_ATTRIBUTE; 404 405/****************************************************************************/ 406// Common header for all command tables. 407// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 408// And the pointer actually points to this header. 409/****************************************************************************/ 410typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 411{ 412 ATOM_COMMON_TABLE_HEADER CommonHeader; 413 ATOM_TABLE_ATTRIBUTE TableAttribute; 414}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 415 416/****************************************************************************/ 417// Structures used by ComputeMemoryEnginePLLTable 418/****************************************************************************/ 419 420#define COMPUTE_MEMORY_PLL_PARAM 1 421#define COMPUTE_ENGINE_PLL_PARAM 2 422#define ADJUST_MC_SETTING_PARAM 3 423 424/****************************************************************************/ 425// Structures used by AdjustMemoryControllerTable 426/****************************************************************************/ 427typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 428{ 429#if ATOM_BIG_ENDIAN 430 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 431 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 432 ULONG ulClockFreq:24; 433#else 434 ULONG ulClockFreq:24; 435 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 436 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 437#endif 438}ATOM_ADJUST_MEMORY_CLOCK_FREQ; 439#define POINTER_RETURN_FLAG 0x80 440 441typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 442{ 443 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 444 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 445 UCHAR ucReserved; //may expand to return larger Fbdiv later 446 UCHAR ucFbDiv; //return value 447 UCHAR ucPostDiv; //return value 448}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 449 450typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 451{ 452 ULONG ulClock; //When return, [23:0] return real clock 453 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 454 USHORT usFbDiv; //return Feedback value to be written to register 455 UCHAR ucPostDiv; //return post div to be written to register 456}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 457 458#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 459 460#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 461#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 462#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 463#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 464#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 465#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 466#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 467 468#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 469#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 470#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 471#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 472#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 473#define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path 474#define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only 475#define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only 476#define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only 477 478typedef struct _ATOM_COMPUTE_CLOCK_FREQ 479{ 480#if ATOM_BIG_ENDIAN 481 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 482 ULONG ulClockFreq:24; // in unit of 10kHz 483#else 484 ULONG ulClockFreq:24; // in unit of 10kHz 485 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 486#endif 487}ATOM_COMPUTE_CLOCK_FREQ; 488 489typedef struct _ATOM_S_MPLL_FB_DIVIDER 490{ 491 USHORT usFbDivFrac; 492 USHORT usFbDiv; 493}ATOM_S_MPLL_FB_DIVIDER; 494 495typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 496{ 497 union 498 { 499 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 500 ULONG ulClockParams; //ULONG access for BE 501 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 502 }; 503 UCHAR ucRefDiv; //Output Parameter 504 UCHAR ucPostDiv; //Output Parameter 505 UCHAR ucCntlFlag; //Output Parameter 506 UCHAR ucReserved; 507}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 508 509// ucCntlFlag 510#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 511#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 512#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 513#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 514 515 516// V4 are only used for APU which PLL outside GPU 517typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 518{ 519#if ATOM_BIG_ENDIAN 520 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 521 ULONG ulClock:24; //Input= target clock, output = actual clock 522#else 523 ULONG ulClock:24; //Input= target clock, output = actual clock 524 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 525#endif 526}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 527 528typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 529{ 530 union 531 { 532 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 533 ULONG ulClockParams; //ULONG access for BE 534 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 535 }; 536 UCHAR ucRefDiv; //Output Parameter 537 UCHAR ucPostDiv; //Output Parameter 538 union 539 { 540 UCHAR ucCntlFlag; //Output Flags 541 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 542 }; 543 UCHAR ucReserved; 544}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 545 546 547typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 548{ 549 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 550 ULONG ulReserved[2]; 551}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; 552 553//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 554#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 555#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 556#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 557 558 559typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 560{ 561 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 562 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider 563 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider 564 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider 565 UCHAR ucPllCntlFlag; //Output Flags: control flag 566 UCHAR ucReserved; 567}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; 568 569//ucPllCntlFlag 570#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 571 572typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 573{ 574 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 575 ULONG ulReserved[5]; 576}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7; 577 578//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 579#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 580#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 581#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 582 583typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 584{ 585 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 586 USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536 587 USHORT usSclk_fcw_int; //integer divider of fcwc 588 UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv 589 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved 590 UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 ) 591 UCHAR ucSscEnable; 592 USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable 593 USHORT usSsc_fcw1_int; //fcw1_int when SSC enable 594 USHORT usReserved; 595 USHORT usPcc_fcw_int; 596 USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable 597 USHORT usPcc_fcw_slew_frac; 598}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7; 599 600// ucInputFlag 601#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 602 603// use for ComputeMemoryClockParamTable 604typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 605{ 606 union 607 { 608 ULONG ulClock; 609 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 610 }; 611 UCHAR ucDllSpeed; //Output 612 UCHAR ucPostDiv; //Output 613 union{ 614 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 615 UCHAR ucPllCntlFlag; //Output: 616 }; 617 UCHAR ucBWCntl; 618}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 619 620// definition of ucInputFlag 621#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 622// definition of ucPllCntlFlag 623#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 624#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 625#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 626#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 627 628//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 629#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 630 631// use for ComputeMemoryClockParamTable 632typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 633{ 634 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; 635 ULONG ulReserved; 636}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2; 637 638typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 639{ 640 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; 641 USHORT usMclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536 642 USHORT usMclk_fcw_int; //integer divider of fcwc 643}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3; 644 645//Input parameter of DynamicMemorySettingsTable 646//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM 647typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 648{ 649 ATOM_COMPUTE_CLOCK_FREQ ulClock; 650 ULONG ulReserved[2]; 651}DYNAMICE_MEMORY_SETTINGS_PARAMETER; 652 653//Input parameter of DynamicMemorySettingsTable 654//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM 655typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 656{ 657 ATOM_COMPUTE_CLOCK_FREQ ulClock; 658 ULONG ulMemoryClock; 659 ULONG ulReserved; 660}DYNAMICE_ENGINE_SETTINGS_PARAMETER; 661 662//Input parameter of DynamicMemorySettingsTable ver2.1 and above 663//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM 664typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER 665{ 666 ATOM_COMPUTE_CLOCK_FREQ ulClock; 667 UCHAR ucMclkDPMState; 668 UCHAR ucReserved[3]; 669 ULONG ulReserved; 670}DYNAMICE_MC_DPM_SETTINGS_PARAMETER; 671 672//ucMclkDPMState 673#define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE 0 674#define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1 675#define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2 676 677typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 678{ 679 DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg; 680 DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg; 681 DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg; 682}DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1; 683 684 685/****************************************************************************/ 686// Structures used by SetEngineClockTable 687/****************************************************************************/ 688typedef struct _SET_ENGINE_CLOCK_PARAMETERS 689{ 690 ULONG ulTargetEngineClock; //In 10Khz unit 691}SET_ENGINE_CLOCK_PARAMETERS; 692 693typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 694{ 695 ULONG ulTargetEngineClock; //In 10Khz unit 696 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 697}SET_ENGINE_CLOCK_PS_ALLOCATION; 698 699typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2 700{ 701 ULONG ulTargetEngineClock; //In 10Khz unit 702 COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved; 703}SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2; 704 705 706/****************************************************************************/ 707// Structures used by SetMemoryClockTable 708/****************************************************************************/ 709typedef struct _SET_MEMORY_CLOCK_PARAMETERS 710{ 711 ULONG ulTargetMemoryClock; //In 10Khz unit 712}SET_MEMORY_CLOCK_PARAMETERS; 713 714typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 715{ 716 ULONG ulTargetMemoryClock; //In 10Khz unit 717 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 718}SET_MEMORY_CLOCK_PS_ALLOCATION; 719 720/****************************************************************************/ 721// Structures used by ASIC_Init.ctb 722/****************************************************************************/ 723typedef struct _ASIC_INIT_PARAMETERS 724{ 725 ULONG ulDefaultEngineClock; //In 10Khz unit 726 ULONG ulDefaultMemoryClock; //In 10Khz unit 727}ASIC_INIT_PARAMETERS; 728 729typedef struct _ASIC_INIT_PS_ALLOCATION 730{ 731 ASIC_INIT_PARAMETERS sASICInitClocks; 732 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 733}ASIC_INIT_PS_ALLOCATION; 734 735typedef struct _ASIC_INIT_CLOCK_PARAMETERS 736{ 737 ULONG ulClkFreqIn10Khz:24; 738 ULONG ucClkFlag:8; 739}ASIC_INIT_CLOCK_PARAMETERS; 740 741typedef struct _ASIC_INIT_PARAMETERS_V1_2 742{ 743 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit 744 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit 745}ASIC_INIT_PARAMETERS_V1_2; 746 747typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2 748{ 749 ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks; 750 ULONG ulReserved[8]; 751}ASIC_INIT_PS_ALLOCATION_V1_2; 752 753/****************************************************************************/ 754// Structure used by DynamicClockGatingTable.ctb 755/****************************************************************************/ 756typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 757{ 758 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 759 UCHAR ucPadding[3]; 760}DYNAMIC_CLOCK_GATING_PARAMETERS; 761#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 762 763/****************************************************************************/ 764// Structure used by EnableDispPowerGatingTable.ctb 765/****************************************************************************/ 766typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 767{ 768 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 769 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 770 UCHAR ucPadding[2]; 771}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 772 773typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION 774{ 775 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 776 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT 777 UCHAR ucPadding[2]; 778 ULONG ulReserved[4]; 779}ENABLE_DISP_POWER_GATING_PS_ALLOCATION; 780 781/****************************************************************************/ 782// Structure used by EnableASIC_StaticPwrMgtTable.ctb 783/****************************************************************************/ 784typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 785{ 786 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 787 UCHAR ucPadding[3]; 788}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 789#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 790 791/****************************************************************************/ 792// Structures used by DAC_LoadDetectionTable.ctb 793/****************************************************************************/ 794typedef struct _DAC_LOAD_DETECTION_PARAMETERS 795{ 796 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 797 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 798 UCHAR ucMisc; //Valid only when table revision =1.3 and above 799}DAC_LOAD_DETECTION_PARAMETERS; 800 801// DAC_LOAD_DETECTION_PARAMETERS.ucMisc 802#define DAC_LOAD_MISC_YPrPb 0x01 803 804typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 805{ 806 DAC_LOAD_DETECTION_PARAMETERS sDacload; 807 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 808}DAC_LOAD_DETECTION_PS_ALLOCATION; 809 810/****************************************************************************/ 811// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 812/****************************************************************************/ 813typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 814{ 815 USHORT usPixelClock; // in 10KHz; for bios convenient 816 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 817 UCHAR ucAction; // 0: turn off encoder 818 // 1: setup and turn on encoder 819 // 7: ATOM_ENCODER_INIT Initialize DAC 820}DAC_ENCODER_CONTROL_PARAMETERS; 821 822#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 823 824/****************************************************************************/ 825// Structures used by DIG1EncoderControlTable 826// DIG2EncoderControlTable 827// ExternalEncoderControlTable 828/****************************************************************************/ 829typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 830{ 831 USHORT usPixelClock; // in 10KHz; for bios convenient 832 UCHAR ucConfig; 833 // [2] Link Select: 834 // =0: PHY linkA if bfLane<3 835 // =1: PHY linkB if bfLanes<3 836 // =0: PHY linkA+B if bfLanes=3 837 // [3] Transmitter Sel 838 // =0: UNIPHY or PCIEPHY 839 // =1: LVTMA 840 UCHAR ucAction; // =0: turn off encoder 841 // =1: turn on encoder 842 UCHAR ucEncoderMode; 843 // =0: DP encoder 844 // =1: LVDS encoder 845 // =2: DVI encoder 846 // =3: HDMI encoder 847 // =4: SDVO encoder 848 UCHAR ucLaneNum; // how many lanes to enable 849 UCHAR ucReserved[2]; 850}DIG_ENCODER_CONTROL_PARAMETERS; 851#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 852#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 853 854//ucConfig 855#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 856#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 857#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 858#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 859#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 860#define ATOM_ENCODER_CONFIG_LINKA 0x00 861#define ATOM_ENCODER_CONFIG_LINKB 0x04 862#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 863#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 864#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 865#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 866#define ATOM_ENCODER_CONFIG_LVTMA 0x08 867#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 868#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 869#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 870// ucAction 871// ATOM_ENABLE: Enable Encoder 872// ATOM_DISABLE: Disable Encoder 873 874//ucEncoderMode 875#define ATOM_ENCODER_MODE_DP 0 876#define ATOM_ENCODER_MODE_LVDS 1 877#define ATOM_ENCODER_MODE_DVI 2 878#define ATOM_ENCODER_MODE_HDMI 3 879#define ATOM_ENCODER_MODE_SDVO 4 880#define ATOM_ENCODER_MODE_DP_AUDIO 5 881#define ATOM_ENCODER_MODE_TV 13 882#define ATOM_ENCODER_MODE_CV 14 883#define ATOM_ENCODER_MODE_CRT 15 884#define ATOM_ENCODER_MODE_DVO 16 885#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 886#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 887 888 889typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 890{ 891#if ATOM_BIG_ENDIAN 892 UCHAR ucReserved1:2; 893 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 894 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 895 UCHAR ucReserved:1; 896 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 897#else 898 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 899 UCHAR ucReserved:1; 900 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 901 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 902 UCHAR ucReserved1:2; 903#endif 904}ATOM_DIG_ENCODER_CONFIG_V2; 905 906 907typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 908{ 909 USHORT usPixelClock; // in 10KHz; for bios convenient 910 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 911 UCHAR ucAction; 912 UCHAR ucEncoderMode; 913 // =0: DP encoder 914 // =1: LVDS encoder 915 // =2: DVI encoder 916 // =3: HDMI encoder 917 // =4: SDVO encoder 918 UCHAR ucLaneNum; // how many lanes to enable 919 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 920 UCHAR ucReserved; 921}DIG_ENCODER_CONTROL_PARAMETERS_V2; 922 923//ucConfig 924#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 925#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 926#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 927#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 928#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 929#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 930#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 931#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 932#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 933#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 934 935// ucAction: 936// ATOM_DISABLE 937// ATOM_ENABLE 938#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 939#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 940#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 941#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 942#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 943#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 944#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 945#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 946#define ATOM_ENCODER_CMD_SETUP 0x0f 947#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 948 949// New Command for DIGxEncoderControlTable v1.5 950#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14 951#define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP 952#define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table 953#define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table 954 955// ucStatus 956#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 957#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 958 959//ucTableFormatRevision=1 960//ucTableContentRevision=3 961// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 962typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 963{ 964#if ATOM_BIG_ENDIAN 965 UCHAR ucReserved1:1; 966 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 967 UCHAR ucReserved:3; 968 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 969#else 970 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 971 UCHAR ucReserved:3; 972 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 973 UCHAR ucReserved1:1; 974#endif 975}ATOM_DIG_ENCODER_CONFIG_V3; 976 977#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 978#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 979#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 980#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 981#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 982#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 983#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 984#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 985#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 986#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 987 988typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 989{ 990 USHORT usPixelClock; // in 10KHz; for bios convenient 991 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 992 UCHAR ucAction; 993 union{ 994 UCHAR ucEncoderMode; 995 // =0: DP encoder 996 // =1: LVDS encoder 997 // =2: DVI encoder 998 // =3: HDMI encoder 999 // =4: SDVO encoder 1000 // =5: DP audio 1001 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 1002 // =0: external DP 1003 // =0x1: internal DP2 1004 // =0x11: internal DP1 for NutMeg/Travis DP translator 1005 }; 1006 UCHAR ucLaneNum; // how many lanes to enable 1007 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 1008 UCHAR ucReserved; 1009}DIG_ENCODER_CONTROL_PARAMETERS_V3; 1010 1011//ucTableFormatRevision=1 1012//ucTableContentRevision=4 1013// start from NI 1014// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 1015typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 1016{ 1017#if ATOM_BIG_ENDIAN 1018 UCHAR ucReserved1:1; 1019 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 1020 UCHAR ucReserved:2; 1021 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 1022#else 1023 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 1024 UCHAR ucReserved:2; 1025 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 1026 UCHAR ucReserved1:1; 1027#endif 1028}ATOM_DIG_ENCODER_CONFIG_V4; 1029 1030#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 1031#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 1032#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 1033#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 1034#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 1035#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 1036#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 1037#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 1038#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 1039#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 1040#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 1041#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 1042#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 1043 1044typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 1045{ 1046 USHORT usPixelClock; // in 10KHz; for bios convenient 1047 union{ 1048 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 1049 UCHAR ucConfig; 1050 }; 1051 UCHAR ucAction; 1052 union{ 1053 UCHAR ucEncoderMode; 1054 // =0: DP encoder 1055 // =1: LVDS encoder 1056 // =2: DVI encoder 1057 // =3: HDMI encoder 1058 // =4: SDVO encoder 1059 // =5: DP audio 1060 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 1061 // =0: external DP 1062 // =0x1: internal DP2 1063 // =0x11: internal DP1 for NutMeg/Travis DP translator 1064 }; 1065 UCHAR ucLaneNum; // how many lanes to enable 1066 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 1067 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 1068}DIG_ENCODER_CONTROL_PARAMETERS_V4; 1069 1070// define ucBitPerColor: 1071#define PANEL_BPC_UNDEFINE 0x00 1072#define PANEL_6BIT_PER_COLOR 0x01 1073#define PANEL_8BIT_PER_COLOR 0x02 1074#define PANEL_10BIT_PER_COLOR 0x03 1075#define PANEL_12BIT_PER_COLOR 0x04 1076#define PANEL_16BIT_PER_COLOR 0x05 1077 1078//define ucPanelMode 1079#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 1080#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 1081#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 1082 1083 1084typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V5 1085{ 1086 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1087 UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP 1088 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1089 UCHAR ucLaneNum; // Lane number 1090 ULONG ulPixelClock; // Pixel Clock in 10Khz 1091 UCHAR ucBitPerColor; 1092 UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 1093 UCHAR ucReserved[2]; 1094}ENCODER_STREAM_SETUP_PARAMETERS_V5; 1095 1096typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V5 1097{ 1098 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1099 UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP 1100 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1101 UCHAR ucLaneNum; // Lane number 1102 ULONG ulSymClock; // Symbol Clock in 10Khz 1103 UCHAR ucHPDSel; 1104 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 1105 UCHAR ucReserved[2]; 1106}ENCODER_LINK_SETUP_PARAMETERS_V5; 1107 1108typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V5 1109{ 1110 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1111 UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP 1112 UCHAR ucPanelMode; // =0: external DP 1113 // =0x1: internal DP2 1114 // =0x11: internal DP1 NutMeg/Travis DP Translator 1115 UCHAR ucReserved; 1116 ULONG ulReserved[2]; 1117}DP_PANEL_MODE_SETUP_PARAMETERS_V5; 1118 1119typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V5 1120{ 1121 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1122 UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters 1123 UCHAR ucReserved[2]; 1124 ULONG ulReserved[2]; 1125}ENCODER_GENERIC_CMD_PARAMETERS_V5; 1126 1127//ucDigId 1128#define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER 0x00 1129#define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER 0x01 1130#define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER 0x02 1131#define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER 0x03 1132#define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER 0x04 1133#define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER 0x05 1134#define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER 0x06 1135 1136 1137typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V5 1138{ 1139 ENCODER_GENERIC_CMD_PARAMETERS_V5 asCmdParam; 1140 ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam; 1141 ENCODER_LINK_SETUP_PARAMETERS_V5 asLinkParam; 1142 DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam; 1143}DIG_ENCODER_CONTROL_PARAMETERS_V5; 1144 1145 1146/****************************************************************************/ 1147// Structures used by UNIPHYTransmitterControlTable 1148// LVTMATransmitterControlTable 1149// DVOOutputControlTable 1150/****************************************************************************/ 1151typedef struct _ATOM_DP_VS_MODE 1152{ 1153 UCHAR ucLaneSel; 1154 UCHAR ucLaneSet; 1155}ATOM_DP_VS_MODE; 1156 1157typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 1158{ 1159 union 1160 { 1161 USHORT usPixelClock; // in 10KHz; for bios convenient 1162 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1163 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1164 }; 1165 UCHAR ucConfig; 1166 // [0]=0: 4 lane Link, 1167 // =1: 8 lane Link ( Dual Links TMDS ) 1168 // [1]=0: InCoherent mode 1169 // =1: Coherent Mode 1170 // [2] Link Select: 1171 // =0: PHY linkA if bfLane<3 1172 // =1: PHY linkB if bfLanes<3 1173 // =0: PHY linkA+B if bfLanes=3 1174 // [5:4]PCIE lane Sel 1175 // =0: lane 0~3 or 0~7 1176 // =1: lane 4~7 1177 // =2: lane 8~11 or 8~15 1178 // =3: lane 12~15 1179 UCHAR ucAction; // =0: turn off encoder 1180 // =1: turn on encoder 1181 UCHAR ucReserved[4]; 1182}DIG_TRANSMITTER_CONTROL_PARAMETERS; 1183 1184#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 1185 1186//ucInitInfo 1187#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 1188 1189//ucConfig 1190#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 1191#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 1192#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 1193#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 1194#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 1195#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 1196#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 1197 1198#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1199#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1200#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1201 1202#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 1203#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 1204#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 1205#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 1206#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 1207#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 1208#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 1209#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 1210#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 1211#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 1212#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 1213 1214//ucAction 1215#define ATOM_TRANSMITTER_ACTION_DISABLE 0 1216#define ATOM_TRANSMITTER_ACTION_ENABLE 1 1217#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 1218#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 1219#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 1220#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 1221#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 1222#define ATOM_TRANSMITTER_ACTION_INIT 7 1223#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 1224#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 1225#define ATOM_TRANSMITTER_ACTION_SETUP 10 1226#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 1227#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 1228#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 1229 1230// Following are used for DigTransmitterControlTable ver1.2 1231typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 1232{ 1233#if ATOM_BIG_ENDIAN 1234 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1235 // =1 Dig Transmitter 2 ( Uniphy CD ) 1236 // =2 Dig Transmitter 3 ( Uniphy EF ) 1237 UCHAR ucReserved:1; 1238 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1239 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1240 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1241 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1242 1243 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1244 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1245#else 1246 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1247 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1248 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1249 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1250 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1251 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1252 UCHAR ucReserved:1; 1253 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1254 // =1 Dig Transmitter 2 ( Uniphy CD ) 1255 // =2 Dig Transmitter 3 ( Uniphy EF ) 1256#endif 1257}ATOM_DIG_TRANSMITTER_CONFIG_V2; 1258 1259//ucConfig 1260//Bit0 1261#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1262 1263//Bit1 1264#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1265 1266//Bit2 1267#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1268#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1269#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1270 1271// Bit3 1272#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1273#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1274#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1275 1276// Bit4 1277#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1278 1279// Bit7:6 1280#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1281#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1282#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1283#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1284 1285typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1286{ 1287 union 1288 { 1289 USHORT usPixelClock; // in 10KHz; for bios convenient 1290 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1291 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1292 }; 1293 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1294 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1295 UCHAR ucReserved[4]; 1296}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1297 1298typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1299{ 1300#if ATOM_BIG_ENDIAN 1301 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1302 // =1 Dig Transmitter 2 ( Uniphy CD ) 1303 // =2 Dig Transmitter 3 ( Uniphy EF ) 1304 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1305 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1306 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1307 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1308 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1309 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1310#else 1311 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1312 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1313 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1314 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1315 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1316 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1317 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1318 // =1 Dig Transmitter 2 ( Uniphy CD ) 1319 // =2 Dig Transmitter 3 ( Uniphy EF ) 1320#endif 1321}ATOM_DIG_TRANSMITTER_CONFIG_V3; 1322 1323 1324typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1325{ 1326 union 1327 { 1328 USHORT usPixelClock; // in 10KHz; for bios convenient 1329 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1330 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1331 }; 1332 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1333 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1334 UCHAR ucLaneNum; 1335 UCHAR ucReserved[3]; 1336}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1337 1338//ucConfig 1339//Bit0 1340#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1341 1342//Bit1 1343#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1344 1345//Bit2 1346#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1347#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1348#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1349 1350// Bit3 1351#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1352#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1353#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1354 1355// Bit5:4 1356#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1357#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1358#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1359#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1360 1361// Bit7:6 1362#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1363#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1364#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1365#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1366 1367 1368/****************************************************************************/ 1369// Structures used by UNIPHYTransmitterControlTable V1.4 1370// ASIC Families: NI 1371// ucTableFormatRevision=1 1372// ucTableContentRevision=4 1373/****************************************************************************/ 1374typedef struct _ATOM_DP_VS_MODE_V4 1375{ 1376 UCHAR ucLaneSel; 1377 union 1378 { 1379 UCHAR ucLaneSet; 1380 struct { 1381#if ATOM_BIG_ENDIAN 1382 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1383 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1384 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1385#else 1386 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1387 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1388 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1389#endif 1390 }; 1391 }; 1392}ATOM_DP_VS_MODE_V4; 1393 1394typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1395{ 1396#if ATOM_BIG_ENDIAN 1397 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1398 // =1 Dig Transmitter 2 ( Uniphy CD ) 1399 // =2 Dig Transmitter 3 ( Uniphy EF ) 1400 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1401 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1402 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1403 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1404 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1405 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1406#else 1407 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1408 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1409 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1410 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1411 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1412 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1413 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1414 // =1 Dig Transmitter 2 ( Uniphy CD ) 1415 // =2 Dig Transmitter 3 ( Uniphy EF ) 1416#endif 1417}ATOM_DIG_TRANSMITTER_CONFIG_V4; 1418 1419typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1420{ 1421 union 1422 { 1423 USHORT usPixelClock; // in 10KHz; for bios convenient 1424 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1425 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1426 }; 1427 union 1428 { 1429 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1430 UCHAR ucConfig; 1431 }; 1432 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1433 UCHAR ucLaneNum; 1434 UCHAR ucReserved[3]; 1435}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1436 1437//ucConfig 1438//Bit0 1439#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1440//Bit1 1441#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1442//Bit2 1443#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1444#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1445#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1446// Bit3 1447#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1448#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1449#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1450// Bit5:4 1451#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1452#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1453#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1454#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1455#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1456// Bit7:6 1457#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1458#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1459#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1460#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1461 1462 1463typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1464{ 1465#if ATOM_BIG_ENDIAN 1466 UCHAR ucReservd1:1; 1467 UCHAR ucHPDSel:3; 1468 UCHAR ucPhyClkSrcId:2; 1469 UCHAR ucCoherentMode:1; 1470 UCHAR ucReserved:1; 1471#else 1472 UCHAR ucReserved:1; 1473 UCHAR ucCoherentMode:1; 1474 UCHAR ucPhyClkSrcId:2; 1475 UCHAR ucHPDSel:3; 1476 UCHAR ucReservd1:1; 1477#endif 1478}ATOM_DIG_TRANSMITTER_CONFIG_V5; 1479 1480typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1481{ 1482 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1483 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1484 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1485 UCHAR ucLaneNum; // indicate lane number 1-8 1486 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1487 UCHAR ucDigMode; // indicate DIG mode 1488 union{ 1489 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1490 UCHAR ucConfig; 1491 }; 1492 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1493 UCHAR ucDPLaneSet; 1494 UCHAR ucReserved; 1495 UCHAR ucReserved1; 1496}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1497 1498//ucPhyId 1499#define ATOM_PHY_ID_UNIPHYA 0 1500#define ATOM_PHY_ID_UNIPHYB 1 1501#define ATOM_PHY_ID_UNIPHYC 2 1502#define ATOM_PHY_ID_UNIPHYD 3 1503#define ATOM_PHY_ID_UNIPHYE 4 1504#define ATOM_PHY_ID_UNIPHYF 5 1505#define ATOM_PHY_ID_UNIPHYG 6 1506 1507// ucDigEncoderSel 1508#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1509#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1510#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1511#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1512#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1513#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1514#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1515 1516// ucDigMode 1517#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1518#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1519#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1520#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1521#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1522#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1523 1524// ucDPLaneSet 1525#define DP_LANE_SET__0DB_0_4V 0x00 1526#define DP_LANE_SET__0DB_0_6V 0x01 1527#define DP_LANE_SET__0DB_0_8V 0x02 1528#define DP_LANE_SET__0DB_1_2V 0x03 1529#define DP_LANE_SET__3_5DB_0_4V 0x08 1530#define DP_LANE_SET__3_5DB_0_6V 0x09 1531#define DP_LANE_SET__3_5DB_0_8V 0x0a 1532#define DP_LANE_SET__6DB_0_4V 0x10 1533#define DP_LANE_SET__6DB_0_6V 0x11 1534#define DP_LANE_SET__9_5DB_0_4V 0x18 1535 1536// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1537// Bit1 1538#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1539 1540// Bit3:2 1541#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1542#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1543 1544#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1545#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1546#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1547#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1548// Bit6:4 1549#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1550#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1551 1552#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1553#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1554#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1555#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1556#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1557#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1558#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1559 1560#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1561 1562typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 1563{ 1564 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1565 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1566 union 1567 { 1568 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1569 UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 1570 }; 1571 UCHAR ucLaneNum; // Lane number 1572 ULONG ulSymClock; // Symbol Clock in 10Khz 1573 UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 1574 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 1575 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1576 UCHAR ucReserved; 1577 ULONG ulReserved; 1578}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6; 1579 1580 1581// ucDigEncoderSel 1582#define ATOM_TRANMSITTER_V6__DIGA_SEL 0x01 1583#define ATOM_TRANMSITTER_V6__DIGB_SEL 0x02 1584#define ATOM_TRANMSITTER_V6__DIGC_SEL 0x04 1585#define ATOM_TRANMSITTER_V6__DIGD_SEL 0x08 1586#define ATOM_TRANMSITTER_V6__DIGE_SEL 0x10 1587#define ATOM_TRANMSITTER_V6__DIGF_SEL 0x20 1588#define ATOM_TRANMSITTER_V6__DIGG_SEL 0x40 1589 1590// ucDigMode 1591#define ATOM_TRANSMITTER_DIGMODE_V6_DP 0 1592#define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2 1593#define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 3 1594#define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 5 1595 1596//ucHPDSel 1597#define ATOM_TRANSMITTER_V6_NO_HPD_SEL 0x00 1598#define ATOM_TRANSMITTER_V6_HPD1_SEL 0x01 1599#define ATOM_TRANSMITTER_V6_HPD2_SEL 0x02 1600#define ATOM_TRANSMITTER_V6_HPD3_SEL 0x03 1601#define ATOM_TRANSMITTER_V6_HPD4_SEL 0x04 1602#define ATOM_TRANSMITTER_V6_HPD5_SEL 0x05 1603#define ATOM_TRANSMITTER_V6_HPD6_SEL 0x06 1604 1605 1606/****************************************************************************/ 1607// Structures used by ExternalEncoderControlTable V1.3 1608// ASIC Families: Evergreen, Llano, NI 1609// ucTableFormatRevision=1 1610// ucTableContentRevision=3 1611/****************************************************************************/ 1612 1613typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1614{ 1615 union{ 1616 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1617 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1618 }; 1619 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1620 UCHAR ucAction; // 1621 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1622 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1623 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1624 UCHAR ucReserved; 1625}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1626 1627// ucAction 1628#define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1629#define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1630#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1631#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1632#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1633#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1634#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1635#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1636 1637// ucConfig 1638#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1639#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1640#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1641#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1642#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70 1643#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1644#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1645#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1646 1647typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1648{ 1649 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1650 ULONG ulReserved[2]; 1651}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1652 1653 1654/****************************************************************************/ 1655// Structures used by DAC1OuputControlTable 1656// DAC2OuputControlTable 1657// LVTMAOutputControlTable (Before DEC30) 1658// TMDSAOutputControlTable (Before DEC30) 1659/****************************************************************************/ 1660typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1661{ 1662 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1663 // When the display is LCD, in addition to above: 1664 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1665 // ATOM_LCD_SELFTEST_STOP 1666 1667 UCHAR aucPadding[3]; // padding to DWORD aligned 1668}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1669 1670#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1671 1672 1673#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1674#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1675 1676#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1677#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1678 1679#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1680#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1681 1682#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1683#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1684 1685#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1686#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1687 1688#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1689#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1690 1691#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1692#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1693 1694#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1695#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1696#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1697 1698 1699typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2 1700{ 1701 // Possible value of ucAction 1702 // ATOM_TRANSMITTER_ACTION_LCD_BLON 1703 // ATOM_TRANSMITTER_ACTION_LCD_BLOFF 1704 // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 1705 // ATOM_TRANSMITTER_ACTION_POWER_ON 1706 // ATOM_TRANSMITTER_ACTION_POWER_OFF 1707 UCHAR ucAction; 1708 UCHAR ucBriLevel; 1709 USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz 1710}LVTMA_OUTPUT_CONTROL_PARAMETERS_V2; 1711 1712 1713 1714/****************************************************************************/ 1715// Structures used by BlankCRTCTable 1716/****************************************************************************/ 1717typedef struct _BLANK_CRTC_PARAMETERS 1718{ 1719 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1720 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1721 USHORT usBlackColorRCr; 1722 USHORT usBlackColorGY; 1723 USHORT usBlackColorBCb; 1724}BLANK_CRTC_PARAMETERS; 1725#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1726 1727/****************************************************************************/ 1728// Structures used by EnableCRTCTable 1729// EnableCRTCMemReqTable 1730// UpdateCRTC_DoubleBufferRegistersTable 1731/****************************************************************************/ 1732typedef struct _ENABLE_CRTC_PARAMETERS 1733{ 1734 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1735 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1736 UCHAR ucPadding[2]; 1737}ENABLE_CRTC_PARAMETERS; 1738#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1739 1740/****************************************************************************/ 1741// Structures used by SetCRTC_OverScanTable 1742/****************************************************************************/ 1743typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1744{ 1745 USHORT usOverscanRight; // right 1746 USHORT usOverscanLeft; // left 1747 USHORT usOverscanBottom; // bottom 1748 USHORT usOverscanTop; // top 1749 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1750 UCHAR ucPadding[3]; 1751}SET_CRTC_OVERSCAN_PARAMETERS; 1752#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1753 1754/****************************************************************************/ 1755// Structures used by SetCRTC_ReplicationTable 1756/****************************************************************************/ 1757typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1758{ 1759 UCHAR ucH_Replication; // horizontal replication 1760 UCHAR ucV_Replication; // vertical replication 1761 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1762 UCHAR ucPadding; 1763}SET_CRTC_REPLICATION_PARAMETERS; 1764#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1765 1766/****************************************************************************/ 1767// Structures used by SelectCRTC_SourceTable 1768/****************************************************************************/ 1769typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1770{ 1771 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1772 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1773 UCHAR ucPadding[2]; 1774}SELECT_CRTC_SOURCE_PARAMETERS; 1775#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1776 1777typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1778{ 1779 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1780 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1781 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1782 UCHAR ucPadding; 1783}SELECT_CRTC_SOURCE_PARAMETERS_V2; 1784 1785//ucEncoderID 1786//#define ASIC_INT_DAC1_ENCODER_ID 0x00 1787//#define ASIC_INT_TV_ENCODER_ID 0x02 1788//#define ASIC_INT_DIG1_ENCODER_ID 0x03 1789//#define ASIC_INT_DAC2_ENCODER_ID 0x04 1790//#define ASIC_EXT_TV_ENCODER_ID 0x06 1791//#define ASIC_INT_DVO_ENCODER_ID 0x07 1792//#define ASIC_INT_DIG2_ENCODER_ID 0x09 1793//#define ASIC_EXT_DIG_ENCODER_ID 0x05 1794 1795//ucEncodeMode 1796//#define ATOM_ENCODER_MODE_DP 0 1797//#define ATOM_ENCODER_MODE_LVDS 1 1798//#define ATOM_ENCODER_MODE_DVI 2 1799//#define ATOM_ENCODER_MODE_HDMI 3 1800//#define ATOM_ENCODER_MODE_SDVO 4 1801//#define ATOM_ENCODER_MODE_TV 13 1802//#define ATOM_ENCODER_MODE_CV 14 1803//#define ATOM_ENCODER_MODE_CRT 15 1804 1805 1806typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3 1807{ 1808 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1809 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1810 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1811 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR 1812}SELECT_CRTC_SOURCE_PARAMETERS_V3; 1813 1814 1815/****************************************************************************/ 1816// Structures used by SetPixelClockTable 1817// GetPixelClockTable 1818/****************************************************************************/ 1819//Major revision=1., Minor revision=1 1820typedef struct _PIXEL_CLOCK_PARAMETERS 1821{ 1822 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1823 // 0 means disable PPLL 1824 USHORT usRefDiv; // Reference divider 1825 USHORT usFbDiv; // feedback divider 1826 UCHAR ucPostDiv; // post divider 1827 UCHAR ucFracFbDiv; // fractional feedback divider 1828 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1829 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1830 UCHAR ucCRTC; // Which CRTC uses this Ppll 1831 UCHAR ucPadding; 1832}PIXEL_CLOCK_PARAMETERS; 1833 1834//Major revision=1., Minor revision=2, add ucMiscIfno 1835//ucMiscInfo: 1836#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1837#define MISC_DEVICE_INDEX_MASK 0xF0 1838#define MISC_DEVICE_INDEX_SHIFT 4 1839 1840typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1841{ 1842 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1843 // 0 means disable PPLL 1844 USHORT usRefDiv; // Reference divider 1845 USHORT usFbDiv; // feedback divider 1846 UCHAR ucPostDiv; // post divider 1847 UCHAR ucFracFbDiv; // fractional feedback divider 1848 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1849 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1850 UCHAR ucCRTC; // Which CRTC uses this Ppll 1851 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1852}PIXEL_CLOCK_PARAMETERS_V2; 1853 1854//Major revision=1., Minor revision=3, structure/definition change 1855//ucEncoderMode: 1856//ATOM_ENCODER_MODE_DP 1857//ATOM_ENOCDER_MODE_LVDS 1858//ATOM_ENOCDER_MODE_DVI 1859//ATOM_ENOCDER_MODE_HDMI 1860//ATOM_ENOCDER_MODE_SDVO 1861//ATOM_ENCODER_MODE_TV 13 1862//ATOM_ENCODER_MODE_CV 14 1863//ATOM_ENCODER_MODE_CRT 15 1864 1865//ucDVOConfig 1866//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1867//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1868//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1869//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1870//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1871//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1872//#define DVO_ENCODER_CONFIG_24BIT 0x08 1873 1874//ucMiscInfo: also changed, see below 1875#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1876#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1877#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1878#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1879#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1880#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1881#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1882// V1.4 for RoadRunner 1883#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1884#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1885 1886 1887typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1888{ 1889 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1890 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1891 USHORT usRefDiv; // Reference divider 1892 USHORT usFbDiv; // feedback divider 1893 UCHAR ucPostDiv; // post divider 1894 UCHAR ucFracFbDiv; // fractional feedback divider 1895 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1896 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1897 union 1898 { 1899 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1900 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1901 }; 1902 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1903 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1904 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1905}PIXEL_CLOCK_PARAMETERS_V3; 1906 1907#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1908#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1909 1910 1911typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1912{ 1913 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1914 // drive the pixel clock. not used for DCPLL case. 1915 union{ 1916 UCHAR ucReserved; 1917 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1918 }; 1919 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1920 // 0 means disable PPLL/DCPLL. 1921 USHORT usFbDiv; // feedback divider integer part. 1922 UCHAR ucPostDiv; // post divider. 1923 UCHAR ucRefDiv; // Reference divider 1924 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1925 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1926 // indicate which graphic encoder will be used. 1927 UCHAR ucEncoderMode; // Encoder mode: 1928 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1929 // bit[1]= when VGA timing is used. 1930 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1931 // bit[4]= RefClock source for PPLL. 1932 // =0: XTLAIN( default mode ) 1933 // =1: other external clock source, which is pre-defined 1934 // by VBIOS depend on the feature required. 1935 // bit[7:5]: reserved. 1936 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1937 1938}PIXEL_CLOCK_PARAMETERS_V5; 1939 1940#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1941#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1942#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1943#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1944#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1945#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1946#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1947 1948typedef struct _CRTC_PIXEL_CLOCK_FREQ 1949{ 1950#if ATOM_BIG_ENDIAN 1951 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1952 // drive the pixel clock. not used for DCPLL case. 1953 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1954 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1955#else 1956 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1957 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1958 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1959 // drive the pixel clock. not used for DCPLL case. 1960#endif 1961}CRTC_PIXEL_CLOCK_FREQ; 1962 1963typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1964{ 1965 union{ 1966 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1967 ULONG ulDispEngClkFreq; // dispclk frequency 1968 }; 1969 USHORT usFbDiv; // feedback divider integer part. 1970 UCHAR ucPostDiv; // post divider. 1971 UCHAR ucRefDiv; // Reference divider 1972 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1973 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1974 // indicate which graphic encoder will be used. 1975 UCHAR ucEncoderMode; // Encoder mode: 1976 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1977 // bit[1]= when VGA timing is used. 1978 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1979 // bit[4]= RefClock source for PPLL. 1980 // =0: XTLAIN( default mode ) 1981 // =1: other external clock source, which is pre-defined 1982 // by VBIOS depend on the feature required. 1983 // bit[7:5]: reserved. 1984 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1985 1986}PIXEL_CLOCK_PARAMETERS_V6; 1987 1988#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1989#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1990#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1991#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1992#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1993#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1) 1994#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1995#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4) 1996#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1997#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1998#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1999#define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40 2000 2001typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 2002{ 2003 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 2004}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 2005 2006typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 2007{ 2008 UCHAR ucStatus; 2009 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 2010 UCHAR ucReserved[2]; 2011}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 2012 2013typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 2014{ 2015 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 2016}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 2017 2018typedef struct _PIXEL_CLOCK_PARAMETERS_V7 2019{ 2020 ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 2021 2022 UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 2023 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 2024 // indicate which graphic encoder will be used. 2025 UCHAR ucEncoderMode; // Encoder mode: 2026 UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk 2027 // bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk ) 2028 // bit[5:4]= RefClock source for PPLL. 2029 // =0: XTLAIN( default mode ) 2030 // =1: pcie 2031 // =2: GENLK 2032 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 2033 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp 2034 UCHAR ucReserved[2]; 2035 ULONG ulReserved; 2036}PIXEL_CLOCK_PARAMETERS_V7; 2037 2038//ucMiscInfo 2039#define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL 0x01 2040#define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL 0x02 2041#define PIXEL_CLOCK_V7_MISC_YUV420_MODE 0x04 2042#define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN 0x08 2043#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC 0x30 2044#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN 0x00 2045#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE 0x10 2046#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK 0x20 2047 2048//ucDeepColorRatio 2049#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2050#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2051#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2052#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2053 2054// SetDCEClockTable input parameter for DCE11.1 2055typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_1 2056{ 2057 ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz. 2058 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS 2059 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1 2060 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1 2061 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1 2062}SET_DCE_CLOCK_PARAMETERS_V1_1; 2063 2064 2065typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1 2066{ 2067 SET_DCE_CLOCK_PARAMETERS_V1_1 asParam; 2068 ULONG ulReserved[2]; 2069}SET_DCE_CLOCK_PS_ALLOCATION_V1_1; 2070 2071//SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag 2072#define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK 0x01 2073#define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01 2074#define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02 2075 2076// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above 2077typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1 2078{ 2079 ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 2080 UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 2081 UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 2082 UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 2083 UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 2084}SET_DCE_CLOCK_PARAMETERS_V2_1; 2085 2086//ucDCEClkType 2087#define DCE_CLOCK_TYPE_DISPCLK 0 2088#define DCE_CLOCK_TYPE_DPREFCLK 1 2089#define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable 2090 2091//ucDCEClkFlag when ucDCEClkType == DPREFCLK 2092#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK 0x03 2093#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA 0x00 2094#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK 0x01 2095#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE 0x02 2096#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN 0x03 2097 2098//ucDCEClkFlag when ucDCEClkType == PIXCLK 2099#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x03 2100#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2101#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2102#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2103#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2104#define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x04 2105 2106typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_1 2107{ 2108 SET_DCE_CLOCK_PARAMETERS_V2_1 asParam; 2109 ULONG ulReserved[2]; 2110}SET_DCE_CLOCK_PS_ALLOCATION_V2_1; 2111 2112 2113 2114/****************************************************************************/ 2115// Structures used by AdjustDisplayPllTable 2116/****************************************************************************/ 2117typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 2118{ 2119 USHORT usPixelClock; 2120 UCHAR ucTransmitterID; 2121 UCHAR ucEncodeMode; 2122 union 2123 { 2124 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 2125 UCHAR ucConfig; //if none DVO, not defined yet 2126 }; 2127 UCHAR ucReserved[3]; 2128}ADJUST_DISPLAY_PLL_PARAMETERS; 2129 2130#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 2131#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 2132 2133typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 2134{ 2135 USHORT usPixelClock; // target pixel clock 2136 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 2137 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 2138 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 2139 UCHAR ucExtTransmitterID; // external encoder id. 2140 UCHAR ucReserved[2]; 2141}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 2142 2143// usDispPllConfig v1.2 for RoadRunner 2144#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 2145#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 2146#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 2147#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 2148#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 2149#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 2150#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 2151#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 2152#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 2153#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 2154 2155 2156typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 2157{ 2158 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 2159 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 2160 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 2161 UCHAR ucReserved[2]; 2162}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 2163 2164typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 2165{ 2166 union 2167 { 2168 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 2169 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 2170 }; 2171} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 2172 2173/****************************************************************************/ 2174// Structures used by EnableYUVTable 2175/****************************************************************************/ 2176typedef struct _ENABLE_YUV_PARAMETERS 2177{ 2178 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 2179 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 2180 UCHAR ucPadding[2]; 2181}ENABLE_YUV_PARAMETERS; 2182#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 2183 2184/****************************************************************************/ 2185// Structures used by GetMemoryClockTable 2186/****************************************************************************/ 2187typedef struct _GET_MEMORY_CLOCK_PARAMETERS 2188{ 2189 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 2190} GET_MEMORY_CLOCK_PARAMETERS; 2191#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 2192 2193/****************************************************************************/ 2194// Structures used by GetEngineClockTable 2195/****************************************************************************/ 2196typedef struct _GET_ENGINE_CLOCK_PARAMETERS 2197{ 2198 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 2199} GET_ENGINE_CLOCK_PARAMETERS; 2200#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 2201 2202/****************************************************************************/ 2203// Following Structures and constant may be obsolete 2204/****************************************************************************/ 2205//Maxium 8 bytes,the data read in will be placed in the parameter space. 2206//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 2207typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 2208{ 2209 USHORT usPrescale; //Ratio between Engine clock and I2C clock 2210 USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID 2211 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 2212 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 2213 UCHAR ucSlaveAddr; //Read from which slave 2214 UCHAR ucLineNumber; //Read from which HW assisted line 2215}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 2216#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 2217 2218 2219#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 2220#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 2221#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 2222#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 2223#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 2224 2225typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2226{ 2227 USHORT usPrescale; //Ratio between Engine clock and I2C clock 2228 USHORT usByteOffset; //Write to which byte 2229 //Upper portion of usByteOffset is Format of data 2230 //1bytePS+offsetPS 2231 //2bytesPS+offsetPS 2232 //blockID+offsetPS 2233 //blockID+offsetID 2234 //blockID+counterID+offsetID 2235 UCHAR ucData; //PS data1 2236 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 2237 UCHAR ucSlaveAddr; //Write to which slave 2238 UCHAR ucLineNumber; //Write from which HW assisted line 2239}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 2240 2241#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2242 2243typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 2244{ 2245 USHORT usPrescale; //Ratio between Engine clock and I2C clock 2246 UCHAR ucSlaveAddr; //Write to which slave 2247 UCHAR ucLineNumber; //Write from which HW assisted line 2248}SET_UP_HW_I2C_DATA_PARAMETERS; 2249 2250/**************************************************************************/ 2251#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2252 2253 2254/****************************************************************************/ 2255// Structures used by PowerConnectorDetectionTable 2256/****************************************************************************/ 2257typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 2258{ 2259 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 2260 UCHAR ucPwrBehaviorId; 2261 USHORT usPwrBudget; //how much power currently boot to in unit of watt 2262}POWER_CONNECTOR_DETECTION_PARAMETERS; 2263 2264typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 2265{ 2266 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 2267 UCHAR ucReserved; 2268 USHORT usPwrBudget; //how much power currently boot to in unit of watt 2269 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2270}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 2271 2272 2273/****************************LVDS SS Command Table Definitions**********************/ 2274 2275/****************************************************************************/ 2276// Structures used by EnableSpreadSpectrumOnPPLLTable 2277/****************************************************************************/ 2278typedef struct _ENABLE_LVDS_SS_PARAMETERS 2279{ 2280 USHORT usSpreadSpectrumPercentage; 2281 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2282 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 2283 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 2284 UCHAR ucPadding[3]; 2285}ENABLE_LVDS_SS_PARAMETERS; 2286 2287//ucTableFormatRevision=1,ucTableContentRevision=2 2288typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 2289{ 2290 USHORT usSpreadSpectrumPercentage; 2291 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2292 UCHAR ucSpreadSpectrumStep; // 2293 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 2294 UCHAR ucSpreadSpectrumDelay; 2295 UCHAR ucSpreadSpectrumRange; 2296 UCHAR ucPadding; 2297}ENABLE_LVDS_SS_PARAMETERS_V2; 2298 2299//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 2300typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 2301{ 2302 USHORT usSpreadSpectrumPercentage; 2303 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2304 UCHAR ucSpreadSpectrumStep; // 2305 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2306 UCHAR ucSpreadSpectrumDelay; 2307 UCHAR ucSpreadSpectrumRange; 2308 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 2309}ENABLE_SPREAD_SPECTRUM_ON_PPLL; 2310 2311 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 2312{ 2313 USHORT usSpreadSpectrumPercentage; 2314 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2315 // Bit[1]: 1-Ext. 0-Int. 2316 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2317 // Bits[7:4] reserved 2318 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2319 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2320 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2321}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 2322 2323#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 2324#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 2325#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 2326#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 2327#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 2328#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 2329#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 2330#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 2331#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 2332#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 2333#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 2334 2335// Used by DCE5.0 2336 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 2337{ 2338 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 2339 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2340 // Bit[1]: 1-Ext. 0-Int. 2341 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2342 // Bits[7:4] reserved 2343 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2344 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2345 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2346}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 2347 2348 2349#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 2350#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 2351#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 2352#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 2353#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 2354#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 2355#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 2356#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 2357#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 2358#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 2359#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 2360#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 2361 2362#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 2363 2364typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 2365{ 2366 PIXEL_CLOCK_PARAMETERS sPCLKInput; 2367 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 2368}SET_PIXEL_CLOCK_PS_ALLOCATION; 2369 2370 2371 2372#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 2373 2374/****************************************************************************/ 2375// Structures used by ### 2376/****************************************************************************/ 2377typedef struct _MEMORY_TRAINING_PARAMETERS 2378{ 2379 ULONG ulTargetMemoryClock; //In 10Khz unit 2380}MEMORY_TRAINING_PARAMETERS; 2381#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 2382 2383 2384typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2 2385{ 2386 USHORT usMemTrainingMode; 2387 USHORT usReserved; 2388}MEMORY_TRAINING_PARAMETERS_V1_2; 2389 2390//usMemTrainingMode 2391#define NORMAL_MEMORY_TRAINING_MODE 0 2392#define ENTER_DRAM_SELFREFRESH_MODE 1 2393#define EXIT_DRAM_SELFRESH_MODE 2 2394 2395/****************************LVDS and other encoder command table definitions **********************/ 2396 2397 2398/****************************************************************************/ 2399// Structures used by LVDSEncoderControlTable (Before DEC30) 2400// LVTMAEncoderControlTable (Before DEC30) 2401// TMDSAEncoderControlTable (Before DEC30) 2402/****************************************************************************/ 2403typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 2404{ 2405 USHORT usPixelClock; // in 10KHz; for bios convenient 2406 UCHAR ucMisc; // bit0=0: Enable single link 2407 // =1: Enable dual link 2408 // Bit1=0: 666RGB 2409 // =1: 888RGB 2410 UCHAR ucAction; // 0: turn off encoder 2411 // 1: setup and turn on encoder 2412}LVDS_ENCODER_CONTROL_PARAMETERS; 2413 2414#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 2415 2416#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 2417#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2418 2419#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2420#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2421 2422//ucTableFormatRevision=1,ucTableContentRevision=2 2423typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2424{ 2425 USHORT usPixelClock; // in 10KHz; for bios convenient 2426 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2427 UCHAR ucAction; // 0: turn off encoder 2428 // 1: setup and turn on encoder 2429 UCHAR ucTruncate; // bit0=0: Disable truncate 2430 // =1: Enable truncate 2431 // bit4=0: 666RGB 2432 // =1: 888RGB 2433 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2434 // =1: Enable spatial dithering 2435 // bit4=0: 666RGB 2436 // =1: 888RGB 2437 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2438 // =1: Enable temporal dithering 2439 // bit4=0: 666RGB 2440 // =1: 888RGB 2441 // bit5=0: Gray level 2 2442 // =1: Gray level 4 2443 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2444 // =1: 25FRC_SEL pattern F 2445 // bit6:5=0: 50FRC_SEL pattern A 2446 // =1: 50FRC_SEL pattern B 2447 // =2: 50FRC_SEL pattern C 2448 // =3: 50FRC_SEL pattern D 2449 // bit7=0: 75FRC_SEL pattern E 2450 // =1: 75FRC_SEL pattern F 2451}LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2452 2453#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2454 2455#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2456#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2457 2458#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2459#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2460 2461 2462#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2463#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2464 2465#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2466#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2467 2468#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2469#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2470 2471/****************************************************************************/ 2472// Structures used by ### 2473/****************************************************************************/ 2474typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2475{ 2476 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2477 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2478 UCHAR ucPadding[2]; 2479}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2480 2481typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2482{ 2483 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2484 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2485}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2486 2487#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2488typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2489{ 2490 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2491 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2492}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2493 2494typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2495{ 2496 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2497 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2498}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2499 2500/****************************************************************************/ 2501// Structures used by DVOEncoderControlTable 2502/****************************************************************************/ 2503//ucTableFormatRevision=1,ucTableContentRevision=3 2504//ucDVOConfig: 2505#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2506#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2507#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2508#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2509#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2510#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2511#define DVO_ENCODER_CONFIG_24BIT 0x08 2512 2513typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2514{ 2515 USHORT usPixelClock; 2516 UCHAR ucDVOConfig; 2517 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2518 UCHAR ucReseved[4]; 2519}DVO_ENCODER_CONTROL_PARAMETERS_V3; 2520#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2521 2522typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2523{ 2524 USHORT usPixelClock; 2525 UCHAR ucDVOConfig; 2526 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2527 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR 2528 UCHAR ucReseved[3]; 2529}DVO_ENCODER_CONTROL_PARAMETERS_V1_4; 2530#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2531 2532 2533//ucTableFormatRevision=1 2534//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2535// bit1=0: non-coherent mode 2536// =1: coherent mode 2537 2538//========================================================================================== 2539//Only change is here next time when changing encoder parameter definitions again! 2540#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2541#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2542 2543#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2544#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2545 2546#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2547#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2548 2549#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2550#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2551 2552//========================================================================================== 2553#define PANEL_ENCODER_MISC_DUAL 0x01 2554#define PANEL_ENCODER_MISC_COHERENT 0x02 2555#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2556#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2557 2558#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2559#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2560#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2561 2562#define PANEL_ENCODER_TRUNCATE_EN 0x01 2563#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2564#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2565#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2566#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2567#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2568#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2569#define PANEL_ENCODER_25FRC_MASK 0x10 2570#define PANEL_ENCODER_25FRC_E 0x00 2571#define PANEL_ENCODER_25FRC_F 0x10 2572#define PANEL_ENCODER_50FRC_MASK 0x60 2573#define PANEL_ENCODER_50FRC_A 0x00 2574#define PANEL_ENCODER_50FRC_B 0x20 2575#define PANEL_ENCODER_50FRC_C 0x40 2576#define PANEL_ENCODER_50FRC_D 0x60 2577#define PANEL_ENCODER_75FRC_MASK 0x80 2578#define PANEL_ENCODER_75FRC_E 0x00 2579#define PANEL_ENCODER_75FRC_F 0x80 2580 2581/****************************************************************************/ 2582// Structures used by SetVoltageTable 2583/****************************************************************************/ 2584#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2585#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2586#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2587#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2588#define SET_VOLTAGE_INIT_MODE 5 2589#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2590 2591#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2592#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2593#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2594 2595#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2596#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2597#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2598 2599typedef struct _SET_VOLTAGE_PARAMETERS 2600{ 2601 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2602 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2603 UCHAR ucVoltageIndex; // An index to tell which voltage level 2604 UCHAR ucReserved; 2605}SET_VOLTAGE_PARAMETERS; 2606 2607typedef struct _SET_VOLTAGE_PARAMETERS_V2 2608{ 2609 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2610 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2611 USHORT usVoltageLevel; // real voltage level 2612}SET_VOLTAGE_PARAMETERS_V2; 2613 2614// used by both SetVoltageTable v1.3 and v1.4 2615typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2616{ 2617 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2618 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2619 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2620}SET_VOLTAGE_PARAMETERS_V1_3; 2621 2622//ucVoltageType 2623#define VOLTAGE_TYPE_VDDC 1 2624#define VOLTAGE_TYPE_MVDDC 2 2625#define VOLTAGE_TYPE_MVDDQ 3 2626#define VOLTAGE_TYPE_VDDCI 4 2627#define VOLTAGE_TYPE_VDDGFX 5 2628#define VOLTAGE_TYPE_PCC 6 2629#define VOLTAGE_TYPE_MVPP 7 2630#define VOLTAGE_TYPE_LEDDPM 8 2631#define VOLTAGE_TYPE_PCC_MVDD 9 2632#define VOLTAGE_TYPE_PCIE_VDDC 10 2633#define VOLTAGE_TYPE_PCIE_VDDR 11 2634 2635#define VOLTAGE_TYPE_GENERIC_I2C_1 0x11 2636#define VOLTAGE_TYPE_GENERIC_I2C_2 0x12 2637#define VOLTAGE_TYPE_GENERIC_I2C_3 0x13 2638#define VOLTAGE_TYPE_GENERIC_I2C_4 0x14 2639#define VOLTAGE_TYPE_GENERIC_I2C_5 0x15 2640#define VOLTAGE_TYPE_GENERIC_I2C_6 0x16 2641#define VOLTAGE_TYPE_GENERIC_I2C_7 0x17 2642#define VOLTAGE_TYPE_GENERIC_I2C_8 0x18 2643#define VOLTAGE_TYPE_GENERIC_I2C_9 0x19 2644#define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A 2645 2646//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2647#define ATOM_SET_VOLTAGE 0 //Set voltage Level 2648#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2649#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator 2650#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 2651#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 2652#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 2653 2654// define vitual voltage id in usVoltageLevel 2655#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2656#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2657#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2658#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2659#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 2660#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 2661#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 2662#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 2663 2664typedef struct _SET_VOLTAGE_PS_ALLOCATION 2665{ 2666 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2667 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2668}SET_VOLTAGE_PS_ALLOCATION; 2669 2670// New Added from SI for GetVoltageInfoTable, input parameter structure 2671typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2672{ 2673 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2674 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2675 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2676 ULONG ulReserved; 2677}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2678 2679// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2680typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2681{ 2682 ULONG ulVotlageGpioState; 2683 ULONG ulVoltageGPioMask; 2684}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2685 2686// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2687typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2688{ 2689 USHORT usVoltageLevel; 2690 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2691 ULONG ulReseved; 2692}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2693 2694// GetVoltageInfo v1.1 ucVoltageMode 2695#define ATOM_GET_VOLTAGE_VID 0x00 2696#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2697#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2698#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info 2699 2700// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2701#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2702// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2703#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2704 2705#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2706#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2707 2708 2709// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2710typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 2711{ 2712 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2713 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2714 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2715 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2716}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; 2717 2718// New in GetVoltageInfo v1.2 ucVoltageMode 2719#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 2720 2721// New Added from CI Hawaii for EVV feature 2722typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 2723{ 2724 USHORT usVoltageLevel; // real voltage level in unit of mv 2725 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2726 USHORT usTDP_Current; // TDP_Current in unit of 0.01A 2727 USHORT usTDP_Power; // TDP_Current in unit of 0.1W 2728}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; 2729 2730 2731// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2732typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 2733{ 2734 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2735 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2736 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2737 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2738 ULONG ulReserved[3]; 2739}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3; 2740 2741// New Added from CI Hawaii for EVV feature 2742typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 2743{ 2744 ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv 2745 ULONG ulReserved[4]; 2746}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3; 2747 2748 2749/****************************************************************************/ 2750// Structures used by GetSMUClockInfo 2751/****************************************************************************/ 2752typedef struct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1 2753{ 2754 ULONG ulDfsPllOutputFreq:24; 2755 ULONG ucDfsDivider:8; 2756}GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1; 2757 2758typedef struct _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1 2759{ 2760 ULONG ulDfsOutputFreq; 2761}GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1; 2762 2763/****************************************************************************/ 2764// Structures used by TVEncoderControlTable 2765/****************************************************************************/ 2766typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2767{ 2768 USHORT usPixelClock; // in 10KHz; for bios convenient 2769 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2770 UCHAR ucAction; // 0: turn off encoder 2771 // 1: setup and turn on encoder 2772}TV_ENCODER_CONTROL_PARAMETERS; 2773 2774typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2775{ 2776 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2777 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2778}TV_ENCODER_CONTROL_PS_ALLOCATION; 2779 2780//==============================Data Table Portion==================================== 2781 2782 2783/****************************************************************************/ 2784// Structure used in Data.mtb 2785/****************************************************************************/ 2786typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2787{ 2788 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2789 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2790 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2791 USHORT StandardVESA_Timing; // Only used by Bios 2792 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2793 USHORT PaletteData; // Only used by BIOS 2794 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2795 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2796 USHORT SMU_Info; // Shared by various SW components,latest version 1.1 2797 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2798 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2799 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2800 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2801 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2802 USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600 2803 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2804 USHORT GPUVirtualizationInfo; // Will be obsolete from R600 2805 USHORT SaveRestoreInfo; // Only used by Bios 2806 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2807 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2808 USHORT XTMDS_Info; // Will be obsolete from R600 2809 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2810 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2811 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2812 USHORT MC_InitParameter; // Only used by command table 2813 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2814 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2815 USHORT TV_VideoMode; // Only used by command table 2816 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2817 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2818 USHORT IntegratedSystemInfo; // Shared by various SW components 2819 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2820 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2821 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2822 USHORT ServiceInfo; 2823}ATOM_MASTER_LIST_OF_DATA_TABLES; 2824 2825typedef struct _ATOM_MASTER_DATA_TABLE 2826{ 2827 ATOM_COMMON_TABLE_HEADER sHeader; 2828 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2829}ATOM_MASTER_DATA_TABLE; 2830 2831// For backward compatible 2832#define LVDS_Info LCD_Info 2833#define DAC_Info PaletteData 2834#define TMDS_Info DIGTransmitterInfo 2835#define CompassionateData GPUVirtualizationInfo 2836#define AnalogTV_Info SMU_Info 2837#define ComponentVideoInfo GFX_Info 2838 2839/****************************************************************************/ 2840// Structure used in MultimediaCapabilityInfoTable 2841/****************************************************************************/ 2842typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2843{ 2844 ATOM_COMMON_TABLE_HEADER sHeader; 2845 ULONG ulSignature; // HW info table signature string "$ATI" 2846 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2847 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2848 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2849 UCHAR ucHostPortInfo; // Provides host port configuration information 2850}ATOM_MULTIMEDIA_CAPABILITY_INFO; 2851 2852 2853/****************************************************************************/ 2854// Structure used in MultimediaConfigInfoTable 2855/****************************************************************************/ 2856typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2857{ 2858 ATOM_COMMON_TABLE_HEADER sHeader; 2859 ULONG ulSignature; // MM info table signature sting "$MMT" 2860 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2861 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2862 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2863 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2864 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2865 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2866 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2867 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2868 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2869 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2870 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2871 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2872}ATOM_MULTIMEDIA_CONFIG_INFO; 2873 2874 2875/****************************************************************************/ 2876// Structures used in FirmwareInfoTable 2877/****************************************************************************/ 2878 2879// usBIOSCapability Defintion: 2880// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2881// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2882// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2883// Others: Reserved 2884#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2885#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2886#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2887#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2888#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2889#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2890#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2891#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2892#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2893#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2894#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2895#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2896#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2897#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2898 2899 2900#ifndef _H2INC 2901 2902//Please don't add or expand this bitfield structure below, this one will retire soon.! 2903typedef struct _ATOM_FIRMWARE_CAPABILITY 2904{ 2905#if ATOM_BIG_ENDIAN 2906 USHORT Reserved:1; 2907 USHORT SCL2Redefined:1; 2908 USHORT PostWithoutModeSet:1; 2909 USHORT HyperMemory_Size:4; 2910 USHORT HyperMemory_Support:1; 2911 USHORT PPMode_Assigned:1; 2912 USHORT WMI_SUPPORT:1; 2913 USHORT GPUControlsBL:1; 2914 USHORT EngineClockSS_Support:1; 2915 USHORT MemoryClockSS_Support:1; 2916 USHORT ExtendedDesktopSupport:1; 2917 USHORT DualCRTC_Support:1; 2918 USHORT FirmwarePosted:1; 2919#else 2920 USHORT FirmwarePosted:1; 2921 USHORT DualCRTC_Support:1; 2922 USHORT ExtendedDesktopSupport:1; 2923 USHORT MemoryClockSS_Support:1; 2924 USHORT EngineClockSS_Support:1; 2925 USHORT GPUControlsBL:1; 2926 USHORT WMI_SUPPORT:1; 2927 USHORT PPMode_Assigned:1; 2928 USHORT HyperMemory_Support:1; 2929 USHORT HyperMemory_Size:4; 2930 USHORT PostWithoutModeSet:1; 2931 USHORT SCL2Redefined:1; 2932 USHORT Reserved:1; 2933#endif 2934}ATOM_FIRMWARE_CAPABILITY; 2935 2936typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2937{ 2938 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2939 USHORT susAccess; 2940}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2941 2942#else 2943 2944typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2945{ 2946 USHORT susAccess; 2947}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2948 2949#endif 2950 2951typedef struct _ATOM_FIRMWARE_INFO 2952{ 2953 ATOM_COMMON_TABLE_HEADER sHeader; 2954 ULONG ulFirmwareRevision; 2955 ULONG ulDefaultEngineClock; //In 10Khz unit 2956 ULONG ulDefaultMemoryClock; //In 10Khz unit 2957 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2958 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2959 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2960 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2961 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2962 ULONG ulASICMaxEngineClock; //In 10Khz unit 2963 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2964 UCHAR ucASICMaxTemperature; 2965 UCHAR ucPadding[3]; //Don't use them 2966 ULONG aulReservedForBIOS[3]; //Don't use them 2967 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2968 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2969 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2970 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2971 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2972 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2973 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2974 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2975 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2976 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2977 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2978 USHORT usReferenceClock; //In 10Khz unit 2979 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2980 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2981 UCHAR ucDesign_ID; //Indicate what is the board design 2982 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2983}ATOM_FIRMWARE_INFO; 2984 2985typedef struct _ATOM_FIRMWARE_INFO_V1_2 2986{ 2987 ATOM_COMMON_TABLE_HEADER sHeader; 2988 ULONG ulFirmwareRevision; 2989 ULONG ulDefaultEngineClock; //In 10Khz unit 2990 ULONG ulDefaultMemoryClock; //In 10Khz unit 2991 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2992 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2993 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2994 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2995 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2996 ULONG ulASICMaxEngineClock; //In 10Khz unit 2997 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2998 UCHAR ucASICMaxTemperature; 2999 UCHAR ucMinAllowedBL_Level; 3000 UCHAR ucPadding[2]; //Don't use them 3001 ULONG aulReservedForBIOS[2]; //Don't use them 3002 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3003 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3004 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3005 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3006 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3007 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3008 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3009 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3010 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3011 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3012 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3013 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3014 USHORT usReferenceClock; //In 10Khz unit 3015 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3016 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3017 UCHAR ucDesign_ID; //Indicate what is the board design 3018 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3019}ATOM_FIRMWARE_INFO_V1_2; 3020 3021typedef struct _ATOM_FIRMWARE_INFO_V1_3 3022{ 3023 ATOM_COMMON_TABLE_HEADER sHeader; 3024 ULONG ulFirmwareRevision; 3025 ULONG ulDefaultEngineClock; //In 10Khz unit 3026 ULONG ulDefaultMemoryClock; //In 10Khz unit 3027 ULONG ulDriverTargetEngineClock; //In 10Khz unit 3028 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 3029 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3030 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3031 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3032 ULONG ulASICMaxEngineClock; //In 10Khz unit 3033 ULONG ulASICMaxMemoryClock; //In 10Khz unit 3034 UCHAR ucASICMaxTemperature; 3035 UCHAR ucMinAllowedBL_Level; 3036 UCHAR ucPadding[2]; //Don't use them 3037 ULONG aulReservedForBIOS; //Don't use them 3038 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 3039 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3040 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3041 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3042 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3043 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3044 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3045 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3046 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3047 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3048 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3049 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3050 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3051 USHORT usReferenceClock; //In 10Khz unit 3052 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3053 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3054 UCHAR ucDesign_ID; //Indicate what is the board design 3055 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3056}ATOM_FIRMWARE_INFO_V1_3; 3057 3058typedef struct _ATOM_FIRMWARE_INFO_V1_4 3059{ 3060 ATOM_COMMON_TABLE_HEADER sHeader; 3061 ULONG ulFirmwareRevision; 3062 ULONG ulDefaultEngineClock; //In 10Khz unit 3063 ULONG ulDefaultMemoryClock; //In 10Khz unit 3064 ULONG ulDriverTargetEngineClock; //In 10Khz unit 3065 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 3066 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3067 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3068 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3069 ULONG ulASICMaxEngineClock; //In 10Khz unit 3070 ULONG ulASICMaxMemoryClock; //In 10Khz unit 3071 UCHAR ucASICMaxTemperature; 3072 UCHAR ucMinAllowedBL_Level; 3073 USHORT usBootUpVDDCVoltage; //In MV unit 3074 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3075 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3076 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 3077 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3078 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3079 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3080 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3081 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3082 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3083 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3084 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3085 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3086 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3087 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3088 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3089 USHORT usReferenceClock; //In 10Khz unit 3090 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3091 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3092 UCHAR ucDesign_ID; //Indicate what is the board design 3093 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3094}ATOM_FIRMWARE_INFO_V1_4; 3095 3096//the structure below to be used from Cypress 3097typedef struct _ATOM_FIRMWARE_INFO_V2_1 3098{ 3099 ATOM_COMMON_TABLE_HEADER sHeader; 3100 ULONG ulFirmwareRevision; 3101 ULONG ulDefaultEngineClock; //In 10Khz unit 3102 ULONG ulDefaultMemoryClock; //In 10Khz unit 3103 ULONG ulReserved1; 3104 ULONG ulReserved2; 3105 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3106 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3107 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3108 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 3109 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 3110 UCHAR ucReserved1; //Was ucASICMaxTemperature; 3111 UCHAR ucMinAllowedBL_Level; 3112 USHORT usBootUpVDDCVoltage; //In MV unit 3113 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3114 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3115 ULONG ulReserved4; //Was ulAsicMaximumVoltage 3116 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3117 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3118 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3119 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3120 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3121 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3122 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3123 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3124 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3125 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3126 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3127 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3128 USHORT usCoreReferenceClock; //In 10Khz unit 3129 USHORT usMemoryReferenceClock; //In 10Khz unit 3130 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 3131 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3132 UCHAR ucReserved4[3]; 3133 3134}ATOM_FIRMWARE_INFO_V2_1; 3135 3136//the structure below to be used from NI 3137//ucTableFormatRevision=2 3138//ucTableContentRevision=2 3139 3140typedef struct _PRODUCT_BRANDING 3141{ 3142 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level 3143 UCHAR ucReserved:2; // Bit[3:2] Reserved 3144 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID 3145}PRODUCT_BRANDING; 3146 3147typedef struct _ATOM_FIRMWARE_INFO_V2_2 3148{ 3149 ATOM_COMMON_TABLE_HEADER sHeader; 3150 ULONG ulFirmwareRevision; 3151 ULONG ulDefaultEngineClock; //In 10Khz unit 3152 ULONG ulDefaultMemoryClock; //In 10Khz unit 3153 ULONG ulSPLL_OutputFreq; //In 10Khz unit 3154 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit 3155 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 3156 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 3157 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3158 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 3159 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 3160 UCHAR ucReserved3; //Was ucASICMaxTemperature; 3161 UCHAR ucMinAllowedBL_Level; 3162 USHORT usBootUpVDDCVoltage; //In MV unit 3163 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3164 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3165 ULONG ulReserved4; //Was ulAsicMaximumVoltage 3166 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3167 UCHAR ucRemoteDisplayConfig; 3168 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 3169 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 3170 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 3171 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 3172 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3173 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3174 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 3175 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3176 USHORT usCoreReferenceClock; //In 10Khz unit 3177 USHORT usMemoryReferenceClock; //In 10Khz unit 3178 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 3179 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3180 UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION] 3181 PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level. 3182 UCHAR ucReserved9; 3183 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 3184 USHORT usBootUpVDDGFXVoltage; //In unit of mv; 3185 ULONG ulReserved10[3]; // New added comparing to previous version 3186}ATOM_FIRMWARE_INFO_V2_2; 3187 3188#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 3189 3190 3191// definition of ucRemoteDisplayConfig 3192#define REMOTE_DISPLAY_DISABLE 0x00 3193#define REMOTE_DISPLAY_ENABLE 0x01 3194 3195/****************************************************************************/ 3196// Structures used in IntegratedSystemInfoTable 3197/****************************************************************************/ 3198#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 3199#define IGP_CAP_FLAG_AC_CARD 0x4 3200#define IGP_CAP_FLAG_SDVO_CARD 0x8 3201#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 3202 3203typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 3204{ 3205 ATOM_COMMON_TABLE_HEADER sHeader; 3206 ULONG ulBootUpEngineClock; //in 10kHz unit 3207 ULONG ulBootUpMemoryClock; //in 10kHz unit 3208 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 3209 ULONG ulMinSystemMemoryClock; //in 10kHz unit 3210 UCHAR ucNumberOfCyclesInPeriodHi; 3211 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 3212 USHORT usReserved1; 3213 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 3214 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 3215 ULONG ulReserved[2]; 3216 3217 USHORT usFSBClock; //In MHz unit 3218 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 3219 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 3220 //Bit[4]==1: P/2 mode, ==0: P/1 mode 3221 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 3222 USHORT usK8MemoryClock; //in MHz unit 3223 USHORT usK8SyncStartDelay; //in 0.01 us unit 3224 USHORT usK8DataReturnTime; //in 0.01 us unit 3225 UCHAR ucMaxNBVoltage; 3226 UCHAR ucMinNBVoltage; 3227 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 3228 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 3229 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 3230 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 3231 UCHAR ucMaxNBVoltageHigh; 3232 UCHAR ucMinNBVoltageHigh; 3233}ATOM_INTEGRATED_SYSTEM_INFO; 3234 3235/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 3236ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 3237 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 3238ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 3239 For AMD IGP,for now this can be 0 3240ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 3241 For AMD IGP,for now this can be 0 3242 3243usFSBClock: For Intel IGP,it's FSB Freq 3244 For AMD IGP,it's HT Link Speed 3245 3246usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 3247usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 3248usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 3249 3250VC:Voltage Control 3251ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 3252ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 3253 3254ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 3255ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 3256 3257ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 3258ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 3259 3260 3261usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 3262usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 3263*/ 3264 3265 3266/* 3267The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 3268Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 3269The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 3270 3271SW components can access the IGP system infor structure in the same way as before 3272*/ 3273 3274 3275typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 3276{ 3277 ATOM_COMMON_TABLE_HEADER sHeader; 3278 ULONG ulBootUpEngineClock; //in 10kHz unit 3279 ULONG ulReserved1[2]; //must be 0x0 for the reserved 3280 ULONG ulBootUpUMAClock; //in 10kHz unit 3281 ULONG ulBootUpSidePortClock; //in 10kHz unit 3282 ULONG ulMinSidePortClock; //in 10kHz unit 3283 ULONG ulReserved2[6]; //must be 0x0 for the reserved 3284 ULONG ulSystemConfig; //see explanation below 3285 ULONG ulBootUpReqDisplayVector; 3286 ULONG ulOtherDisplayMisc; 3287 ULONG ulDDISlot1Config; 3288 ULONG ulDDISlot2Config; 3289 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3290 UCHAR ucUMAChannelNumber; 3291 UCHAR ucDockingPinBit; 3292 UCHAR ucDockingPinPolarity; 3293 ULONG ulDockingPinCFGInfo; 3294 ULONG ulCPUCapInfo; 3295 USHORT usNumberOfCyclesInPeriod; 3296 USHORT usMaxNBVoltage; 3297 USHORT usMinNBVoltage; 3298 USHORT usBootUpNBVoltage; 3299 ULONG ulHTLinkFreq; //in 10Khz 3300 USHORT usMinHTLinkWidth; 3301 USHORT usMaxHTLinkWidth; 3302 USHORT usUMASyncStartDelay; 3303 USHORT usUMADataReturnTime; 3304 USHORT usLinkStatusZeroTime; 3305 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 3306 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 3307 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 3308 USHORT usMaxUpStreamHTLinkWidth; 3309 USHORT usMaxDownStreamHTLinkWidth; 3310 USHORT usMinUpStreamHTLinkWidth; 3311 USHORT usMinDownStreamHTLinkWidth; 3312 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 3313 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 3314 ULONG ulReserved3[96]; //must be 0x0 3315}ATOM_INTEGRATED_SYSTEM_INFO_V2; 3316 3317/* 3318ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 3319ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 3320ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 3321 3322ulSystemConfig: 3323Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 3324Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 3325 =0: system boots up at driver control state. Power state depends on PowerPlay table. 3326Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 3327Bit[3]=1: Only one power state(Performance) will be supported. 3328 =0: Multiple power states supported from PowerPlay table. 3329Bit[4]=1: CLMC is supported and enabled on current system. 3330 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 3331Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 3332 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 3333Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 3334 =0: Voltage settings is determined by powerplay table. 3335Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 3336 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 3337Bit[8]=1: CDLF is supported and enabled on current system. 3338 =0: CDLF is not supported or enabled on current system. 3339Bit[9]=1: DLL Shut Down feature is enabled on current system. 3340 =0: DLL Shut Down feature is not enabled or supported on current system. 3341 3342ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 3343 3344ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 3345 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; 3346 3347ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 3348 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 3349 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 3350 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 3351 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 3352 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 3353 3354 [15:8] - Lane configuration attribute; 3355 [23:16]- Connector type, possible value: 3356 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 3357 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 3358 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 3359 CONNECTOR_OBJECT_ID_DISPLAYPORT 3360 CONNECTOR_OBJECT_ID_eDP 3361 [31:24]- Reserved 3362 3363ulDDISlot2Config: Same as Slot1. 3364ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 3365For IGP, Hypermemory is the only memory type showed in CCC. 3366 3367ucUMAChannelNumber: how many channels for the UMA; 3368 3369ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 3370ucDockingPinBit: which bit in this register to read the pin status; 3371ucDockingPinPolarity:Polarity of the pin when docked; 3372 3373ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 3374 3375usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 3376 3377usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 3378usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 3379 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 3380 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 3381 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 3382 3383usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 3384 3385 3386ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 3387usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 3388 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3389usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 3390 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3391 3392usUMASyncStartDelay: Memory access latency, required for watermark calculation 3393usUMADataReturnTime: Memory access latency, required for watermark calculation 3394usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 3395for Griffin or Greyhound. SBIOS needs to convert to actual time by: 3396 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 3397 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 3398 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 3399 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 3400 3401ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 3402 This must be less than or equal to ulHTLinkFreq(bootup frequency). 3403ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 3404 This must be less than or equal to ulHighVoltageHTLinkFreq. 3405 3406usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 3407usMaxDownStreamHTLinkWidth: same as above. 3408usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 3409usMinDownStreamHTLinkWidth: same as above. 3410*/ 3411 3412// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 3413#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 3414#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 3415#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 3416#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 3417#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 3418#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 3419 3420#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 3421 3422#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 3423#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 3424#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 3425#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 3426#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 3427#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 3428#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 3429#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 3430#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 3431#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 3432 3433#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 3434 3435#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 3436#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 3437#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 3438#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 3439#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 3440#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 3441 3442#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 3443#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 3444#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 3445 3446#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 3447 3448// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 3449typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 3450{ 3451 ATOM_COMMON_TABLE_HEADER sHeader; 3452 ULONG ulBootUpEngineClock; //in 10kHz unit 3453 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 3454 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 3455 ULONG ulBootUpUMAClock; //in 10kHz unit 3456 ULONG ulReserved1[8]; //must be 0x0 for the reserved 3457 ULONG ulBootUpReqDisplayVector; 3458 ULONG ulOtherDisplayMisc; 3459 ULONG ulReserved2[4]; //must be 0x0 for the reserved 3460 ULONG ulSystemConfig; //TBD 3461 ULONG ulCPUCapInfo; //TBD 3462 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3463 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3464 USHORT usBootUpNBVoltage; //boot up NB voltage 3465 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 3466 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 3467 ULONG ulReserved3[4]; //must be 0x0 for the reserved 3468 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 3469 ULONG ulDDISlot2Config; 3470 ULONG ulDDISlot3Config; 3471 ULONG ulDDISlot4Config; 3472 ULONG ulReserved4[4]; //must be 0x0 for the reserved 3473 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3474 UCHAR ucUMAChannelNumber; 3475 USHORT usReserved; 3476 ULONG ulReserved5[4]; //must be 0x0 for the reserved 3477 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 3478 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 3479 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 3480 ULONG ulReserved6[61]; //must be 0x0 3481}ATOM_INTEGRATED_SYSTEM_INFO_V5; 3482 3483 3484 3485/****************************************************************************/ 3486// Structure used in GPUVirtualizationInfoTable 3487/****************************************************************************/ 3488typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1 3489{ 3490 ATOM_COMMON_TABLE_HEADER sHeader; 3491 ULONG ulMCUcodeRomStartAddr; 3492 ULONG ulMCUcodeLength; 3493 ULONG ulSMCUcodeRomStartAddr; 3494 ULONG ulSMCUcodeLength; 3495 ULONG ulRLCVUcodeRomStartAddr; 3496 ULONG ulRLCVUcodeLength; 3497 ULONG ulTOCUcodeStartAddr; 3498 ULONG ulTOCUcodeLength; 3499 ULONG ulSMCPatchTableStartAddr; 3500 ULONG ulSmcPatchTableLength; 3501 ULONG ulSystemFlag; 3502}ATOM_GPU_VIRTUALIZATION_INFO_V2_1; 3503 3504 3505#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 3506#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 3507#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 3508#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 3509#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 3510#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 3511#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 3512#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 3513#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 3514#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 3515#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 3516#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 3517#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 3518#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 3519 3520// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 3521#define ASIC_INT_DAC1_ENCODER_ID 0x00 3522#define ASIC_INT_TV_ENCODER_ID 0x02 3523#define ASIC_INT_DIG1_ENCODER_ID 0x03 3524#define ASIC_INT_DAC2_ENCODER_ID 0x04 3525#define ASIC_EXT_TV_ENCODER_ID 0x06 3526#define ASIC_INT_DVO_ENCODER_ID 0x07 3527#define ASIC_INT_DIG2_ENCODER_ID 0x09 3528#define ASIC_EXT_DIG_ENCODER_ID 0x05 3529#define ASIC_EXT_DIG2_ENCODER_ID 0x08 3530#define ASIC_INT_DIG3_ENCODER_ID 0x0a 3531#define ASIC_INT_DIG4_ENCODER_ID 0x0b 3532#define ASIC_INT_DIG5_ENCODER_ID 0x0c 3533#define ASIC_INT_DIG6_ENCODER_ID 0x0d 3534#define ASIC_INT_DIG7_ENCODER_ID 0x0e 3535 3536//define Encoder attribute 3537#define ATOM_ANALOG_ENCODER 0 3538#define ATOM_DIGITAL_ENCODER 1 3539#define ATOM_DP_ENCODER 2 3540 3541#define ATOM_ENCODER_ENUM_MASK 0x70 3542#define ATOM_ENCODER_ENUM_ID1 0x00 3543#define ATOM_ENCODER_ENUM_ID2 0x10 3544#define ATOM_ENCODER_ENUM_ID3 0x20 3545#define ATOM_ENCODER_ENUM_ID4 0x30 3546#define ATOM_ENCODER_ENUM_ID5 0x40 3547#define ATOM_ENCODER_ENUM_ID6 0x50 3548 3549#define ATOM_DEVICE_CRT1_INDEX 0x00000000 3550#define ATOM_DEVICE_LCD1_INDEX 0x00000001 3551#define ATOM_DEVICE_TV1_INDEX 0x00000002 3552#define ATOM_DEVICE_DFP1_INDEX 0x00000003 3553#define ATOM_DEVICE_CRT2_INDEX 0x00000004 3554#define ATOM_DEVICE_LCD2_INDEX 0x00000005 3555#define ATOM_DEVICE_DFP6_INDEX 0x00000006 3556#define ATOM_DEVICE_DFP2_INDEX 0x00000007 3557#define ATOM_DEVICE_CV_INDEX 0x00000008 3558#define ATOM_DEVICE_DFP3_INDEX 0x00000009 3559#define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3560#define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3561 3562#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3563#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3564#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3565#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3566#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3567#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3568#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3569 3570#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3571 3572#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3573#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3574#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3575#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3576#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3577#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3578#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3579#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3580#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3581#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3582#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3583#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3584 3585 3586#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3587#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3588#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT 3589#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3590 3591#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3592#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3593#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3594#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3595#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3596#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3597#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3598#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3599#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3600#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3601#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3602#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3603#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3604#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3605#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3606 3607 3608#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3609#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3610#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3611#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3612#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3613#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3614 3615#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3616 3617#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3618#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3619 3620#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3621#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3622#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3623#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3624#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3625#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3626 3627#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3628#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3629#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3630#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3631 3632// usDeviceSupport: 3633// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3634// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3635// Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3636// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3637// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3638// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3639// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3640// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3641// Bit 8 = 0 - no CV support= 1- CV is supported 3642// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3643// Bit 10= 0 - no DFP4 support= 1- DFP4 is supported 3644// Bit 11= 0 - no DFP5 support= 1- DFP5 is supported 3645// 3646// 3647 3648/****************************************************************************/ 3649// Structure used in MclkSS_InfoTable 3650/****************************************************************************/ 3651// ucI2C_ConfigID 3652// [7:0] - I2C LINE Associate ID 3653// = 0 - no I2C 3654// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3655// = 0, [6:0]=SW assisted I2C ID 3656// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3657// = 2, HW engine for Multimedia use 3658// = 3-7 Reserved for future I2C engines 3659// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3660 3661typedef struct _ATOM_I2C_ID_CONFIG 3662{ 3663#if ATOM_BIG_ENDIAN 3664 UCHAR bfHW_Capable:1; 3665 UCHAR bfHW_EngineID:3; 3666 UCHAR bfI2C_LineMux:4; 3667#else 3668 UCHAR bfI2C_LineMux:4; 3669 UCHAR bfHW_EngineID:3; 3670 UCHAR bfHW_Capable:1; 3671#endif 3672}ATOM_I2C_ID_CONFIG; 3673 3674typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3675{ 3676 ATOM_I2C_ID_CONFIG sbfAccess; 3677 UCHAR ucAccess; 3678}ATOM_I2C_ID_CONFIG_ACCESS; 3679 3680 3681/****************************************************************************/ 3682// Structure used in GPIO_I2C_InfoTable 3683/****************************************************************************/ 3684typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3685{ 3686 USHORT usClkMaskRegisterIndex; 3687 USHORT usClkEnRegisterIndex; 3688 USHORT usClkY_RegisterIndex; 3689 USHORT usClkA_RegisterIndex; 3690 USHORT usDataMaskRegisterIndex; 3691 USHORT usDataEnRegisterIndex; 3692 USHORT usDataY_RegisterIndex; 3693 USHORT usDataA_RegisterIndex; 3694 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3695 UCHAR ucClkMaskShift; 3696 UCHAR ucClkEnShift; 3697 UCHAR ucClkY_Shift; 3698 UCHAR ucClkA_Shift; 3699 UCHAR ucDataMaskShift; 3700 UCHAR ucDataEnShift; 3701 UCHAR ucDataY_Shift; 3702 UCHAR ucDataA_Shift; 3703 UCHAR ucReserved1; 3704 UCHAR ucReserved2; 3705}ATOM_GPIO_I2C_ASSIGMENT; 3706 3707typedef struct _ATOM_GPIO_I2C_INFO 3708{ 3709 ATOM_COMMON_TABLE_HEADER sHeader; 3710 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3711}ATOM_GPIO_I2C_INFO; 3712 3713/****************************************************************************/ 3714// Common Structure used in other structures 3715/****************************************************************************/ 3716 3717#ifndef _H2INC 3718 3719//Please don't add or expand this bitfield structure below, this one will retire soon.! 3720typedef struct _ATOM_MODE_MISC_INFO 3721{ 3722#if ATOM_BIG_ENDIAN 3723 USHORT Reserved:6; 3724 USHORT RGB888:1; 3725 USHORT DoubleClock:1; 3726 USHORT Interlace:1; 3727 USHORT CompositeSync:1; 3728 USHORT V_ReplicationBy2:1; 3729 USHORT H_ReplicationBy2:1; 3730 USHORT VerticalCutOff:1; 3731 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3732 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3733 USHORT HorizontalCutOff:1; 3734#else 3735 USHORT HorizontalCutOff:1; 3736 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3737 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3738 USHORT VerticalCutOff:1; 3739 USHORT H_ReplicationBy2:1; 3740 USHORT V_ReplicationBy2:1; 3741 USHORT CompositeSync:1; 3742 USHORT Interlace:1; 3743 USHORT DoubleClock:1; 3744 USHORT RGB888:1; 3745 USHORT Reserved:6; 3746#endif 3747}ATOM_MODE_MISC_INFO; 3748 3749typedef union _ATOM_MODE_MISC_INFO_ACCESS 3750{ 3751 ATOM_MODE_MISC_INFO sbfAccess; 3752 USHORT usAccess; 3753}ATOM_MODE_MISC_INFO_ACCESS; 3754 3755#else 3756 3757typedef union _ATOM_MODE_MISC_INFO_ACCESS 3758{ 3759 USHORT usAccess; 3760}ATOM_MODE_MISC_INFO_ACCESS; 3761 3762#endif 3763 3764// usModeMiscInfo- 3765#define ATOM_H_CUTOFF 0x01 3766#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3767#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3768#define ATOM_V_CUTOFF 0x08 3769#define ATOM_H_REPLICATIONBY2 0x10 3770#define ATOM_V_REPLICATIONBY2 0x20 3771#define ATOM_COMPOSITESYNC 0x40 3772#define ATOM_INTERLACE 0x80 3773#define ATOM_DOUBLE_CLOCK_MODE 0x100 3774#define ATOM_RGB888_MODE 0x200 3775 3776//usRefreshRate- 3777#define ATOM_REFRESH_43 43 3778#define ATOM_REFRESH_47 47 3779#define ATOM_REFRESH_56 56 3780#define ATOM_REFRESH_60 60 3781#define ATOM_REFRESH_65 65 3782#define ATOM_REFRESH_70 70 3783#define ATOM_REFRESH_72 72 3784#define ATOM_REFRESH_75 75 3785#define ATOM_REFRESH_85 85 3786 3787// ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3788// Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3789// 3790// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3791// = EDID_HA + EDID_HBL 3792// VESA_HDISP = VESA_ACTIVE = EDID_HA 3793// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3794// = EDID_HA + EDID_HSO 3795// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3796// VESA_BORDER = EDID_BORDER 3797 3798 3799/****************************************************************************/ 3800// Structure used in SetCRTC_UsingDTDTimingTable 3801/****************************************************************************/ 3802typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3803{ 3804 USHORT usH_Size; 3805 USHORT usH_Blanking_Time; 3806 USHORT usV_Size; 3807 USHORT usV_Blanking_Time; 3808 USHORT usH_SyncOffset; 3809 USHORT usH_SyncWidth; 3810 USHORT usV_SyncOffset; 3811 USHORT usV_SyncWidth; 3812 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3813 UCHAR ucH_Border; // From DFP EDID 3814 UCHAR ucV_Border; 3815 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3816 UCHAR ucPadding[3]; 3817}SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3818 3819/****************************************************************************/ 3820// Structure used in SetCRTC_TimingTable 3821/****************************************************************************/ 3822typedef struct _SET_CRTC_TIMING_PARAMETERS 3823{ 3824 USHORT usH_Total; // horizontal total 3825 USHORT usH_Disp; // horizontal display 3826 USHORT usH_SyncStart; // horozontal Sync start 3827 USHORT usH_SyncWidth; // horizontal Sync width 3828 USHORT usV_Total; // vertical total 3829 USHORT usV_Disp; // vertical display 3830 USHORT usV_SyncStart; // vertical Sync start 3831 USHORT usV_SyncWidth; // vertical Sync width 3832 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3833 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3834 UCHAR ucOverscanRight; // right 3835 UCHAR ucOverscanLeft; // left 3836 UCHAR ucOverscanBottom; // bottom 3837 UCHAR ucOverscanTop; // top 3838 UCHAR ucReserved; 3839}SET_CRTC_TIMING_PARAMETERS; 3840#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3841 3842 3843/****************************************************************************/ 3844// Structure used in StandardVESA_TimingTable 3845// AnalogTV_InfoTable 3846// ComponentVideoInfoTable 3847/****************************************************************************/ 3848typedef struct _ATOM_MODE_TIMING 3849{ 3850 USHORT usCRTC_H_Total; 3851 USHORT usCRTC_H_Disp; 3852 USHORT usCRTC_H_SyncStart; 3853 USHORT usCRTC_H_SyncWidth; 3854 USHORT usCRTC_V_Total; 3855 USHORT usCRTC_V_Disp; 3856 USHORT usCRTC_V_SyncStart; 3857 USHORT usCRTC_V_SyncWidth; 3858 USHORT usPixelClock; //in 10Khz unit 3859 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3860 USHORT usCRTC_OverscanRight; 3861 USHORT usCRTC_OverscanLeft; 3862 USHORT usCRTC_OverscanBottom; 3863 USHORT usCRTC_OverscanTop; 3864 USHORT usReserve; 3865 UCHAR ucInternalModeNumber; 3866 UCHAR ucRefreshRate; 3867}ATOM_MODE_TIMING; 3868 3869typedef struct _ATOM_DTD_FORMAT 3870{ 3871 USHORT usPixClk; 3872 USHORT usHActive; 3873 USHORT usHBlanking_Time; 3874 USHORT usVActive; 3875 USHORT usVBlanking_Time; 3876 USHORT usHSyncOffset; 3877 USHORT usHSyncWidth; 3878 USHORT usVSyncOffset; 3879 USHORT usVSyncWidth; 3880 USHORT usImageHSize; 3881 USHORT usImageVSize; 3882 UCHAR ucHBorder; 3883 UCHAR ucVBorder; 3884 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3885 UCHAR ucInternalModeNumber; 3886 UCHAR ucRefreshRate; 3887}ATOM_DTD_FORMAT; 3888 3889/****************************************************************************/ 3890// Structure used in LVDS_InfoTable 3891// * Need a document to describe this table 3892/****************************************************************************/ 3893#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3894#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3895#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3896#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3897#define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040 3898 3899//ucTableFormatRevision=1 3900//ucTableContentRevision=1 3901typedef struct _ATOM_LVDS_INFO 3902{ 3903 ATOM_COMMON_TABLE_HEADER sHeader; 3904 ATOM_DTD_FORMAT sLCDTiming; 3905 USHORT usModePatchTableOffset; 3906 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3907 USHORT usOffDelayInMs; 3908 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3909 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3910 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3911 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3912 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3913 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3914 UCHAR ucPanelDefaultRefreshRate; 3915 UCHAR ucPanelIdentification; 3916 UCHAR ucSS_Id; 3917}ATOM_LVDS_INFO; 3918 3919//ucTableFormatRevision=1 3920//ucTableContentRevision=2 3921typedef struct _ATOM_LVDS_INFO_V12 3922{ 3923 ATOM_COMMON_TABLE_HEADER sHeader; 3924 ATOM_DTD_FORMAT sLCDTiming; 3925 USHORT usExtInfoTableOffset; 3926 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3927 USHORT usOffDelayInMs; 3928 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3929 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3930 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3931 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3932 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3933 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3934 UCHAR ucPanelDefaultRefreshRate; 3935 UCHAR ucPanelIdentification; 3936 UCHAR ucSS_Id; 3937 USHORT usLCDVenderID; 3938 USHORT usLCDProductID; 3939 UCHAR ucLCDPanel_SpecialHandlingCap; 3940 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3941 UCHAR ucReserved[2]; 3942}ATOM_LVDS_INFO_V12; 3943 3944//Definitions for ucLCDPanel_SpecialHandlingCap: 3945 3946//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3947//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3948#define LCDPANEL_CAP_READ_EDID 0x1 3949 3950//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3951//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3952//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3953#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3954 3955//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3956#define LCDPANEL_CAP_eDP 0x4 3957 3958 3959//Color Bit Depth definition in EDID V1.4 @BYTE 14h 3960//Bit 6 5 4 3961 // 0 0 0 - Color bit depth is undefined 3962 // 0 0 1 - 6 Bits per Primary Color 3963 // 0 1 0 - 8 Bits per Primary Color 3964 // 0 1 1 - 10 Bits per Primary Color 3965 // 1 0 0 - 12 Bits per Primary Color 3966 // 1 0 1 - 14 Bits per Primary Color 3967 // 1 1 0 - 16 Bits per Primary Color 3968 // 1 1 1 - Reserved 3969 3970#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3971 3972// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3973#define PANEL_RANDOM_DITHER 0x80 3974#define PANEL_RANDOM_DITHER_MASK 0x80 3975 3976#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3977 3978 3979typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT 3980{ 3981 UCHAR ucSupportedRefreshRate; 3982 UCHAR ucMinRefreshRateForDRR; 3983}ATOM_LCD_REFRESH_RATE_SUPPORT; 3984 3985/****************************************************************************/ 3986// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3987// ASIC Families: NI 3988// ucTableFormatRevision=1 3989// ucTableContentRevision=3 3990/****************************************************************************/ 3991typedef struct _ATOM_LCD_INFO_V13 3992{ 3993 ATOM_COMMON_TABLE_HEADER sHeader; 3994 ATOM_DTD_FORMAT sLCDTiming; 3995 USHORT usExtInfoTableOffset; 3996 union 3997 { 3998 USHORT usSupportedRefreshRate; 3999 ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport; 4000 }; 4001 ULONG ulReserved0; 4002 UCHAR ucLCD_Misc; // Reorganized in V13 4003 // Bit0: {=0:single, =1:dual}, 4004 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 4005 // Bit3:2: {Grey level} 4006 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 4007 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 4008 UCHAR ucPanelDefaultRefreshRate; 4009 UCHAR ucPanelIdentification; 4010 UCHAR ucSS_Id; 4011 USHORT usLCDVenderID; 4012 USHORT usLCDProductID; 4013 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 4014 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 4015 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 4016 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 4017 // Bit7-3: Reserved 4018 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 4019 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 4020 4021 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 4022 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 4023 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 4024 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 4025 4026 UCHAR ucOffDelay_in4Ms; 4027 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 4028 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 4029 UCHAR ucReserved1; 4030 4031 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 4032 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 4033 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 4034 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 4035 4036 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 4037 UCHAR uceDPToLVDSRxId; 4038 UCHAR ucLcdReservd; 4039 ULONG ulReserved[2]; 4040}ATOM_LCD_INFO_V13; 4041 4042#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 4043 4044//Definitions for ucLCD_Misc 4045#define ATOM_PANEL_MISC_V13_DUAL 0x00000001 4046#define ATOM_PANEL_MISC_V13_FPDI 0x00000002 4047#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 4048#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 4049#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 4050#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 4051#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 4052 4053//Color Bit Depth definition in EDID V1.4 @BYTE 14h 4054//Bit 6 5 4 4055 // 0 0 0 - Color bit depth is undefined 4056 // 0 0 1 - 6 Bits per Primary Color 4057 // 0 1 0 - 8 Bits per Primary Color 4058 // 0 1 1 - 10 Bits per Primary Color 4059 // 1 0 0 - 12 Bits per Primary Color 4060 // 1 0 1 - 14 Bits per Primary Color 4061 // 1 1 0 - 16 Bits per Primary Color 4062 // 1 1 1 - Reserved 4063 4064//Definitions for ucLCDPanel_SpecialHandlingCap: 4065 4066//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 4067//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 4068#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 4069 4070//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 4071//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 4072//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 4073#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 4074 4075//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 4076#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 4077 4078//uceDPToLVDSRxId 4079#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 4080#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 4081#define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init 4082 4083typedef struct _ATOM_PATCH_RECORD_MODE 4084{ 4085 UCHAR ucRecordType; 4086 USHORT usHDisp; 4087 USHORT usVDisp; 4088}ATOM_PATCH_RECORD_MODE; 4089 4090typedef struct _ATOM_LCD_RTS_RECORD 4091{ 4092 UCHAR ucRecordType; 4093 UCHAR ucRTSValue; 4094}ATOM_LCD_RTS_RECORD; 4095 4096//!! If the record below exits, it shoud always be the first record for easy use in command table!!! 4097// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 4098typedef struct _ATOM_LCD_MODE_CONTROL_CAP 4099{ 4100 UCHAR ucRecordType; 4101 USHORT usLCDCap; 4102}ATOM_LCD_MODE_CONTROL_CAP; 4103 4104#define LCD_MODE_CAP_BL_OFF 1 4105#define LCD_MODE_CAP_CRTC_OFF 2 4106#define LCD_MODE_CAP_PANEL_OFF 4 4107 4108 4109typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 4110{ 4111 UCHAR ucRecordType; 4112 UCHAR ucFakeEDIDLength; // = 128 means EDID length is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128 4113 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 4114} ATOM_FAKE_EDID_PATCH_RECORD; 4115 4116typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 4117{ 4118 UCHAR ucRecordType; 4119 USHORT usHSize; 4120 USHORT usVSize; 4121}ATOM_PANEL_RESOLUTION_PATCH_RECORD; 4122 4123#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 4124#define LCD_RTS_RECORD_TYPE 2 4125#define LCD_CAP_RECORD_TYPE 3 4126#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 4127#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 4128#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 4129#define ATOM_RECORD_END_TYPE 0xFF 4130 4131/****************************Spread Spectrum Info Table Definitions **********************/ 4132 4133//ucTableFormatRevision=1 4134//ucTableContentRevision=2 4135typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 4136{ 4137 USHORT usSpreadSpectrumPercentage; 4138 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 4139 UCHAR ucSS_Step; 4140 UCHAR ucSS_Delay; 4141 UCHAR ucSS_Id; 4142 UCHAR ucRecommendedRef_Div; 4143 UCHAR ucSS_Range; //it was reserved for V11 4144}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 4145 4146#define ATOM_MAX_SS_ENTRY 16 4147#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 4148#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 4149#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 4150#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 4151 4152 4153 4154#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 4155#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 4156#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 4157#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 4158#define ATOM_INTERNAL_SS_MASK 0x00000000 4159#define ATOM_EXTERNAL_SS_MASK 0x00000002 4160#define EXEC_SS_STEP_SIZE_SHIFT 2 4161#define EXEC_SS_DELAY_SHIFT 4 4162#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 4163 4164typedef struct _ATOM_SPREAD_SPECTRUM_INFO 4165{ 4166 ATOM_COMMON_TABLE_HEADER sHeader; 4167 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 4168}ATOM_SPREAD_SPECTRUM_INFO; 4169 4170 4171/****************************************************************************/ 4172// Structure used in AnalogTV_InfoTable (Top level) 4173/****************************************************************************/ 4174//ucTVBootUpDefaultStd definiton: 4175 4176//ATOM_TV_NTSC 1 4177//ATOM_TV_NTSCJ 2 4178//ATOM_TV_PAL 3 4179//ATOM_TV_PALM 4 4180//ATOM_TV_PALCN 5 4181//ATOM_TV_PALN 6 4182//ATOM_TV_PAL60 7 4183//ATOM_TV_SECAM 8 4184 4185//ucTVSuppportedStd definition: 4186#define NTSC_SUPPORT 0x1 4187#define NTSCJ_SUPPORT 0x2 4188 4189#define PAL_SUPPORT 0x4 4190#define PALM_SUPPORT 0x8 4191#define PALCN_SUPPORT 0x10 4192#define PALN_SUPPORT 0x20 4193#define PAL60_SUPPORT 0x40 4194#define SECAM_SUPPORT 0x80 4195 4196#define MAX_SUPPORTED_TV_TIMING 2 4197 4198typedef struct _ATOM_ANALOG_TV_INFO 4199{ 4200 ATOM_COMMON_TABLE_HEADER sHeader; 4201 UCHAR ucTV_SuppportedStandard; 4202 UCHAR ucTV_BootUpDefaultStandard; 4203 UCHAR ucExt_TV_ASIC_ID; 4204 UCHAR ucExt_TV_ASIC_SlaveAddr; 4205 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; 4206}ATOM_ANALOG_TV_INFO; 4207 4208typedef struct _ATOM_DPCD_INFO 4209{ 4210 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 4211 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 4212 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 4213 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 4214}ATOM_DPCD_INFO; 4215 4216#define ATOM_DPCD_MAX_LANE_MASK 0x1F 4217 4218/**************************************************************************/ 4219// VRAM usage and their defintions 4220 4221// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 4222// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 4223// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 4224// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 4225// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 4226 4227// Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU). 4228//#ifndef VESA_MEMORY_IN_64K_BLOCK 4229//#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 4230//#endif 4231 4232#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 4233#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 4234#define ATOM_HWICON_INFOTABLE_SIZE 32 4235#define MAX_DTD_MODE_IN_VRAM 6 4236#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 4237#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 4238//20 bytes for Encoder Type and DPCD in STD EDID area 4239#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 4240#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 4241 4242#define ATOM_HWICON1_SURFACE_ADDR 0 4243#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 4244#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 4245#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 4246#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4247#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4248 4249#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4250#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4251#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4252 4253#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4254 4255#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4256#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4257#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4258 4259#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4260#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4261#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4262 4263#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4264#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4265#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4266 4267#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4268#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4269#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4270 4271#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4272#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4273#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4274 4275#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4276#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4277#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4278 4279#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4280#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4281#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4282 4283#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4284#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4285#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4286 4287#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4288#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4289#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4290 4291#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4292 4293#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 4294#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 4295 4296//The size below is in Kb! 4297#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 4298 4299#define ATOM_VRAM_RESERVE_V2_SIZE 32 4300 4301#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 4302#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 4303#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 4304#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 4305#define ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 0x2 4306 4307/***********************************************************************************/ 4308// Structure used in VRAM_UsageByFirmwareTable 4309// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 4310// at running time. 4311// note2: From RV770, the memory is more than 32bit addressable, so we will change 4312// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 4313// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 4314// (in offset to start of memory address) is KB aligned instead of byte aligend. 4315// Note3: 4316/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged 4317constant across VGA or non VGA adapter, 4318for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 4319 4320If (ulStartAddrUsedByFirmware!=0) 4321FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 4322Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 4323else //Non VGA case 4324 if (FB_Size<=2Gb) 4325 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 4326 else 4327 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 4328 4329CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 4330 4331/***********************************************************************************/ 4332#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 4333 4334typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 4335{ 4336 ULONG ulStartAddrUsedByFirmware; 4337 USHORT usFirmwareUseInKb; 4338 USHORT usReserved; 4339}ATOM_FIRMWARE_VRAM_RESERVE_INFO; 4340 4341typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 4342{ 4343 ATOM_COMMON_TABLE_HEADER sHeader; 4344 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 4345}ATOM_VRAM_USAGE_BY_FIRMWARE; 4346 4347// change verion to 1.5, when allow driver to allocate the vram area for command table access. 4348typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 4349{ 4350 ULONG ulStartAddrUsedByFirmware; 4351 USHORT usFirmwareUseInKb; 4352 USHORT usFBUsedByDrvInKb; 4353}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 4354 4355typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 4356{ 4357 ATOM_COMMON_TABLE_HEADER sHeader; 4358 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 4359}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 4360 4361/****************************************************************************/ 4362// Structure used in GPIO_Pin_LUTTable 4363/****************************************************************************/ 4364typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 4365{ 4366 USHORT usGpioPin_AIndex; 4367 UCHAR ucGpioPinBitShift; 4368 UCHAR ucGPIO_ID; 4369}ATOM_GPIO_PIN_ASSIGNMENT; 4370 4371//ucGPIO_ID pre-define id for multiple usage 4372// GPIO use to control PCIE_VDDC in certain SLT board 4373#define PCIE_VDDC_CONTROL_GPIO_PINID 56 4374 4375//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable 4376#define PP_AC_DC_SWITCH_GPIO_PINID 60 4377//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 4378#define VDDC_VRHOT_GPIO_PINID 61 4379//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled 4380#define VDDC_PCC_GPIO_PINID 62 4381// Only used on certain SLT/PA board to allow utility to cut Efuse. 4382#define EFUSE_CUT_ENABLE_GPIO_PINID 63 4383// ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= 4384#define DRAM_SELF_REFRESH_GPIO_PINID 64 4385// Thermal interrupt output->system thermal chip GPIO pin 4386#define THERMAL_INT_OUTPUT_GPIO_PINID 65 4387 4388 4389typedef struct _ATOM_GPIO_PIN_LUT 4390{ 4391 ATOM_COMMON_TABLE_HEADER sHeader; 4392 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 4393}ATOM_GPIO_PIN_LUT; 4394 4395/****************************************************************************/ 4396// Structure used in ComponentVideoInfoTable 4397/****************************************************************************/ 4398#define GPIO_PIN_ACTIVE_HIGH 0x1 4399#define MAX_SUPPORTED_CV_STANDARDS 5 4400 4401// definitions for ATOM_D_INFO.ucSettings 4402#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 4403#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 4404#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 4405 4406typedef struct _ATOM_GPIO_INFO 4407{ 4408 USHORT usAOffset; 4409 UCHAR ucSettings; 4410 UCHAR ucReserved; 4411}ATOM_GPIO_INFO; 4412 4413// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 4414#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 4415 4416// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 4417#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 4418#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 4419 4420// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 4421//Line 3 out put 5V. 4422#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 4423#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 4424#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 4425 4426//Line 3 out put 2.2V 4427#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 4428#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 4429#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 4430 4431//Line 3 out put 0V 4432#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 4433#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 4434#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 4435 4436#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 4437 4438#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 4439 4440//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 4441#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4442#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4443 4444 4445typedef struct _ATOM_COMPONENT_VIDEO_INFO 4446{ 4447 ATOM_COMMON_TABLE_HEADER sHeader; 4448 USHORT usMask_PinRegisterIndex; 4449 USHORT usEN_PinRegisterIndex; 4450 USHORT usY_PinRegisterIndex; 4451 USHORT usA_PinRegisterIndex; 4452 UCHAR ucBitShift; 4453 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 4454 ATOM_DTD_FORMAT sReserved; // must be zeroed out 4455 UCHAR ucMiscInfo; 4456 UCHAR uc480i; 4457 UCHAR uc480p; 4458 UCHAR uc720p; 4459 UCHAR uc1080i; 4460 UCHAR ucLetterBoxMode; 4461 UCHAR ucReserved[3]; 4462 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4463 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4464 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4465}ATOM_COMPONENT_VIDEO_INFO; 4466 4467//ucTableFormatRevision=2 4468//ucTableContentRevision=1 4469typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 4470{ 4471 ATOM_COMMON_TABLE_HEADER sHeader; 4472 UCHAR ucMiscInfo; 4473 UCHAR uc480i; 4474 UCHAR uc480p; 4475 UCHAR uc720p; 4476 UCHAR uc1080i; 4477 UCHAR ucReserved; 4478 UCHAR ucLetterBoxMode; 4479 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4480 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4481 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4482}ATOM_COMPONENT_VIDEO_INFO_V21; 4483 4484#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 4485 4486/****************************************************************************/ 4487// Structure used in object_InfoTable 4488/****************************************************************************/ 4489typedef struct _ATOM_OBJECT_HEADER 4490{ 4491 ATOM_COMMON_TABLE_HEADER sHeader; 4492 USHORT usDeviceSupport; 4493 USHORT usConnectorObjectTableOffset; 4494 USHORT usRouterObjectTableOffset; 4495 USHORT usEncoderObjectTableOffset; 4496 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4497 USHORT usDisplayPathTableOffset; 4498}ATOM_OBJECT_HEADER; 4499 4500typedef struct _ATOM_OBJECT_HEADER_V3 4501{ 4502 ATOM_COMMON_TABLE_HEADER sHeader; 4503 USHORT usDeviceSupport; 4504 USHORT usConnectorObjectTableOffset; 4505 USHORT usRouterObjectTableOffset; 4506 USHORT usEncoderObjectTableOffset; 4507 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4508 USHORT usDisplayPathTableOffset; 4509 USHORT usMiscObjectTableOffset; 4510}ATOM_OBJECT_HEADER_V3; 4511 4512 4513typedef struct _ATOM_DISPLAY_OBJECT_PATH 4514{ 4515 USHORT usDeviceTag; //supported device 4516 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4517 USHORT usConnObjectId; //Connector Object ID 4518 USHORT usGPUObjectId; //GPU ID 4519 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 4520}ATOM_DISPLAY_OBJECT_PATH; 4521 4522typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 4523{ 4524 USHORT usDeviceTag; //supported device 4525 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4526 USHORT usConnObjectId; //Connector Object ID 4527 USHORT usGPUObjectId; //GPU ID 4528 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 4529}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 4530 4531typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 4532{ 4533 UCHAR ucNumOfDispPath; 4534 UCHAR ucVersion; 4535 UCHAR ucPadding[2]; 4536 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 4537}ATOM_DISPLAY_OBJECT_PATH_TABLE; 4538 4539typedef struct _ATOM_OBJECT //each object has this structure 4540{ 4541 USHORT usObjectID; 4542 USHORT usSrcDstTableOffset; 4543 USHORT usRecordOffset; //this pointing to a bunch of records defined below 4544 USHORT usReserved; 4545}ATOM_OBJECT; 4546 4547typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 4548{ 4549 UCHAR ucNumberOfObjects; 4550 UCHAR ucPadding[3]; 4551 ATOM_OBJECT asObjects[1]; 4552}ATOM_OBJECT_TABLE; 4553 4554typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 4555{ 4556 UCHAR ucNumberOfSrc; 4557 USHORT usSrcObjectID[1]; 4558 UCHAR ucNumberOfDst; 4559 USHORT usDstObjectID[1]; 4560}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 4561 4562 4563//Two definitions below are for OPM on MXM module designs 4564 4565#define EXT_HPDPIN_LUTINDEX_0 0 4566#define EXT_HPDPIN_LUTINDEX_1 1 4567#define EXT_HPDPIN_LUTINDEX_2 2 4568#define EXT_HPDPIN_LUTINDEX_3 3 4569#define EXT_HPDPIN_LUTINDEX_4 4 4570#define EXT_HPDPIN_LUTINDEX_5 5 4571#define EXT_HPDPIN_LUTINDEX_6 6 4572#define EXT_HPDPIN_LUTINDEX_7 7 4573#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4574 4575#define EXT_AUXDDC_LUTINDEX_0 0 4576#define EXT_AUXDDC_LUTINDEX_1 1 4577#define EXT_AUXDDC_LUTINDEX_2 2 4578#define EXT_AUXDDC_LUTINDEX_3 3 4579#define EXT_AUXDDC_LUTINDEX_4 4 4580#define EXT_AUXDDC_LUTINDEX_5 5 4581#define EXT_AUXDDC_LUTINDEX_6 6 4582#define EXT_AUXDDC_LUTINDEX_7 7 4583#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4584 4585//ucChannelMapping are defined as following 4586//for DP connector, eDP, DP to VGA/LVDS 4587//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4588//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4589//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4590//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4591typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4592{ 4593#if ATOM_BIG_ENDIAN 4594 UCHAR ucDP_Lane3_Source:2; 4595 UCHAR ucDP_Lane2_Source:2; 4596 UCHAR ucDP_Lane1_Source:2; 4597 UCHAR ucDP_Lane0_Source:2; 4598#else 4599 UCHAR ucDP_Lane0_Source:2; 4600 UCHAR ucDP_Lane1_Source:2; 4601 UCHAR ucDP_Lane2_Source:2; 4602 UCHAR ucDP_Lane3_Source:2; 4603#endif 4604}ATOM_DP_CONN_CHANNEL_MAPPING; 4605 4606//for DVI/HDMI, in dual link case, both links have to have same mapping. 4607//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4608//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4609//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4610//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4611typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4612{ 4613#if ATOM_BIG_ENDIAN 4614 UCHAR ucDVI_CLK_Source:2; 4615 UCHAR ucDVI_DATA0_Source:2; 4616 UCHAR ucDVI_DATA1_Source:2; 4617 UCHAR ucDVI_DATA2_Source:2; 4618#else 4619 UCHAR ucDVI_DATA2_Source:2; 4620 UCHAR ucDVI_DATA1_Source:2; 4621 UCHAR ucDVI_DATA0_Source:2; 4622 UCHAR ucDVI_CLK_Source:2; 4623#endif 4624}ATOM_DVI_CONN_CHANNEL_MAPPING; 4625 4626typedef struct _EXT_DISPLAY_PATH 4627{ 4628 USHORT usDeviceTag; //A bit vector to show what devices are supported 4629 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4630 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4631 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4632 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4633 USHORT usExtEncoderObjId; //external encoder object id 4634 union{ 4635 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4636 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4637 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4638 }; 4639 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4640 USHORT usCaps; 4641 USHORT usReserved; 4642}EXT_DISPLAY_PATH; 4643 4644#define NUMBER_OF_UCHAR_FOR_GUID 16 4645#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4646 4647//usCaps 4648#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x0001 4649#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x0002 4650#define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C 4651#define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip 4652#define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip 4653#define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recoverter chip 4654 4655 4656 4657 4658typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4659{ 4660 ATOM_COMMON_TABLE_HEADER sHeader; 4661 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4662 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4663 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4664 UCHAR uc3DStereoPinId; // use for eDP panel 4665 UCHAR ucRemoteDisplayConfig; 4666 UCHAR uceDPToLVDSRxId; 4667 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value 4668 UCHAR Reserved[3]; // for potential expansion 4669}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4670 4671//Related definitions, all records are different but they have a common header 4672typedef struct _ATOM_COMMON_RECORD_HEADER 4673{ 4674 UCHAR ucRecordType; //An emun to indicate the record type 4675 UCHAR ucRecordSize; //The size of the whole record in byte 4676}ATOM_COMMON_RECORD_HEADER; 4677 4678 4679#define ATOM_I2C_RECORD_TYPE 1 4680#define ATOM_HPD_INT_RECORD_TYPE 2 4681#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4682#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4683#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4684#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4685#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4686#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4687#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4688#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4689#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4690#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4691#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4692#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4693#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4694#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4695#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4696#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4697#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4698#define ATOM_ENCODER_CAP_RECORD_TYPE 20 4699#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 4700#define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 22 4701 4702//Must be updated when new record type is added,equal to that record definition! 4703#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 4704 4705typedef struct _ATOM_I2C_RECORD 4706{ 4707 ATOM_COMMON_RECORD_HEADER sheader; 4708 ATOM_I2C_ID_CONFIG sucI2cId; 4709 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4710}ATOM_I2C_RECORD; 4711 4712typedef struct _ATOM_HPD_INT_RECORD 4713{ 4714 ATOM_COMMON_RECORD_HEADER sheader; 4715 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4716 UCHAR ucPlugged_PinState; 4717}ATOM_HPD_INT_RECORD; 4718 4719 4720typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4721{ 4722 ATOM_COMMON_RECORD_HEADER sheader; 4723 UCHAR ucProtectionFlag; 4724 UCHAR ucReserved; 4725}ATOM_OUTPUT_PROTECTION_RECORD; 4726 4727typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4728{ 4729 ULONG ulACPIDeviceEnum; //Reserved for now 4730 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4731 USHORT usPadding; 4732}ATOM_CONNECTOR_DEVICE_TAG; 4733 4734typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4735{ 4736 ATOM_COMMON_RECORD_HEADER sheader; 4737 UCHAR ucNumberOfDevice; 4738 UCHAR ucReserved; 4739 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4740}ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4741 4742 4743typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4744{ 4745 ATOM_COMMON_RECORD_HEADER sheader; 4746 UCHAR ucConfigGPIOID; 4747 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4748 UCHAR ucFlowinGPIPID; 4749 UCHAR ucExtInGPIPID; 4750}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4751 4752typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4753{ 4754 ATOM_COMMON_RECORD_HEADER sheader; 4755 UCHAR ucCTL1GPIO_ID; 4756 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4757 UCHAR ucCTL2GPIO_ID; 4758 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4759 UCHAR ucCTL3GPIO_ID; 4760 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4761 UCHAR ucCTLFPGA_IN_ID; 4762 UCHAR ucPadding[3]; 4763}ATOM_ENCODER_FPGA_CONTROL_RECORD; 4764 4765typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4766{ 4767 ATOM_COMMON_RECORD_HEADER sheader; 4768 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4769 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4770}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4771 4772typedef struct _ATOM_JTAG_RECORD 4773{ 4774 ATOM_COMMON_RECORD_HEADER sheader; 4775 UCHAR ucTMSGPIO_ID; 4776 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4777 UCHAR ucTCKGPIO_ID; 4778 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4779 UCHAR ucTDOGPIO_ID; 4780 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4781 UCHAR ucTDIGPIO_ID; 4782 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4783 UCHAR ucPadding[2]; 4784}ATOM_JTAG_RECORD; 4785 4786 4787//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4788typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4789{ 4790 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4791 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4792}ATOM_GPIO_PIN_CONTROL_PAIR; 4793 4794typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4795{ 4796 ATOM_COMMON_RECORD_HEADER sheader; 4797 UCHAR ucFlags; // Future expnadibility 4798 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4799 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4800}ATOM_OBJECT_GPIO_CNTL_RECORD; 4801 4802//Definitions for GPIO pin state 4803#define GPIO_PIN_TYPE_INPUT 0x00 4804#define GPIO_PIN_TYPE_OUTPUT 0x10 4805#define GPIO_PIN_TYPE_HW_CONTROL 0x20 4806 4807//For GPIO_PIN_TYPE_OUTPUT the following is defined 4808#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4809#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4810#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4811#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4812 4813// Indexes to GPIO array in GLSync record 4814// GLSync record is for Frame Lock/Gen Lock feature. 4815#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4816#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4817#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4818#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4819#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4820#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4821#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4822#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4823#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4824#define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4825 4826typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4827{ 4828 ATOM_COMMON_RECORD_HEADER sheader; 4829 ULONG ulStrengthControl; // DVOA strength control for CF 4830 UCHAR ucPadding[2]; 4831}ATOM_ENCODER_DVO_CF_RECORD; 4832 4833// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 4834#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 4835#define ATOM_ENCODER_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not. 4836#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4837#define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not. 4838#define ATOM_ENCODER_CAP_RECORD_HBR3_EN 0x08 // DP1.3 HBR3 is supported by board. 4839 4840typedef struct _ATOM_ENCODER_CAP_RECORD 4841{ 4842 ATOM_COMMON_RECORD_HEADER sheader; 4843 union { 4844 USHORT usEncoderCap; 4845 struct { 4846#if ATOM_BIG_ENDIAN 4847 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4848 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4849 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4850#else 4851 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4852 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4853 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4854#endif 4855 }; 4856 }; 4857}ATOM_ENCODER_CAP_RECORD; 4858 4859// Used after SI 4860typedef struct _ATOM_ENCODER_CAP_RECORD_V2 4861{ 4862 ATOM_COMMON_RECORD_HEADER sheader; 4863 union { 4864 USHORT usEncoderCap; 4865 struct { 4866#if ATOM_BIG_ENDIAN 4867 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future 4868 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable 4869 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) 4870 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4871 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable 4872#else 4873 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable 4874 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4875 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) 4876 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable 4877 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future 4878#endif 4879 }; 4880 }; 4881}ATOM_ENCODER_CAP_RECORD_V2; 4882 4883 4884// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4885#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4886#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4887 4888typedef struct _ATOM_CONNECTOR_CF_RECORD 4889{ 4890 ATOM_COMMON_RECORD_HEADER sheader; 4891 USHORT usMaxPixClk; 4892 UCHAR ucFlowCntlGpioId; 4893 UCHAR ucSwapCntlGpioId; 4894 UCHAR ucConnectedDvoBundle; 4895 UCHAR ucPadding; 4896}ATOM_CONNECTOR_CF_RECORD; 4897 4898typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4899{ 4900 ATOM_COMMON_RECORD_HEADER sheader; 4901 ATOM_DTD_FORMAT asTiming; 4902}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4903 4904typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4905{ 4906 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4907 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4908 UCHAR ucReserved; 4909}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4910 4911 4912typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4913{ 4914 ATOM_COMMON_RECORD_HEADER sheader; 4915 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4916 UCHAR ucMuxControlPin; 4917 UCHAR ucMuxState[2]; //for alligment purpose 4918}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4919 4920typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4921{ 4922 ATOM_COMMON_RECORD_HEADER sheader; 4923 UCHAR ucMuxType; 4924 UCHAR ucMuxControlPin; 4925 UCHAR ucMuxState[2]; //for alligment purpose 4926}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4927 4928// define ucMuxType 4929#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4930#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4931 4932typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4933{ 4934 ATOM_COMMON_RECORD_HEADER sheader; 4935 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4936}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4937 4938typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4939{ 4940 ATOM_COMMON_RECORD_HEADER sheader; 4941 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4942}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4943 4944typedef struct _ATOM_OBJECT_LINK_RECORD 4945{ 4946 ATOM_COMMON_RECORD_HEADER sheader; 4947 USHORT usObjectID; //could be connector, encorder or other object in object.h 4948}ATOM_OBJECT_LINK_RECORD; 4949 4950typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4951{ 4952 ATOM_COMMON_RECORD_HEADER sheader; 4953 USHORT usReserved; 4954}ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4955 4956 4957typedef struct _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD 4958{ 4959 ATOM_COMMON_RECORD_HEADER sheader; 4960 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 4961 UCHAR ucMaxTmdsClkRateIn2_5Mhz; 4962 UCHAR ucReserved; 4963} ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD; 4964 4965 4966typedef struct _ATOM_CONNECTOR_LAYOUT_INFO 4967{ 4968 USHORT usConnectorObjectId; 4969 UCHAR ucConnectorType; 4970 UCHAR ucPosition; 4971}ATOM_CONNECTOR_LAYOUT_INFO; 4972 4973// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 4974#define CONNECTOR_TYPE_DVI_D 1 4975#define CONNECTOR_TYPE_DVI_I 2 4976#define CONNECTOR_TYPE_VGA 3 4977#define CONNECTOR_TYPE_HDMI 4 4978#define CONNECTOR_TYPE_DISPLAY_PORT 5 4979#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 4980 4981typedef struct _ATOM_BRACKET_LAYOUT_RECORD 4982{ 4983 ATOM_COMMON_RECORD_HEADER sheader; 4984 UCHAR ucLength; 4985 UCHAR ucWidth; 4986 UCHAR ucConnNum; 4987 UCHAR ucReserved; 4988 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; 4989}ATOM_BRACKET_LAYOUT_RECORD; 4990 4991 4992/****************************************************************************/ 4993// Structure used in XXXX 4994/****************************************************************************/ 4995typedef struct _ATOM_VOLTAGE_INFO_HEADER 4996{ 4997 USHORT usVDDCBaseLevel; //In number of 50mv unit 4998 USHORT usReserved; //For possible extension table offset 4999 UCHAR ucNumOfVoltageEntries; 5000 UCHAR ucBytesPerVoltageEntry; 5001 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 5002 UCHAR ucDefaultVoltageEntry; 5003 UCHAR ucVoltageControlI2cLine; 5004 UCHAR ucVoltageControlAddress; 5005 UCHAR ucVoltageControlOffset; 5006}ATOM_VOLTAGE_INFO_HEADER; 5007 5008typedef struct _ATOM_VOLTAGE_INFO 5009{ 5010 ATOM_COMMON_TABLE_HEADER sHeader; 5011 ATOM_VOLTAGE_INFO_HEADER viHeader; 5012 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 5013}ATOM_VOLTAGE_INFO; 5014 5015 5016typedef struct _ATOM_VOLTAGE_FORMULA 5017{ 5018 USHORT usVoltageBaseLevel; // In number of 1mv unit 5019 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 5020 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 5021 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 5022 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 5023 UCHAR ucReserved; 5024 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 5025}ATOM_VOLTAGE_FORMULA; 5026 5027typedef struct _VOLTAGE_LUT_ENTRY 5028{ 5029 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 5030 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 5031}VOLTAGE_LUT_ENTRY; 5032 5033typedef struct _ATOM_VOLTAGE_FORMULA_V2 5034{ 5035 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 5036 UCHAR ucReserved[3]; 5037 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 5038}ATOM_VOLTAGE_FORMULA_V2; 5039 5040typedef struct _ATOM_VOLTAGE_CONTROL 5041{ 5042 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 5043 UCHAR ucVoltageControlI2cLine; 5044 UCHAR ucVoltageControlAddress; 5045 UCHAR ucVoltageControlOffset; 5046 USHORT usGpioPin_AIndex; //GPIO_PAD register index 5047 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 5048 UCHAR ucReserved; 5049}ATOM_VOLTAGE_CONTROL; 5050 5051// Define ucVoltageControlId 5052#define VOLTAGE_CONTROLLED_BY_HW 0x00 5053#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 5054#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 5055#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 5056#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 5057#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 5058#define VOLTAGE_CONTROL_ID_DS4402 0x04 5059#define VOLTAGE_CONTROL_ID_UP6266 0x05 5060#define VOLTAGE_CONTROL_ID_SCORPIO 0x06 5061#define VOLTAGE_CONTROL_ID_VT1556M 0x07 5062#define VOLTAGE_CONTROL_ID_CHL822x 0x08 5063#define VOLTAGE_CONTROL_ID_VT1586M 0x09 5064#define VOLTAGE_CONTROL_ID_UP1637 0x0A 5065#define VOLTAGE_CONTROL_ID_CHL8214 0x0B 5066#define VOLTAGE_CONTROL_ID_UP1801 0x0C 5067#define VOLTAGE_CONTROL_ID_ST6788A 0x0D 5068#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E 5069#define VOLTAGE_CONTROL_ID_AD527x 0x0F 5070#define VOLTAGE_CONTROL_ID_NCP81022 0x10 5071#define VOLTAGE_CONTROL_ID_LTC2635 0x11 5072#define VOLTAGE_CONTROL_ID_NCP4208 0x12 5073#define VOLTAGE_CONTROL_ID_IR35xx 0x13 5074#define VOLTAGE_CONTROL_ID_RT9403 0x14 5075 5076#define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40 5077 5078typedef struct _ATOM_VOLTAGE_OBJECT 5079{ 5080 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5081 UCHAR ucSize; //Size of Object 5082 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 5083 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 5084}ATOM_VOLTAGE_OBJECT; 5085 5086typedef struct _ATOM_VOLTAGE_OBJECT_V2 5087{ 5088 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5089 UCHAR ucSize; //Size of Object 5090 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 5091 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 5092}ATOM_VOLTAGE_OBJECT_V2; 5093 5094typedef struct _ATOM_VOLTAGE_OBJECT_INFO 5095{ 5096 ATOM_COMMON_TABLE_HEADER sHeader; 5097 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 5098}ATOM_VOLTAGE_OBJECT_INFO; 5099 5100typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 5101{ 5102 ATOM_COMMON_TABLE_HEADER sHeader; 5103 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 5104}ATOM_VOLTAGE_OBJECT_INFO_V2; 5105 5106typedef struct _ATOM_LEAKID_VOLTAGE 5107{ 5108 UCHAR ucLeakageId; 5109 UCHAR ucReserved; 5110 USHORT usVoltage; 5111}ATOM_LEAKID_VOLTAGE; 5112 5113typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 5114 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5115 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 5116 USHORT usSize; //Size of Object 5117}ATOM_VOLTAGE_OBJECT_HEADER_V3; 5118 5119// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode 5120#define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 5121#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 5122#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 5123#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 5124#define VOLTAGE_OBJ_EVV 8 5125#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5126#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5127#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5128 5129typedef struct _VOLTAGE_LUT_ENTRY_V2 5130{ 5131 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 5132 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 5133}VOLTAGE_LUT_ENTRY_V2; 5134 5135typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 5136{ 5137 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 5138 USHORT usVoltageId; 5139 USHORT usLeakageId; // The corresponding Voltage Value, in mV 5140}LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 5141 5142 5143typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 5144{ 5145 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 5146 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 5147 UCHAR ucVoltageControlI2cLine; 5148 UCHAR ucVoltageControlAddress; 5149 UCHAR ucVoltageControlOffset; 5150 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data 5151 UCHAR ulReserved[3]; 5152 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 5153}ATOM_I2C_VOLTAGE_OBJECT_V3; 5154 5155// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 5156#define VOLTAGE_DATA_ONE_BYTE 0 5157#define VOLTAGE_DATA_TWO_BYTE 1 5158 5159typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 5160{ 5161 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 5162 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 5163 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 5164 UCHAR ucPhaseDelay; // phase delay in unit of micro second 5165 UCHAR ucReserved; 5166 ULONG ulGpioMaskVal; // GPIO Mask value 5167 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 5168}ATOM_GPIO_VOLTAGE_OBJECT_V3; 5169 5170typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5171{ 5172 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 5173 UCHAR ucLeakageCntlId; // default is 0 5174 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 5175 UCHAR ucReserved[2]; 5176 ULONG ulMaxVoltageLevel; 5177 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 5178}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 5179 5180 5181typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 5182{ 5183 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 5184// 14:7 - PSI0_VID 5185// 6 - PSI0_EN 5186// 5 - PSI1 5187// 4:2 - load line slope trim. 5188// 1:0 - offset trim, 5189 USHORT usLoadLine_PSI; 5190// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 5191 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 5192 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 5193 ULONG ulReserved; 5194}ATOM_SVID2_VOLTAGE_OBJECT_V3; 5195 5196 5197 5198typedef struct _ATOM_MERGED_VOLTAGE_OBJECT_V3 5199{ 5200 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 5201 UCHAR ucMergedVType; // VDDC/VDCCI/.... 5202 UCHAR ucReserved[3]; 5203}ATOM_MERGED_VOLTAGE_OBJECT_V3; 5204 5205 5206typedef struct _ATOM_EVV_DPM_INFO 5207{ 5208 ULONG ulDPMSclk; // DPM state SCLK 5209 USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv 5210 UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable 5211 UCHAR ucDPMState; // DPMState0~7 5212} ATOM_EVV_DPM_INFO; 5213 5214// ucVoltageMode = VOLTAGE_OBJ_EVV 5215typedef struct _ATOM_EVV_VOLTAGE_OBJECT_V3 5216{ 5217 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 5218 ATOM_EVV_DPM_INFO asEvvDpmList[8]; 5219}ATOM_EVV_VOLTAGE_OBJECT_V3; 5220 5221 5222typedef union _ATOM_VOLTAGE_OBJECT_V3{ 5223 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 5224 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 5225 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 5226 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; 5227 ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvObj; 5228}ATOM_VOLTAGE_OBJECT_V3; 5229 5230typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 5231{ 5232 ATOM_COMMON_TABLE_HEADER sHeader; 5233 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 5234}ATOM_VOLTAGE_OBJECT_INFO_V3_1; 5235 5236 5237typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 5238{ 5239 UCHAR ucProfileId; 5240 UCHAR ucReserved; 5241 USHORT usSize; 5242 USHORT usEfuseSpareStartAddr; 5243 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 5244 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 5245}ATOM_ASIC_PROFILE_VOLTAGE; 5246 5247//ucProfileId 5248#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 5249#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 5250#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 5251 5252typedef struct _ATOM_ASIC_PROFILING_INFO 5253{ 5254 ATOM_COMMON_TABLE_HEADER asHeader; 5255 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 5256}ATOM_ASIC_PROFILING_INFO; 5257 5258typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 5259{ 5260 ATOM_COMMON_TABLE_HEADER asHeader; 5261 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table 5262 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 5263 5264 UCHAR ucElbVDDC_Num; 5265 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) 5266 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 5267 5268 UCHAR ucElbVDDCI_Num; 5269 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 5270 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 5271}ATOM_ASIC_PROFILING_INFO_V2_1; 5272 5273 5274//Here is parameter to convert Efuse value to Measure value 5275//Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2 5276typedef struct _EFUSE_LOGISTIC_FUNC_PARAM 5277{ 5278 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 5279 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 5280 UCHAR ucEfuseLength; // Efuse bits length, 5281 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 5282 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2 5283}EFUSE_LOGISTIC_FUNC_PARAM; 5284 5285//Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min ) 5286typedef struct _EFUSE_LINEAR_FUNC_PARAM 5287{ 5288 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 5289 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 5290 UCHAR ucEfuseLength; // Efuse bits length, 5291 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 5292 ULONG ulEfuseMin; // Min 5293}EFUSE_LINEAR_FUNC_PARAM; 5294 5295 5296typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 5297{ 5298 ATOM_COMMON_TABLE_HEADER asHeader; 5299 ULONG ulEvvDerateTdp; 5300 ULONG ulEvvDerateTdc; 5301 ULONG ulBoardCoreTemp; 5302 ULONG ulMaxVddc; 5303 ULONG ulMinVddc; 5304 ULONG ulLoadLineSlop; 5305 ULONG ulLeakageTemp; 5306 ULONG ulLeakageVoltage; 5307 EFUSE_LINEAR_FUNC_PARAM sCACm; 5308 EFUSE_LINEAR_FUNC_PARAM sCACb; 5309 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5310 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5311 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5312 USHORT usLkgEuseIndex; 5313 UCHAR ucLkgEfuseBitLSB; 5314 UCHAR ucLkgEfuseLength; 5315 ULONG ulLkgEncodeLn_MaxDivMin; 5316 ULONG ulLkgEncodeMax; 5317 ULONG ulLkgEncodeMin; 5318 ULONG ulEfuseLogisticAlpha; 5319 USHORT usPowerDpm0; 5320 USHORT usCurrentDpm0; 5321 USHORT usPowerDpm1; 5322 USHORT usCurrentDpm1; 5323 USHORT usPowerDpm2; 5324 USHORT usCurrentDpm2; 5325 USHORT usPowerDpm3; 5326 USHORT usCurrentDpm3; 5327 USHORT usPowerDpm4; 5328 USHORT usCurrentDpm4; 5329 USHORT usPowerDpm5; 5330 USHORT usCurrentDpm5; 5331 USHORT usPowerDpm6; 5332 USHORT usCurrentDpm6; 5333 USHORT usPowerDpm7; 5334 USHORT usCurrentDpm7; 5335}ATOM_ASIC_PROFILING_INFO_V3_1; 5336 5337 5338typedef struct _ATOM_ASIC_PROFILING_INFO_V3_2 5339{ 5340 ATOM_COMMON_TABLE_HEADER asHeader; 5341 ULONG ulEvvLkgFactor; 5342 ULONG ulBoardCoreTemp; 5343 ULONG ulMaxVddc; 5344 ULONG ulMinVddc; 5345 ULONG ulLoadLineSlop; 5346 ULONG ulLeakageTemp; 5347 ULONG ulLeakageVoltage; 5348 EFUSE_LINEAR_FUNC_PARAM sCACm; 5349 EFUSE_LINEAR_FUNC_PARAM sCACb; 5350 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5351 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5352 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5353 USHORT usLkgEuseIndex; 5354 UCHAR ucLkgEfuseBitLSB; 5355 UCHAR ucLkgEfuseLength; 5356 ULONG ulLkgEncodeLn_MaxDivMin; 5357 ULONG ulLkgEncodeMax; 5358 ULONG ulLkgEncodeMin; 5359 ULONG ulEfuseLogisticAlpha; 5360 USHORT usPowerDpm0; 5361 USHORT usPowerDpm1; 5362 USHORT usPowerDpm2; 5363 USHORT usPowerDpm3; 5364 USHORT usPowerDpm4; 5365 USHORT usPowerDpm5; 5366 USHORT usPowerDpm6; 5367 USHORT usPowerDpm7; 5368 ULONG ulTdpDerateDPM0; 5369 ULONG ulTdpDerateDPM1; 5370 ULONG ulTdpDerateDPM2; 5371 ULONG ulTdpDerateDPM3; 5372 ULONG ulTdpDerateDPM4; 5373 ULONG ulTdpDerateDPM5; 5374 ULONG ulTdpDerateDPM6; 5375 ULONG ulTdpDerateDPM7; 5376}ATOM_ASIC_PROFILING_INFO_V3_2; 5377 5378 5379// for Tonga/Fiji speed EVV algorithm 5380typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3 5381{ 5382 ATOM_COMMON_TABLE_HEADER asHeader; 5383 ULONG ulEvvLkgFactor; 5384 ULONG ulBoardCoreTemp; 5385 ULONG ulMaxVddc; 5386 ULONG ulMinVddc; 5387 ULONG ulLoadLineSlop; 5388 ULONG ulLeakageTemp; 5389 ULONG ulLeakageVoltage; 5390 EFUSE_LINEAR_FUNC_PARAM sCACm; 5391 EFUSE_LINEAR_FUNC_PARAM sCACb; 5392 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5393 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5394 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5395 USHORT usLkgEuseIndex; 5396 UCHAR ucLkgEfuseBitLSB; 5397 UCHAR ucLkgEfuseLength; 5398 ULONG ulLkgEncodeLn_MaxDivMin; 5399 ULONG ulLkgEncodeMax; 5400 ULONG ulLkgEncodeMin; 5401 ULONG ulEfuseLogisticAlpha; 5402 5403 union{ 5404 USHORT usPowerDpm0; 5405 USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m max is postive 5406 }; 5407 USHORT usPowerDpm1; 5408 USHORT usPowerDpm2; 5409 USHORT usPowerDpm3; 5410 USHORT usPowerDpm4; 5411 USHORT usPowerDpm5; 5412 USHORT usPowerDpm6; 5413 USHORT usPowerDpm7; 5414 ULONG ulTdpDerateDPM0; 5415 ULONG ulTdpDerateDPM1; 5416 ULONG ulTdpDerateDPM2; 5417 ULONG ulTdpDerateDPM3; 5418 ULONG ulTdpDerateDPM4; 5419 ULONG ulTdpDerateDPM5; 5420 ULONG ulTdpDerateDPM6; 5421 ULONG ulTdpDerateDPM7; 5422 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5423 ULONG ulRoAlpha; 5424 ULONG ulRoBeta; 5425 ULONG ulRoGamma; 5426 ULONG ulRoEpsilon; 5427 ULONG ulATermRo; 5428 ULONG ulBTermRo; 5429 ULONG ulCTermRo; 5430 ULONG ulSclkMargin; 5431 ULONG ulFmaxPercent; 5432 ULONG ulCRPercent; 5433 ULONG ulSFmaxPercent; 5434 ULONG ulSCRPercent; 5435 ULONG ulSDCMargine; 5436}ATOM_ASIC_PROFILING_INFO_V3_3; 5437 5438// for Fiji speed EVV algorithm 5439typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4 5440{ 5441 ATOM_COMMON_TABLE_HEADER asHeader; 5442 ULONG ulEvvLkgFactor; 5443 ULONG ulBoardCoreTemp; 5444 ULONG ulMaxVddc; 5445 ULONG ulMinVddc; 5446 ULONG ulLoadLineSlop; 5447 ULONG ulLeakageTemp; 5448 ULONG ulLeakageVoltage; 5449 EFUSE_LINEAR_FUNC_PARAM sCACm; 5450 EFUSE_LINEAR_FUNC_PARAM sCACb; 5451 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5452 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5453 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5454 USHORT usLkgEuseIndex; 5455 UCHAR ucLkgEfuseBitLSB; 5456 UCHAR ucLkgEfuseLength; 5457 ULONG ulLkgEncodeLn_MaxDivMin; 5458 ULONG ulLkgEncodeMax; 5459 ULONG ulLkgEncodeMin; 5460 ULONG ulEfuseLogisticAlpha; 5461 USHORT usPowerDpm0; 5462 USHORT usPowerDpm1; 5463 USHORT usPowerDpm2; 5464 USHORT usPowerDpm3; 5465 USHORT usPowerDpm4; 5466 USHORT usPowerDpm5; 5467 USHORT usPowerDpm6; 5468 USHORT usPowerDpm7; 5469 ULONG ulTdpDerateDPM0; 5470 ULONG ulTdpDerateDPM1; 5471 ULONG ulTdpDerateDPM2; 5472 ULONG ulTdpDerateDPM3; 5473 ULONG ulTdpDerateDPM4; 5474 ULONG ulTdpDerateDPM5; 5475 ULONG ulTdpDerateDPM6; 5476 ULONG ulTdpDerateDPM7; 5477 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5478 ULONG ulEvvDefaultVddc; 5479 ULONG ulEvvNoCalcVddc; 5480 USHORT usParamNegFlag; 5481 USHORT usSpeed_Model; 5482 ULONG ulSM_A0; 5483 ULONG ulSM_A1; 5484 ULONG ulSM_A2; 5485 ULONG ulSM_A3; 5486 ULONG ulSM_A4; 5487 ULONG ulSM_A5; 5488 ULONG ulSM_A6; 5489 ULONG ulSM_A7; 5490 UCHAR ucSM_A0_sign; 5491 UCHAR ucSM_A1_sign; 5492 UCHAR ucSM_A2_sign; 5493 UCHAR ucSM_A3_sign; 5494 UCHAR ucSM_A4_sign; 5495 UCHAR ucSM_A5_sign; 5496 UCHAR ucSM_A6_sign; 5497 UCHAR ucSM_A7_sign; 5498 ULONG ulMargin_RO_a; 5499 ULONG ulMargin_RO_b; 5500 ULONG ulMargin_RO_c; 5501 ULONG ulMargin_fixed; 5502 ULONG ulMargin_Fmax_mean; 5503 ULONG ulMargin_plat_mean; 5504 ULONG ulMargin_Fmax_sigma; 5505 ULONG ulMargin_plat_sigma; 5506 ULONG ulMargin_DC_sigma; 5507 ULONG ulReserved[8]; // Reserved for future ASIC 5508}ATOM_ASIC_PROFILING_INFO_V3_4; 5509 5510// for Polaris10/Polaris11 speed EVV algorithm 5511typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5 5512{ 5513 ATOM_COMMON_TABLE_HEADER asHeader; 5514 ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv 5515 ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv 5516 USHORT usLkgEuseIndex; //Efuse Lkg_FT address ( BYTE address ) 5517 UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD 5518 UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length 5519 ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 ) 5520 ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) 5521 ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) 5522 EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1. 5523 ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/> 5524 ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/> 5525 ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/> 5526 ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/> 5527 ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/> 5528 ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/> 5529 ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/> 5530 ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/> 5531 ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/> 5532 ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/> 5533 ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/> 5534 UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/> 5535 UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/> 5536 UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/> 5537 UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/> 5538 UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/> 5539 UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/> 5540 UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/> 5541 UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/> 5542 ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1" 5543 ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1" 5544 ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1" 5545 ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/> 5546 ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/> 5547 ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/> 5548 ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/> 5549 ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/> 5550 ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/> 5551 ULONG ulReserved[12]; 5552}ATOM_ASIC_PROFILING_INFO_V3_5; 5553 5554/* for Polars10/11 AVFS parameters */ 5555typedef struct _ATOM_ASIC_PROFILING_INFO_V3_6 5556{ 5557 ATOM_COMMON_TABLE_HEADER asHeader; 5558 ULONG ulMaxVddc; 5559 ULONG ulMinVddc; 5560 USHORT usLkgEuseIndex; 5561 UCHAR ucLkgEfuseBitLSB; 5562 UCHAR ucLkgEfuseLength; 5563 ULONG ulLkgEncodeLn_MaxDivMin; 5564 ULONG ulLkgEncodeMax; 5565 ULONG ulLkgEncodeMin; 5566 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5567 ULONG ulEvvDefaultVddc; 5568 ULONG ulEvvNoCalcVddc; 5569 ULONG ulSpeed_Model; 5570 ULONG ulSM_A0; 5571 ULONG ulSM_A1; 5572 ULONG ulSM_A2; 5573 ULONG ulSM_A3; 5574 ULONG ulSM_A4; 5575 ULONG ulSM_A5; 5576 ULONG ulSM_A6; 5577 ULONG ulSM_A7; 5578 UCHAR ucSM_A0_sign; 5579 UCHAR ucSM_A1_sign; 5580 UCHAR ucSM_A2_sign; 5581 UCHAR ucSM_A3_sign; 5582 UCHAR ucSM_A4_sign; 5583 UCHAR ucSM_A5_sign; 5584 UCHAR ucSM_A6_sign; 5585 UCHAR ucSM_A7_sign; 5586 ULONG ulMargin_RO_a; 5587 ULONG ulMargin_RO_b; 5588 ULONG ulMargin_RO_c; 5589 ULONG ulMargin_fixed; 5590 ULONG ulMargin_Fmax_mean; 5591 ULONG ulMargin_plat_mean; 5592 ULONG ulMargin_Fmax_sigma; 5593 ULONG ulMargin_plat_sigma; 5594 ULONG ulMargin_DC_sigma; 5595 ULONG ulLoadLineSlop; 5596 ULONG ulaTDClimitPerDPM[8]; 5597 ULONG ulaNoCalcVddcPerDPM[8]; 5598 ULONG ulAVFS_meanNsigma_Acontant0; 5599 ULONG ulAVFS_meanNsigma_Acontant1; 5600 ULONG ulAVFS_meanNsigma_Acontant2; 5601 USHORT usAVFS_meanNsigma_DC_tol_sigma; 5602 USHORT usAVFS_meanNsigma_Platform_mean; 5603 USHORT usAVFS_meanNsigma_Platform_sigma; 5604 ULONG ulGB_VDROOP_TABLE_CKSOFF_a0; 5605 ULONG ulGB_VDROOP_TABLE_CKSOFF_a1; 5606 ULONG ulGB_VDROOP_TABLE_CKSOFF_a2; 5607 ULONG ulGB_VDROOP_TABLE_CKSON_a0; 5608 ULONG ulGB_VDROOP_TABLE_CKSON_a1; 5609 ULONG ulGB_VDROOP_TABLE_CKSON_a2; 5610 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1; 5611 USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2; 5612 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b; 5613 ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1; 5614 USHORT usAVFSGB_FUSE_TABLE_CKSON_m2; 5615 ULONG ulAVFSGB_FUSE_TABLE_CKSON_b; 5616 USHORT usMaxVoltage_0_25mv; 5617 UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF; 5618 UCHAR ucEnableGB_VDROOP_TABLE_CKSON; 5619 UCHAR ucEnableGB_FUSE_TABLE_CKSOFF; 5620 UCHAR ucEnableGB_FUSE_TABLE_CKSON; 5621 USHORT usPSM_Age_ComFactor; 5622 UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage; 5623 UCHAR ucReserved; 5624}ATOM_ASIC_PROFILING_INFO_V3_6; 5625 5626 5627typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{ 5628 ULONG ulMaxSclkFreq; 5629 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz 5630 UCHAR ucPostdiv; // divide by 2^n 5631 USHORT ucFcw_pcc; 5632 USHORT ucFcw_trans_upper; 5633 USHORT ucRcw_trans_lower; 5634}ATOM_SCLK_FCW_RANGE_ENTRY_V1; 5635 5636 5637// SMU_InfoTable for Polaris10/Polaris11 5638typedef struct _ATOM_SMU_INFO_V2_1 5639{ 5640 ATOM_COMMON_TABLE_HEADER asHeader; 5641 UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1 5642 UCHAR ucSMUVer; 5643 UCHAR ucSharePowerSource; 5644 UCHAR ucReserved; 5645 ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8]; 5646}ATOM_SMU_INFO_V2_1; 5647 5648 5649// GFX_InfoTable for Polaris10/Polaris11 5650typedef struct _ATOM_GFX_INFO_V2_1 5651{ 5652 ATOM_COMMON_TABLE_HEADER asHeader; 5653 UCHAR GfxIpMinVer; 5654 UCHAR GfxIpMajVer; 5655 UCHAR max_shader_engines; 5656 UCHAR max_tile_pipes; 5657 UCHAR max_cu_per_sh; 5658 UCHAR max_sh_per_se; 5659 UCHAR max_backends_per_se; 5660 UCHAR max_texture_channel_caches; 5661}ATOM_GFX_INFO_V2_1; 5662 5663typedef struct _ATOM_GFX_INFO_V2_3 5664{ 5665 ATOM_COMMON_TABLE_HEADER asHeader; 5666 UCHAR GfxIpMinVer; 5667 UCHAR GfxIpMajVer; 5668 UCHAR max_shader_engines; 5669 UCHAR max_tile_pipes; 5670 UCHAR max_cu_per_sh; 5671 UCHAR max_sh_per_se; 5672 UCHAR max_backends_per_se; 5673 UCHAR max_texture_channel_caches; 5674 USHORT usHiLoLeakageThreshold; 5675 USHORT usEdcDidtLoDpm7TableOffset; //offset of DPM7 low leakage table _ATOM_EDC_DIDT_TABLE_V1 5676 USHORT usEdcDidtHiDpm7TableOffset; //offset of DPM7 high leakage table _ATOM_EDC_DIDT_TABLE_V1 5677 USHORT usReserverd[3]; 5678}ATOM_GFX_INFO_V2_3; 5679 5680typedef struct _ATOM_POWER_SOURCE_OBJECT 5681{ 5682 UCHAR ucPwrSrcId; // Power source 5683 UCHAR ucPwrSensorType; // GPIO, I2C or none 5684 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 5685 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 5686 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 5687 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 5688 UCHAR ucPwrSensActiveState; // high active or low active 5689 UCHAR ucReserve[3]; // reserve 5690 USHORT usSensPwr; // in unit of watt 5691}ATOM_POWER_SOURCE_OBJECT; 5692 5693typedef struct _ATOM_POWER_SOURCE_INFO 5694{ 5695 ATOM_COMMON_TABLE_HEADER asHeader; 5696 UCHAR asPwrbehave[16]; 5697 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 5698}ATOM_POWER_SOURCE_INFO; 5699 5700 5701//Define ucPwrSrcId 5702#define POWERSOURCE_PCIE_ID1 0x00 5703#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 5704#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 5705#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 5706#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 5707 5708//define ucPwrSensorId 5709#define POWER_SENSOR_ALWAYS 0x00 5710#define POWER_SENSOR_GPIO 0x01 5711#define POWER_SENSOR_I2C 0x02 5712 5713typedef struct _ATOM_CLK_VOLT_CAPABILITY 5714{ 5715 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 5716 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5717}ATOM_CLK_VOLT_CAPABILITY; 5718 5719 5720typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2 5721{ 5722 USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv, 5723 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5724}ATOM_CLK_VOLT_CAPABILITY_V2; 5725 5726typedef struct _ATOM_AVAILABLE_SCLK_LIST 5727{ 5728 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5729 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 5730 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 5731}ATOM_AVAILABLE_SCLK_LIST; 5732 5733// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 5734#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 5735 5736// this IntegrateSystemInfoTable is used for Liano/Ontario APU 5737typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 5738{ 5739 ATOM_COMMON_TABLE_HEADER sHeader; 5740 ULONG ulBootUpEngineClock; 5741 ULONG ulDentistVCOFreq; 5742 ULONG ulBootUpUMAClock; 5743 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5744 ULONG ulBootUpReqDisplayVector; 5745 ULONG ulOtherDisplayMisc; 5746 ULONG ulGPUCapInfo; 5747 ULONG ulSB_MMIO_Base_Addr; 5748 USHORT usRequestedPWMFreqInHz; 5749 UCHAR ucHtcTmpLmt; 5750 UCHAR ucHtcHystLmt; 5751 ULONG ulMinEngineClock; 5752 ULONG ulSystemConfig; 5753 ULONG ulCPUCapInfo; 5754 USHORT usNBP0Voltage; 5755 USHORT usNBP1Voltage; 5756 USHORT usBootUpNBVoltage; 5757 USHORT usExtDispConnInfoOffset; 5758 USHORT usPanelRefreshRateRange; 5759 UCHAR ucMemoryType; 5760 UCHAR ucUMAChannelNumber; 5761 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 5762 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 5763 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 5764 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5765 ULONG ulGMCRestoreResetTime; 5766 ULONG ulMinimumNClk; 5767 ULONG ulIdleNClk; 5768 ULONG ulDDR_DLL_PowerUpTime; 5769 ULONG ulDDR_PLL_PowerUpTime; 5770 USHORT usPCIEClkSSPercentage; 5771 USHORT usPCIEClkSSType; 5772 USHORT usLvdsSSPercentage; 5773 USHORT usLvdsSSpreadRateIn10Hz; 5774 USHORT usHDMISSPercentage; 5775 USHORT usHDMISSpreadRateIn10Hz; 5776 USHORT usDVISSPercentage; 5777 USHORT usDVISSpreadRateIn10Hz; 5778 ULONG SclkDpmBoostMargin; 5779 ULONG SclkDpmThrottleMargin; 5780 USHORT SclkDpmTdpLimitPG; 5781 USHORT SclkDpmTdpLimitBoost; 5782 ULONG ulBoostEngineCLock; 5783 UCHAR ulBoostVid_2bit; 5784 UCHAR EnableBoost; 5785 USHORT GnbTdpLimit; 5786 USHORT usMaxLVDSPclkFreqInSingleLink; 5787 UCHAR ucLvdsMisc; 5788 UCHAR ucLVDSReserved; 5789 ULONG ulReserved3[15]; 5790 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5791}ATOM_INTEGRATED_SYSTEM_INFO_V6; 5792 5793// ulGPUCapInfo 5794#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5795#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 5796 5797//ucLVDSMisc: 5798#define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 5799#define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 5800#define SYS_INFO_LVDSMISC__888_BPC 0x04 5801#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 5802#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 5803// new since Trinity 5804#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 5805 5806// not used any more 5807#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 5808#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 5809 5810/********************************************************************************************************************** 5811 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 5812ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5813ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5814ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5815sDISPCLK_Voltage: Report Display clock voltage requirement. 5816 5817ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 5818 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5819 ATOM_DEVICE_CRT2_SUPPORT 0x0010 5820 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5821 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5822 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5823 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5824 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5825 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5826 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5827ulOtherDisplayMisc: Other display related flags, not defined yet. 5828ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5829 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5830 bit[3]=0: Enable HW AUX mode detection logic 5831 =1: Disable HW AUX mode dettion logic 5832ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5833 5834usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5835 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5836 5837 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5838 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5839 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5840 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5841 and enabling VariBri under the driver environment from PP table is optional. 5842 5843 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5844 that BL control from GPU is expected. 5845 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5846 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5847 it's per platform 5848 and enabling VariBri under the driver environment from PP table is optional. 5849 5850ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5851 Threshold on value to enter HTC_active state. 5852ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5853 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5854ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5855ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5856 =1: PCIE Power Gating Enabled 5857 Bit[1]=0: DDR-DLL shut-down feature disabled. 5858 1: DDR-DLL shut-down feature enabled. 5859 Bit[2]=0: DDR-PLL Power down feature disabled. 5860 1: DDR-PLL Power down feature enabled. 5861ulCPUCapInfo: TBD 5862usNBP0Voltage: VID for voltage on NB P0 State 5863usNBP1Voltage: VID for voltage on NB P1 State 5864usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5865usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5866usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5867 to indicate a range. 5868 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5869 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5870 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5871 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5872ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5873ucUMAChannelNumber: System memory channel numbers. 5874ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5875ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5876ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5877sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5878ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5879ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5880ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5881ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5882ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5883usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 5884usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5885usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5886usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5887usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5888usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5889usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5890usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5891usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5892ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5893 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5894 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5895 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5896 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5897**********************************************************************************************************************/ 5898 5899// this Table is used for Liano/Ontario APU 5900typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 5901{ 5902 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 5903 ULONG ulPowerplayTable[128]; 5904}ATOM_FUSION_SYSTEM_INFO_V1; 5905 5906 5907typedef struct _ATOM_TDP_CONFIG_BITS 5908{ 5909#if ATOM_BIG_ENDIAN 5910 ULONG uReserved:2; 5911 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5912 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5913 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5914#else 5915 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5916 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5917 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5918 ULONG uReserved:2; 5919#endif 5920}ATOM_TDP_CONFIG_BITS; 5921 5922typedef union _ATOM_TDP_CONFIG 5923{ 5924 ATOM_TDP_CONFIG_BITS TDP_config; 5925 ULONG TDP_config_all; 5926}ATOM_TDP_CONFIG; 5927 5928/********************************************************************************************************************** 5929 ATOM_FUSION_SYSTEM_INFO_V1 Description 5930sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 5931ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 5932**********************************************************************************************************************/ 5933 5934// this IntegrateSystemInfoTable is used for Trinity APU 5935typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 5936{ 5937 ATOM_COMMON_TABLE_HEADER sHeader; 5938 ULONG ulBootUpEngineClock; 5939 ULONG ulDentistVCOFreq; 5940 ULONG ulBootUpUMAClock; 5941 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5942 ULONG ulBootUpReqDisplayVector; 5943 ULONG ulOtherDisplayMisc; 5944 ULONG ulGPUCapInfo; 5945 ULONG ulSB_MMIO_Base_Addr; 5946 USHORT usRequestedPWMFreqInHz; 5947 UCHAR ucHtcTmpLmt; 5948 UCHAR ucHtcHystLmt; 5949 ULONG ulMinEngineClock; 5950 ULONG ulSystemConfig; 5951 ULONG ulCPUCapInfo; 5952 USHORT usNBP0Voltage; 5953 USHORT usNBP1Voltage; 5954 USHORT usBootUpNBVoltage; 5955 USHORT usExtDispConnInfoOffset; 5956 USHORT usPanelRefreshRateRange; 5957 UCHAR ucMemoryType; 5958 UCHAR ucUMAChannelNumber; 5959 UCHAR strVBIOSMsg[40]; 5960 ATOM_TDP_CONFIG asTdpConfig; 5961 ULONG ulReserved[19]; 5962 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5963 ULONG ulGMCRestoreResetTime; 5964 ULONG ulMinimumNClk; 5965 ULONG ulIdleNClk; 5966 ULONG ulDDR_DLL_PowerUpTime; 5967 ULONG ulDDR_PLL_PowerUpTime; 5968 USHORT usPCIEClkSSPercentage; 5969 USHORT usPCIEClkSSType; 5970 USHORT usLvdsSSPercentage; 5971 USHORT usLvdsSSpreadRateIn10Hz; 5972 USHORT usHDMISSPercentage; 5973 USHORT usHDMISSpreadRateIn10Hz; 5974 USHORT usDVISSPercentage; 5975 USHORT usDVISSpreadRateIn10Hz; 5976 ULONG SclkDpmBoostMargin; 5977 ULONG SclkDpmThrottleMargin; 5978 USHORT SclkDpmTdpLimitPG; 5979 USHORT SclkDpmTdpLimitBoost; 5980 ULONG ulBoostEngineCLock; 5981 UCHAR ulBoostVid_2bit; 5982 UCHAR EnableBoost; 5983 USHORT GnbTdpLimit; 5984 USHORT usMaxLVDSPclkFreqInSingleLink; 5985 UCHAR ucLvdsMisc; 5986 UCHAR ucTravisLVDSVolAdjust; 5987 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5988 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5989 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5990 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5991 UCHAR ucLVDSOffToOnDelay_in4Ms; 5992 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5993 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5994 UCHAR ucMinAllowedBL_Level; 5995 ULONG ulLCDBitDepthControlVal; 5996 ULONG ulNbpStateMemclkFreq[4]; 5997 USHORT usNBP2Voltage; 5998 USHORT usNBP3Voltage; 5999 ULONG ulNbpStateNClkFreq[4]; 6000 UCHAR ucNBDPMEnable; 6001 UCHAR ucReserved[3]; 6002 UCHAR ucDPMState0VclkFid; 6003 UCHAR ucDPMState0DclkFid; 6004 UCHAR ucDPMState1VclkFid; 6005 UCHAR ucDPMState1DclkFid; 6006 UCHAR ucDPMState2VclkFid; 6007 UCHAR ucDPMState2DclkFid; 6008 UCHAR ucDPMState3VclkFid; 6009 UCHAR ucDPMState3DclkFid; 6010 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6011}ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 6012 6013// ulOtherDisplayMisc 6014#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 6015#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 6016#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 6017#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 6018 6019// ulGPUCapInfo 6020#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 6021#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 6022#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 6023#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 6024//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 6025#define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000 6026 6027//ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML 6028#define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000 6029 6030/********************************************************************************************************************** 6031 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 6032ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 6033ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 6034ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 6035sDISPCLK_Voltage: Report Display clock voltage requirement. 6036 6037ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 6038 ATOM_DEVICE_CRT1_SUPPORT 0x0001 6039 ATOM_DEVICE_DFP1_SUPPORT 0x0008 6040 ATOM_DEVICE_DFP6_SUPPORT 0x0040 6041 ATOM_DEVICE_DFP2_SUPPORT 0x0080 6042 ATOM_DEVICE_DFP3_SUPPORT 0x0200 6043 ATOM_DEVICE_DFP4_SUPPORT 0x0400 6044 ATOM_DEVICE_DFP5_SUPPORT 0x0800 6045 ATOM_DEVICE_LCD1_SUPPORT 0x0002 6046ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 6047 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 6048 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 6049 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 6050 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 6051 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 6052 bit[3]=0: VBIOS fast boot is disable 6053 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 6054ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 6055 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 6056 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 6057 =1: DP mode use single PLL mode 6058 bit[3]=0: Enable AUX HW mode detection logic 6059 =1: Disable AUX HW mode detection logic 6060 6061ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 6062 6063usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 6064 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 6065 6066 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 6067 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 6068 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 6069 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 6070 and enabling VariBri under the driver environment from PP table is optional. 6071 6072 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 6073 that BL control from GPU is expected. 6074 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 6075 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 6076 it's per platform 6077 and enabling VariBri under the driver environment from PP table is optional. 6078 6079ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 6080 Threshold on value to enter HTC_active state. 6081ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 6082 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 6083ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 6084ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 6085 =1: PCIE Power Gating Enabled 6086 Bit[1]=0: DDR-DLL shut-down feature disabled. 6087 1: DDR-DLL shut-down feature enabled. 6088 Bit[2]=0: DDR-PLL Power down feature disabled. 6089 1: DDR-PLL Power down feature enabled. 6090ulCPUCapInfo: TBD 6091usNBP0Voltage: VID for voltage on NB P0 State 6092usNBP1Voltage: VID for voltage on NB P1 State 6093usNBP2Voltage: VID for voltage on NB P2 State 6094usNBP3Voltage: VID for voltage on NB P3 State 6095usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 6096usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 6097usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 6098 to indicate a range. 6099 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 6100 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 6101 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 6102 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 6103ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 6104ucUMAChannelNumber: System memory channel numbers. 6105ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 6106ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 6107ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 6108sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 6109ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 6110ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 6111ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 6112ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 6113ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 6114usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 6115usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 6116usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 6117usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6118usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6119usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6120usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6121usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6122usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 6123ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 6124 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 6125 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 6126 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 6127 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 6128 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 6129ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 6130 value to program Travis register LVDS_CTRL_4 6131ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 6132 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6133 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6134ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 6135 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6136 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6137 6138ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 6139 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6140 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6141 6142ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 6143 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6144 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6145 6146ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 6147 =0 means to use VBIOS default delay which is 125 ( 500ms ). 6148 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6149 6150ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 6151 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 6152 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6153 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6154 6155ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 6156 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 6157 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6158 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6159 6160ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 6161 6162ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 6163 6164**********************************************************************************************************************/ 6165 6166// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU 6167typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 6168{ 6169 ATOM_COMMON_TABLE_HEADER sHeader; 6170 ULONG ulBootUpEngineClock; 6171 ULONG ulDentistVCOFreq; 6172 ULONG ulBootUpUMAClock; 6173 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 6174 ULONG ulBootUpReqDisplayVector; 6175 ULONG ulVBIOSMisc; 6176 ULONG ulGPUCapInfo; 6177 ULONG ulDISP_CLK2Freq; 6178 USHORT usRequestedPWMFreqInHz; 6179 UCHAR ucHtcTmpLmt; 6180 UCHAR ucHtcHystLmt; 6181 ULONG ulReserved2; 6182 ULONG ulSystemConfig; 6183 ULONG ulCPUCapInfo; 6184 ULONG ulReserved3; 6185 USHORT usGPUReservedSysMemSize; 6186 USHORT usExtDispConnInfoOffset; 6187 USHORT usPanelRefreshRateRange; 6188 UCHAR ucMemoryType; 6189 UCHAR ucUMAChannelNumber; 6190 UCHAR strVBIOSMsg[40]; 6191 ATOM_TDP_CONFIG asTdpConfig; 6192 ULONG ulReserved[19]; 6193 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 6194 ULONG ulGMCRestoreResetTime; 6195 ULONG ulReserved4; 6196 ULONG ulIdleNClk; 6197 ULONG ulDDR_DLL_PowerUpTime; 6198 ULONG ulDDR_PLL_PowerUpTime; 6199 USHORT usPCIEClkSSPercentage; 6200 USHORT usPCIEClkSSType; 6201 USHORT usLvdsSSPercentage; 6202 USHORT usLvdsSSpreadRateIn10Hz; 6203 USHORT usHDMISSPercentage; 6204 USHORT usHDMISSpreadRateIn10Hz; 6205 USHORT usDVISSPercentage; 6206 USHORT usDVISSpreadRateIn10Hz; 6207 ULONG ulGPUReservedSysMemBaseAddrLo; 6208 ULONG ulGPUReservedSysMemBaseAddrHi; 6209 ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage; 6210 ULONG ulReserved5; 6211 USHORT usMaxLVDSPclkFreqInSingleLink; 6212 UCHAR ucLvdsMisc; 6213 UCHAR ucTravisLVDSVolAdjust; 6214 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6215 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6216 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6217 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6218 UCHAR ucLVDSOffToOnDelay_in4Ms; 6219 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6220 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6221 UCHAR ucMinAllowedBL_Level; 6222 ULONG ulLCDBitDepthControlVal; 6223 ULONG ulNbpStateMemclkFreq[4]; 6224 ULONG ulPSPVersion; 6225 ULONG ulNbpStateNClkFreq[4]; 6226 USHORT usNBPStateVoltage[4]; 6227 USHORT usBootUpNBVoltage; 6228 USHORT usReserved2; 6229 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6230}ATOM_INTEGRATED_SYSTEM_INFO_V1_8; 6231 6232/********************************************************************************************************************** 6233 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description 6234ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 6235ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 6236ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 6237sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). 6238 6239ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 6240 ATOM_DEVICE_CRT1_SUPPORT 0x0001 6241 ATOM_DEVICE_DFP1_SUPPORT 0x0008 6242 ATOM_DEVICE_DFP6_SUPPORT 0x0040 6243 ATOM_DEVICE_DFP2_SUPPORT 0x0080 6244 ATOM_DEVICE_DFP3_SUPPORT 0x0200 6245 ATOM_DEVICE_DFP4_SUPPORT 0x0400 6246 ATOM_DEVICE_DFP5_SUPPORT 0x0800 6247 ATOM_DEVICE_LCD1_SUPPORT 0x0002 6248 6249ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface 6250 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 6251 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 6252 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 6253 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 6254 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 6255 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 6256 bit[3]=0: VBIOS fast boot is disable 6257 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 6258 6259ulGPUCapInfo: bit[0~2]= Reserved 6260 bit[3]=0: Enable AUX HW mode detection logic 6261 =1: Disable AUX HW mode detection logic 6262 bit[4]=0: Disable DFS bypass feature 6263 =1: Enable DFS bypass feature 6264 6265usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 6266 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 6267 6268 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 6269 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 6270 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 6271 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 6272 and enabling VariBri under the driver environment from PP table is optional. 6273 6274 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 6275 that BL control from GPU is expected. 6276 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 6277 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 6278 it's per platform 6279 and enabling VariBri under the driver environment from PP table is optional. 6280 6281ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. 6282ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 6283 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 6284 6285ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 6286 =1: PCIE Power Gating Enabled 6287 Bit[1]=0: DDR-DLL shut-down feature disabled. 6288 1: DDR-DLL shut-down feature enabled. 6289 Bit[2]=0: DDR-PLL Power down feature disabled. 6290 1: DDR-PLL Power down feature enabled. 6291 Bit[3]=0: GNB DPM is disabled 6292 =1: GNB DPM is enabled 6293ulCPUCapInfo: TBD 6294 6295usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 6296usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 6297 to indicate a range. 6298 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 6299 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 6300 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 6301 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 6302 6303ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. 6304ucUMAChannelNumber: System memory channel numbers. 6305 6306strVBIOSMsg[40]: VBIOS boot up customized message string 6307 6308sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 6309 6310ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 6311ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. 6312ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 6313ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 6314 6315usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 6316usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 6317usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 6318usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6319usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6320usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6321usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6322usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6323 6324usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. 6325ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. 6326ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. 6327 6328usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 6329ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 6330 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 6331 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 6332 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 6333 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 6334 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 6335ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 6336 value to program Travis register LVDS_CTRL_4 6337ucLVDSPwrOnSeqDIGONtoDE_in4Ms: 6338 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 6339 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6340 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6341ucLVDSPwrOnDEtoVARY_BL_in4Ms: 6342 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 6343 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6344 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6345ucLVDSPwrOffVARY_BLtoDE_in4Ms: 6346 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 6347 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6348 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6349ucLVDSPwrOffDEtoDIGON_in4Ms: 6350 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 6351 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6352 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6353ucLVDSOffToOnDelay_in4Ms: 6354 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 6355 =0 means to use VBIOS default delay which is 125 ( 500ms ). 6356 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6357ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 6358 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 6359 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6360 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6361 6362ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 6363 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 6364 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6365 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6366ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 6367 6368ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL 6369 6370ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). 6371ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State 6372usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage 6373usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded 6374sExtDispConnInfo: Display connector information table provided to VBIOS 6375 6376**********************************************************************************************************************/ 6377 6378typedef struct _ATOM_I2C_REG_INFO 6379{ 6380 UCHAR ucI2cRegIndex; 6381 UCHAR ucI2cRegVal; 6382}ATOM_I2C_REG_INFO; 6383 6384// this IntegrateSystemInfoTable is used for Carrizo 6385typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 6386{ 6387 ATOM_COMMON_TABLE_HEADER sHeader; 6388 ULONG ulBootUpEngineClock; 6389 ULONG ulDentistVCOFreq; 6390 ULONG ulBootUpUMAClock; 6391 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error 6392 ULONG ulBootUpReqDisplayVector; 6393 ULONG ulVBIOSMisc; 6394 ULONG ulGPUCapInfo; 6395 ULONG ulDISP_CLK2Freq; 6396 USHORT usRequestedPWMFreqInHz; 6397 UCHAR ucHtcTmpLmt; 6398 UCHAR ucHtcHystLmt; 6399 ULONG ulReserved2; 6400 ULONG ulSystemConfig; 6401 ULONG ulCPUCapInfo; 6402 ULONG ulReserved3; 6403 USHORT usGPUReservedSysMemSize; 6404 USHORT usExtDispConnInfoOffset; 6405 USHORT usPanelRefreshRateRange; 6406 UCHAR ucMemoryType; 6407 UCHAR ucUMAChannelNumber; 6408 UCHAR strVBIOSMsg[40]; 6409 ATOM_TDP_CONFIG asTdpConfig; 6410 UCHAR ucExtHDMIReDrvSlvAddr; 6411 UCHAR ucExtHDMIReDrvRegNum; 6412 ATOM_I2C_REG_INFO asExtHDMIRegSetting[9]; 6413 ULONG ulReserved[2]; 6414 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 6415 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error 6416 ULONG ulGMCRestoreResetTime; 6417 ULONG ulReserved4; 6418 ULONG ulIdleNClk; 6419 ULONG ulDDR_DLL_PowerUpTime; 6420 ULONG ulDDR_PLL_PowerUpTime; 6421 USHORT usPCIEClkSSPercentage; 6422 USHORT usPCIEClkSSType; 6423 USHORT usLvdsSSPercentage; 6424 USHORT usLvdsSSpreadRateIn10Hz; 6425 USHORT usHDMISSPercentage; 6426 USHORT usHDMISSpreadRateIn10Hz; 6427 USHORT usDVISSPercentage; 6428 USHORT usDVISSpreadRateIn10Hz; 6429 ULONG ulGPUReservedSysMemBaseAddrLo; 6430 ULONG ulGPUReservedSysMemBaseAddrHi; 6431 ULONG ulReserved5[3]; 6432 USHORT usMaxLVDSPclkFreqInSingleLink; 6433 UCHAR ucLvdsMisc; 6434 UCHAR ucTravisLVDSVolAdjust; 6435 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6436 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6437 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6438 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6439 UCHAR ucLVDSOffToOnDelay_in4Ms; 6440 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6441 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6442 UCHAR ucMinAllowedBL_Level; 6443 ULONG ulLCDBitDepthControlVal; 6444 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed. 6445 ULONG ulPSPVersion; 6446 ULONG ulNbpStateNClkFreq[4]; 6447 USHORT usNBPStateVoltage[4]; 6448 USHORT usBootUpNBVoltage; 6449 UCHAR ucEDPv1_4VSMode; 6450 UCHAR ucReserved2; 6451 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6452}ATOM_INTEGRATED_SYSTEM_INFO_V1_9; 6453 6454 6455// definition for ucEDPv1_4VSMode 6456#define EDP_VS_LEGACY_MODE 0 6457#define EDP_VS_LOW_VDIFF_MODE 1 6458#define EDP_VS_HIGH_VDIFF_MODE 2 6459#define EDP_VS_STRETCH_MODE 3 6460#define EDP_VS_SINGLE_VDIFF_MODE 4 6461#define EDP_VS_VARIABLE_PREM_MODE 5 6462 6463 6464// ulGPUCapInfo 6465#define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT 0x08 6466#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS 0x10 6467//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 6468#define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE 0x00010000 6469//ulGPUCapInfo[18]=1 indicate the IOMMU is not available 6470#define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE 0x00040000 6471//ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened. 6472#define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE 0x00080000 6473 6474 6475typedef struct _DPHY_TIMING_PARA 6476{ 6477 UCHAR ucProfileID; // SENSOR_PROFILES 6478 ULONG ucPara; 6479} DPHY_TIMING_PARA; 6480 6481typedef struct _DPHY_ELEC_PARA 6482{ 6483 USHORT usPara[3]; 6484} DPHY_ELEC_PARA; 6485 6486typedef struct _CAMERA_MODULE_INFO 6487{ 6488 UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user 6489 UCHAR strModuleName[8]; 6490 DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor 6491} CAMERA_MODULE_INFO; 6492 6493typedef struct _FLASHLIGHT_INFO 6494{ 6495 UCHAR ucID; // 0: Rear, 1: Front 6496 UCHAR strName[8]; 6497} FLASHLIGHT_INFO; 6498 6499typedef struct _CAMERA_DATA 6500{ 6501 ULONG ulVersionCode; 6502 CAMERA_MODULE_INFO asCameraInfo[3]; // Assuming 3 camera sensors max 6503 FLASHLIGHT_INFO asFlashInfo; // Assuming 1 flashlight max 6504 DPHY_ELEC_PARA asDphyElecPara; 6505 ULONG ulCrcVal; // CRC 6506}CAMERA_DATA; 6507 6508typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 6509{ 6510 ATOM_COMMON_TABLE_HEADER sHeader; 6511 ULONG ulBootUpEngineClock; 6512 ULONG ulDentistVCOFreq; 6513 ULONG ulBootUpUMAClock; 6514 ULONG ulReserved0[8]; 6515 ULONG ulBootUpReqDisplayVector; 6516 ULONG ulVBIOSMisc; 6517 ULONG ulGPUCapInfo; 6518 ULONG ulReserved1; 6519 USHORT usRequestedPWMFreqInHz; 6520 UCHAR ucHtcTmpLmt; 6521 UCHAR ucHtcHystLmt; 6522 ULONG ulReserved2; 6523 ULONG ulSystemConfig; 6524 ULONG ulCPUCapInfo; 6525 ULONG ulReserved3; 6526 USHORT usGPUReservedSysMemSize; 6527 USHORT usExtDispConnInfoOffset; 6528 USHORT usPanelRefreshRateRange; 6529 UCHAR ucMemoryType; 6530 UCHAR ucUMAChannelNumber; 6531 ULONG ulMsgReserved[10]; 6532 ATOM_TDP_CONFIG asTdpConfig; 6533 ULONG ulReserved[7]; 6534 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 6535 ULONG ulReserved6[10]; 6536 ULONG ulGMCRestoreResetTime; 6537 ULONG ulReserved4; 6538 ULONG ulIdleNClk; 6539 ULONG ulDDR_DLL_PowerUpTime; 6540 ULONG ulDDR_PLL_PowerUpTime; 6541 USHORT usPCIEClkSSPercentage; 6542 USHORT usPCIEClkSSType; 6543 USHORT usLvdsSSPercentage; 6544 USHORT usLvdsSSpreadRateIn10Hz; 6545 USHORT usHDMISSPercentage; 6546 USHORT usHDMISSpreadRateIn10Hz; 6547 USHORT usDVISSPercentage; 6548 USHORT usDVISSpreadRateIn10Hz; 6549 ULONG ulGPUReservedSysMemBaseAddrLo; 6550 ULONG ulGPUReservedSysMemBaseAddrHi; 6551 ULONG ulReserved5[3]; 6552 USHORT usMaxLVDSPclkFreqInSingleLink; 6553 UCHAR ucLvdsMisc; 6554 UCHAR ucTravisLVDSVolAdjust; 6555 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6556 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6557 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6558 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6559 UCHAR ucLVDSOffToOnDelay_in4Ms; 6560 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6561 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6562 UCHAR ucMinAllowedBL_Level; 6563 ULONG ulLCDBitDepthControlVal; 6564 ULONG ulNbpStateMemclkFreq[2]; 6565 ULONG ulReserved7[2]; 6566 ULONG ulPSPVersion; 6567 ULONG ulNbpStateNClkFreq[4]; 6568 USHORT usNBPStateVoltage[4]; 6569 USHORT usBootUpNBVoltage; 6570 UCHAR ucEDPv1_4VSMode; 6571 UCHAR ucReserved2; 6572 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6573 CAMERA_DATA asCameraInfo; 6574 ULONG ulReserved8[29]; 6575}ATOM_INTEGRATED_SYSTEM_INFO_V1_10; 6576 6577 6578// this Table is used for Kaveri/Kabini APU 6579typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 6580{ 6581 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 6582 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure 6583}ATOM_FUSION_SYSTEM_INFO_V2; 6584 6585 6586typedef struct _ATOM_FUSION_SYSTEM_INFO_V3 6587{ 6588 ATOM_INTEGRATED_SYSTEM_INFO_V1_10 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 6589 ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable 6590}ATOM_FUSION_SYSTEM_INFO_V3; 6591 6592#define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x800 6593 6594/**************************************************************************/ 6595// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 6596//Memory SS Info Table 6597//Define Memory Clock SS chip ID 6598#define ICS91719 1 6599#define ICS91720 2 6600 6601//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 6602typedef struct _ATOM_I2C_DATA_RECORD 6603{ 6604 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 6605 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 6606}ATOM_I2C_DATA_RECORD; 6607 6608 6609//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 6610typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 6611{ 6612 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 6613 UCHAR ucSSChipID; //SS chip being used 6614 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 6615 UCHAR ucNumOfI2CDataRecords; //number of data block 6616 ATOM_I2C_DATA_RECORD asI2CData[1]; 6617}ATOM_I2C_DEVICE_SETUP_INFO; 6618 6619//========================================================================================== 6620typedef struct _ATOM_ASIC_MVDD_INFO 6621{ 6622 ATOM_COMMON_TABLE_HEADER sHeader; 6623 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 6624}ATOM_ASIC_MVDD_INFO; 6625 6626//========================================================================================== 6627#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 6628 6629//========================================================================================== 6630/**************************************************************************/ 6631 6632typedef struct _ATOM_ASIC_SS_ASSIGNMENT 6633{ 6634 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 6635 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 6636 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 6637 UCHAR ucClockIndication; //Indicate which clock source needs SS 6638 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 6639 UCHAR ucReserved[2]; 6640}ATOM_ASIC_SS_ASSIGNMENT; 6641 6642//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. 6643//SS is not required or enabled if a match is not found. 6644#define ASIC_INTERNAL_MEMORY_SS 1 6645#define ASIC_INTERNAL_ENGINE_SS 2 6646#define ASIC_INTERNAL_UVD_SS 3 6647#define ASIC_INTERNAL_SS_ON_TMDS 4 6648#define ASIC_INTERNAL_SS_ON_HDMI 5 6649#define ASIC_INTERNAL_SS_ON_LVDS 6 6650#define ASIC_INTERNAL_SS_ON_DP 7 6651#define ASIC_INTERNAL_SS_ON_DCPLL 8 6652#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 6653#define ASIC_INTERNAL_VCE_SS 10 6654#define ASIC_INTERNAL_GPUPLL_SS 11 6655 6656 6657typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 6658{ 6659 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 6660 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 6661 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 6662 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 6663 UCHAR ucClockIndication; //Indicate which clock source needs SS 6664 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6665 UCHAR ucReserved[2]; 6666}ATOM_ASIC_SS_ASSIGNMENT_V2; 6667 6668//ucSpreadSpectrumMode 6669//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 6670//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 6671//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 6672//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 6673//#define ATOM_INTERNAL_SS_MASK 0x00000000 6674//#define ATOM_EXTERNAL_SS_MASK 0x00000002 6675 6676typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 6677{ 6678 ATOM_COMMON_TABLE_HEADER sHeader; 6679 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 6680}ATOM_ASIC_INTERNAL_SS_INFO; 6681 6682typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 6683{ 6684 ATOM_COMMON_TABLE_HEADER sHeader; 6685 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 6686}ATOM_ASIC_INTERNAL_SS_INFO_V2; 6687 6688typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 6689{ 6690 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 6691 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 6692 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 6693 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 6694 UCHAR ucClockIndication; //Indicate which clock source needs SS 6695 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6696 UCHAR ucReserved[2]; 6697}ATOM_ASIC_SS_ASSIGNMENT_V3; 6698 6699//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode 6700#define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 6701#define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 6702#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 6703 6704typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 6705{ 6706 ATOM_COMMON_TABLE_HEADER sHeader; 6707 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 6708}ATOM_ASIC_INTERNAL_SS_INFO_V3; 6709 6710 6711//==============================Scratch Pad Definition Portion=============================== 6712#define ATOM_DEVICE_CONNECT_INFO_DEF 0 6713#define ATOM_ROM_LOCATION_DEF 1 6714#define ATOM_TV_STANDARD_DEF 2 6715#define ATOM_ACTIVE_INFO_DEF 3 6716#define ATOM_LCD_INFO_DEF 4 6717#define ATOM_DOS_REQ_INFO_DEF 5 6718#define ATOM_ACC_CHANGE_INFO_DEF 6 6719#define ATOM_DOS_MODE_INFO_DEF 7 6720#define ATOM_I2C_CHANNEL_STATUS_DEF 8 6721#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 6722#define ATOM_INTERNAL_TIMER_DEF 10 6723 6724// BIOS_0_SCRATCH Definition 6725#define ATOM_S0_CRT1_MONO 0x00000001L 6726#define ATOM_S0_CRT1_COLOR 0x00000002L 6727#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 6728 6729#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 6730#define ATOM_S0_TV1_SVIDEO_A 0x00000008L 6731#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 6732 6733#define ATOM_S0_CV_A 0x00000010L 6734#define ATOM_S0_CV_DIN_A 0x00000020L 6735#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 6736 6737 6738#define ATOM_S0_CRT2_MONO 0x00000100L 6739#define ATOM_S0_CRT2_COLOR 0x00000200L 6740#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 6741 6742#define ATOM_S0_TV1_COMPOSITE 0x00000400L 6743#define ATOM_S0_TV1_SVIDEO 0x00000800L 6744#define ATOM_S0_TV1_SCART 0x00004000L 6745#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 6746 6747#define ATOM_S0_CV 0x00001000L 6748#define ATOM_S0_CV_DIN 0x00002000L 6749#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 6750 6751#define ATOM_S0_DFP1 0x00010000L 6752#define ATOM_S0_DFP2 0x00020000L 6753#define ATOM_S0_LCD1 0x00040000L 6754#define ATOM_S0_LCD2 0x00080000L 6755#define ATOM_S0_DFP6 0x00100000L 6756#define ATOM_S0_DFP3 0x00200000L 6757#define ATOM_S0_DFP4 0x00400000L 6758#define ATOM_S0_DFP5 0x00800000L 6759 6760 6761#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 6762 6763#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 6764 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 6765 6766#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 6767#define ATOM_S0_THERMAL_STATE_SHIFT 26 6768 6769#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 6770#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 6771 6772#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 6773#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 6774#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 6775#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 6776 6777//Byte aligned defintion for BIOS usage 6778#define ATOM_S0_CRT1_MONOb0 0x01 6779#define ATOM_S0_CRT1_COLORb0 0x02 6780#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 6781 6782#define ATOM_S0_TV1_COMPOSITEb0 0x04 6783#define ATOM_S0_TV1_SVIDEOb0 0x08 6784#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 6785 6786#define ATOM_S0_CVb0 0x10 6787#define ATOM_S0_CV_DINb0 0x20 6788#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 6789 6790#define ATOM_S0_CRT2_MONOb1 0x01 6791#define ATOM_S0_CRT2_COLORb1 0x02 6792#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 6793 6794#define ATOM_S0_TV1_COMPOSITEb1 0x04 6795#define ATOM_S0_TV1_SVIDEOb1 0x08 6796#define ATOM_S0_TV1_SCARTb1 0x40 6797#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 6798 6799#define ATOM_S0_CVb1 0x10 6800#define ATOM_S0_CV_DINb1 0x20 6801#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 6802 6803#define ATOM_S0_DFP1b2 0x01 6804#define ATOM_S0_DFP2b2 0x02 6805#define ATOM_S0_LCD1b2 0x04 6806#define ATOM_S0_LCD2b2 0x08 6807#define ATOM_S0_DFP6b2 0x10 6808#define ATOM_S0_DFP3b2 0x20 6809#define ATOM_S0_DFP4b2 0x40 6810#define ATOM_S0_DFP5b2 0x80 6811 6812 6813#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 6814#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 6815 6816#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 6817#define ATOM_S0_LCD1_SHIFT 18 6818 6819// BIOS_1_SCRATCH Definition 6820#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 6821#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 6822 6823// BIOS_2_SCRATCH Definition 6824#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 6825#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 6826#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 6827 6828#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 6829#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 6830#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 6831 6832#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 6833#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 6834 6835#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 6836#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 6837#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 6838#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 6839#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 6840#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 6841 6842 6843//Byte aligned defintion for BIOS usage 6844#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 6845#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 6846#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 6847 6848#define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 6849#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 6850#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 6851 6852 6853// BIOS_3_SCRATCH Definition 6854#define ATOM_S3_CRT1_ACTIVE 0x00000001L 6855#define ATOM_S3_LCD1_ACTIVE 0x00000002L 6856#define ATOM_S3_TV1_ACTIVE 0x00000004L 6857#define ATOM_S3_DFP1_ACTIVE 0x00000008L 6858#define ATOM_S3_CRT2_ACTIVE 0x00000010L 6859#define ATOM_S3_LCD2_ACTIVE 0x00000020L 6860#define ATOM_S3_DFP6_ACTIVE 0x00000040L 6861#define ATOM_S3_DFP2_ACTIVE 0x00000080L 6862#define ATOM_S3_CV_ACTIVE 0x00000100L 6863#define ATOM_S3_DFP3_ACTIVE 0x00000200L 6864#define ATOM_S3_DFP4_ACTIVE 0x00000400L 6865#define ATOM_S3_DFP5_ACTIVE 0x00000800L 6866 6867 6868#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 6869 6870#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 6871#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 6872 6873#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 6874#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 6875#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 6876#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 6877#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 6878#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 6879#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 6880#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 6881#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 6882#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 6883#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 6884#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 6885 6886 6887#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 6888#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 6889//Below two definitions are not supported in pplib, but in the old powerplay in DAL 6890#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 6891#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 6892 6893 6894 6895//Byte aligned defintion for BIOS usage 6896#define ATOM_S3_CRT1_ACTIVEb0 0x01 6897#define ATOM_S3_LCD1_ACTIVEb0 0x02 6898#define ATOM_S3_TV1_ACTIVEb0 0x04 6899#define ATOM_S3_DFP1_ACTIVEb0 0x08 6900#define ATOM_S3_CRT2_ACTIVEb0 0x10 6901#define ATOM_S3_LCD2_ACTIVEb0 0x20 6902#define ATOM_S3_DFP6_ACTIVEb0 0x40 6903#define ATOM_S3_DFP2_ACTIVEb0 0x80 6904#define ATOM_S3_CV_ACTIVEb1 0x01 6905#define ATOM_S3_DFP3_ACTIVEb1 0x02 6906#define ATOM_S3_DFP4_ACTIVEb1 0x04 6907#define ATOM_S3_DFP5_ACTIVEb1 0x08 6908 6909 6910#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 6911 6912#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 6913#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 6914#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 6915#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 6916#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 6917#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 6918#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 6919#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 6920#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 6921#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 6922#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 6923#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 6924 6925 6926#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 6927 6928 6929// BIOS_4_SCRATCH Definition 6930#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 6931#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 6932#define ATOM_S4_LCD1_REFRESH_SHIFT 8 6933 6934//Byte aligned defintion for BIOS usage 6935#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 6936#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 6937#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 6938 6939// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 6940#define ATOM_S5_DOS_REQ_CRT1b0 0x01 6941#define ATOM_S5_DOS_REQ_LCD1b0 0x02 6942#define ATOM_S5_DOS_REQ_TV1b0 0x04 6943#define ATOM_S5_DOS_REQ_DFP1b0 0x08 6944#define ATOM_S5_DOS_REQ_CRT2b0 0x10 6945#define ATOM_S5_DOS_REQ_LCD2b0 0x20 6946#define ATOM_S5_DOS_REQ_DFP6b0 0x40 6947#define ATOM_S5_DOS_REQ_DFP2b0 0x80 6948#define ATOM_S5_DOS_REQ_CVb1 0x01 6949#define ATOM_S5_DOS_REQ_DFP3b1 0x02 6950#define ATOM_S5_DOS_REQ_DFP4b1 0x04 6951#define ATOM_S5_DOS_REQ_DFP5b1 0x08 6952 6953 6954#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 6955 6956#define ATOM_S5_DOS_REQ_CRT1 0x0001 6957#define ATOM_S5_DOS_REQ_LCD1 0x0002 6958#define ATOM_S5_DOS_REQ_TV1 0x0004 6959#define ATOM_S5_DOS_REQ_DFP1 0x0008 6960#define ATOM_S5_DOS_REQ_CRT2 0x0010 6961#define ATOM_S5_DOS_REQ_LCD2 0x0020 6962#define ATOM_S5_DOS_REQ_DFP6 0x0040 6963#define ATOM_S5_DOS_REQ_DFP2 0x0080 6964#define ATOM_S5_DOS_REQ_CV 0x0100 6965#define ATOM_S5_DOS_REQ_DFP3 0x0200 6966#define ATOM_S5_DOS_REQ_DFP4 0x0400 6967#define ATOM_S5_DOS_REQ_DFP5 0x0800 6968 6969#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 6970#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 6971#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 6972#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 6973#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 6974 (ATOM_S5_DOS_FORCE_CVb3<<8)) 6975// BIOS_6_SCRATCH Definition 6976#define ATOM_S6_DEVICE_CHANGE 0x00000001L 6977#define ATOM_S6_SCALER_CHANGE 0x00000002L 6978#define ATOM_S6_LID_CHANGE 0x00000004L 6979#define ATOM_S6_DOCKING_CHANGE 0x00000008L 6980#define ATOM_S6_ACC_MODE 0x00000010L 6981#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 6982#define ATOM_S6_LID_STATE 0x00000040L 6983#define ATOM_S6_DOCK_STATE 0x00000080L 6984#define ATOM_S6_CRITICAL_STATE 0x00000100L 6985#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 6986#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 6987#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 6988#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 6989#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 6990 6991#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 6992#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 6993 6994#define ATOM_S6_ACC_REQ_CRT1 0x00010000L 6995#define ATOM_S6_ACC_REQ_LCD1 0x00020000L 6996#define ATOM_S6_ACC_REQ_TV1 0x00040000L 6997#define ATOM_S6_ACC_REQ_DFP1 0x00080000L 6998#define ATOM_S6_ACC_REQ_CRT2 0x00100000L 6999#define ATOM_S6_ACC_REQ_LCD2 0x00200000L 7000#define ATOM_S6_ACC_REQ_DFP6 0x00400000L 7001#define ATOM_S6_ACC_REQ_DFP2 0x00800000L 7002#define ATOM_S6_ACC_REQ_CV 0x01000000L 7003#define ATOM_S6_ACC_REQ_DFP3 0x02000000L 7004#define ATOM_S6_ACC_REQ_DFP4 0x04000000L 7005#define ATOM_S6_ACC_REQ_DFP5 0x08000000L 7006 7007#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 7008#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 7009#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 7010#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 7011#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 7012 7013//Byte aligned defintion for BIOS usage 7014#define ATOM_S6_DEVICE_CHANGEb0 0x01 7015#define ATOM_S6_SCALER_CHANGEb0 0x02 7016#define ATOM_S6_LID_CHANGEb0 0x04 7017#define ATOM_S6_DOCKING_CHANGEb0 0x08 7018#define ATOM_S6_ACC_MODEb0 0x10 7019#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 7020#define ATOM_S6_LID_STATEb0 0x40 7021#define ATOM_S6_DOCK_STATEb0 0x80 7022#define ATOM_S6_CRITICAL_STATEb1 0x01 7023#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 7024#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 7025#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 7026#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 7027#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 7028 7029#define ATOM_S6_ACC_REQ_CRT1b2 0x01 7030#define ATOM_S6_ACC_REQ_LCD1b2 0x02 7031#define ATOM_S6_ACC_REQ_TV1b2 0x04 7032#define ATOM_S6_ACC_REQ_DFP1b2 0x08 7033#define ATOM_S6_ACC_REQ_CRT2b2 0x10 7034#define ATOM_S6_ACC_REQ_LCD2b2 0x20 7035#define ATOM_S6_ACC_REQ_DFP6b2 0x40 7036#define ATOM_S6_ACC_REQ_DFP2b2 0x80 7037#define ATOM_S6_ACC_REQ_CVb3 0x01 7038#define ATOM_S6_ACC_REQ_DFP3b3 0x02 7039#define ATOM_S6_ACC_REQ_DFP4b3 0x04 7040#define ATOM_S6_ACC_REQ_DFP5b3 0x08 7041 7042#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 7043#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 7044#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 7045#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 7046#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 7047 7048#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 7049#define ATOM_S6_SCALER_CHANGE_SHIFT 1 7050#define ATOM_S6_LID_CHANGE_SHIFT 2 7051#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 7052#define ATOM_S6_ACC_MODE_SHIFT 4 7053#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 7054#define ATOM_S6_LID_STATE_SHIFT 6 7055#define ATOM_S6_DOCK_STATE_SHIFT 7 7056#define ATOM_S6_CRITICAL_STATE_SHIFT 8 7057#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 7058#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 7059#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 7060#define ATOM_S6_REQ_SCALER_SHIFT 12 7061#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 7062#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 7063#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 7064#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 7065#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 7066#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 7067#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 7068 7069// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 7070#define ATOM_S7_DOS_MODE_TYPEb0 0x03 7071#define ATOM_S7_DOS_MODE_VGAb0 0x00 7072#define ATOM_S7_DOS_MODE_VESAb0 0x01 7073#define ATOM_S7_DOS_MODE_EXTb0 0x02 7074#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 7075#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 7076#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 7077#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 7078#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 7079#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 7080 7081#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 7082 7083// BIOS_8_SCRATCH Definition 7084#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 7085#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 7086 7087#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 7088#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 7089 7090// BIOS_9_SCRATCH Definition 7091#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 7092#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 7093#endif 7094#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 7095#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 7096#endif 7097#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 7098#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 7099#endif 7100#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 7101#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 7102#endif 7103 7104 7105#define ATOM_FLAG_SET 0x20 7106#define ATOM_FLAG_CLEAR 0 7107#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 7108#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 7109#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 7110#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 7111#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 7112 7113#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 7114#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 7115 7116#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 7117#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 7118#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 7119 7120#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 7121#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 7122#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 7123 7124#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 7125#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 7126 7127#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 7128#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 7129 7130#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 7131#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 7132 7133#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 7134 7135#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 7136 7137#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 7138#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 7139#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 7140#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 7141 7142/****************************************************************************/ 7143//Portion II: Definitinos only used in Driver 7144/****************************************************************************/ 7145 7146// Macros used by driver 7147 7148#ifdef __cplusplus 7149#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 7150 7151#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 7152#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 7153#else // not __cplusplus 7154#define GetIndexIntoMasterTable(MasterOrData, FieldName) (offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, FieldName) / sizeof(USHORT)) 7155 7156#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 7157#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 7158#endif // __cplusplus 7159 7160#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 7161#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 7162 7163/****************************************************************************/ 7164//Portion III: Definitinos only used in VBIOS 7165/****************************************************************************/ 7166#define ATOM_DAC_SRC 0x80 7167#define ATOM_SRC_DAC1 0 7168#define ATOM_SRC_DAC2 0x80 7169 7170 7171 7172typedef struct _MEMORY_PLLINIT_PARAMETERS 7173{ 7174 ULONG ulTargetMemoryClock; //In 10Khz unit 7175 UCHAR ucAction; //not define yet 7176 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 7177 UCHAR ucFbDiv; //FB value 7178 UCHAR ucPostDiv; //Post div 7179}MEMORY_PLLINIT_PARAMETERS; 7180 7181#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 7182 7183 7184#define GPIO_PIN_WRITE 0x01 7185#define GPIO_PIN_READ 0x00 7186 7187typedef struct _GPIO_PIN_CONTROL_PARAMETERS 7188{ 7189 UCHAR ucGPIO_ID; //return value, read from GPIO pins 7190 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 7191 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 7192 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 7193}GPIO_PIN_CONTROL_PARAMETERS; 7194 7195typedef struct _ENABLE_SCALER_PARAMETERS 7196{ 7197 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 7198 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 7199 UCHAR ucTVStandard; // 7200 UCHAR ucPadding[1]; 7201}ENABLE_SCALER_PARAMETERS; 7202#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 7203 7204//ucEnable: 7205#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 7206#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 7207#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 7208#define SCALER_ENABLE_MULTITAP_MODE 3 7209 7210typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 7211{ 7212 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 7213 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 7214 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 7215 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 7216 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7217}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 7218 7219typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 7220{ 7221 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 7222 ENABLE_CRTC_PARAMETERS sReserved; 7223}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 7224 7225typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 7226{ 7227 USHORT usHight; // Image Hight 7228 USHORT usWidth; // Image Width 7229 UCHAR ucSurface; // Surface 1 or 2 7230 UCHAR ucPadding[3]; 7231}ENABLE_GRAPH_SURFACE_PARAMETERS; 7232 7233typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 7234{ 7235 USHORT usHight; // Image Hight 7236 USHORT usWidth; // Image Width 7237 UCHAR ucSurface; // Surface 1 or 2 7238 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7239 UCHAR ucPadding[2]; 7240}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 7241 7242typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 7243{ 7244 USHORT usHight; // Image Hight 7245 USHORT usWidth; // Image Width 7246 UCHAR ucSurface; // Surface 1 or 2 7247 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7248 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 7249}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 7250 7251typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 7252{ 7253 USHORT usHight; // Image Hight 7254 USHORT usWidth; // Image Width 7255 USHORT usGraphPitch; 7256 UCHAR ucColorDepth; 7257 UCHAR ucPixelFormat; 7258 UCHAR ucSurface; // Surface 1 or 2 7259 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7260 UCHAR ucModeType; 7261 UCHAR ucReserved; 7262}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 7263 7264// ucEnable 7265#define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 7266#define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 7267 7268typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 7269{ 7270 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 7271 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 7272}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 7273 7274typedef struct _MEMORY_CLEAN_UP_PARAMETERS 7275{ 7276 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address 7277 USHORT usMemorySize; //8Kb blocks aligned 7278}MEMORY_CLEAN_UP_PARAMETERS; 7279 7280#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 7281 7282typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 7283{ 7284 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 7285 USHORT usY_Size; 7286}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 7287 7288typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 7289{ 7290 union{ 7291 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 7292 USHORT usSurface; 7293 }; 7294 USHORT usY_Size; 7295 USHORT usDispXStart; 7296 USHORT usDispYStart; 7297}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 7298 7299 7300typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 7301{ 7302 UCHAR ucLutId; 7303 UCHAR ucAction; 7304 USHORT usLutStartIndex; 7305 USHORT usLutLength; 7306 USHORT usLutOffsetInVram; 7307}PALETTE_DATA_CONTROL_PARAMETERS_V3; 7308 7309// ucAction: 7310#define PALETTE_DATA_AUTO_FILL 1 7311#define PALETTE_DATA_READ 2 7312#define PALETTE_DATA_WRITE 3 7313 7314 7315typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 7316{ 7317 UCHAR ucInterruptId; 7318 UCHAR ucServiceId; 7319 UCHAR ucStatus; 7320 UCHAR ucReserved; 7321}INTERRUPT_SERVICE_PARAMETER_V2; 7322 7323// ucInterruptId 7324#define HDP1_INTERRUPT_ID 1 7325#define HDP2_INTERRUPT_ID 2 7326#define HDP3_INTERRUPT_ID 3 7327#define HDP4_INTERRUPT_ID 4 7328#define HDP5_INTERRUPT_ID 5 7329#define HDP6_INTERRUPT_ID 6 7330#define SW_INTERRUPT_ID 11 7331 7332// ucAction 7333#define INTERRUPT_SERVICE_GEN_SW_INT 1 7334#define INTERRUPT_SERVICE_GET_STATUS 2 7335 7336 // ucStatus 7337#define INTERRUPT_STATUS__INT_TRIGGER 1 7338#define INTERRUPT_STATUS__HPD_HIGH 2 7339 7340typedef struct _EFUSE_INPUT_PARAMETER 7341{ 7342 USHORT usEfuseIndex; 7343 UCHAR ucBitShift; 7344 UCHAR ucBitLength; 7345}EFUSE_INPUT_PARAMETER; 7346 7347// ReadEfuseValue command table input/output parameter 7348typedef union _READ_EFUSE_VALUE_PARAMETER 7349{ 7350 EFUSE_INPUT_PARAMETER sEfuse; 7351 ULONG ulEfuseValue; 7352}READ_EFUSE_VALUE_PARAMETER; 7353 7354typedef struct _INDIRECT_IO_ACCESS 7355{ 7356 ATOM_COMMON_TABLE_HEADER sHeader; 7357 UCHAR IOAccessSequence[256]; 7358} INDIRECT_IO_ACCESS; 7359 7360#define INDIRECT_READ 0x00 7361#define INDIRECT_WRITE 0x80 7362 7363#define INDIRECT_IO_MM 0 7364#define INDIRECT_IO_PLL 1 7365#define INDIRECT_IO_MC 2 7366#define INDIRECT_IO_PCIE 3 7367#define INDIRECT_IO_PCIEP 4 7368#define INDIRECT_IO_NBMISC 5 7369#define INDIRECT_IO_SMU 5 7370 7371#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 7372#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 7373#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 7374#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 7375#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 7376#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 7377#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 7378#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 7379#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 7380#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 7381#define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ 7382#define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE 7383 7384 7385typedef struct _ATOM_OEM_INFO 7386{ 7387 ATOM_COMMON_TABLE_HEADER sHeader; 7388 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 7389}ATOM_OEM_INFO; 7390 7391typedef struct _ATOM_TV_MODE 7392{ 7393 UCHAR ucVMode_Num; //Video mode number 7394 UCHAR ucTV_Mode_Num; //Internal TV mode number 7395}ATOM_TV_MODE; 7396 7397typedef struct _ATOM_BIOS_INT_TVSTD_MODE 7398{ 7399 ATOM_COMMON_TABLE_HEADER sHeader; 7400 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 7401 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 7402 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 7403 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 7404 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 7405}ATOM_BIOS_INT_TVSTD_MODE; 7406 7407 7408typedef struct _ATOM_TV_MODE_SCALER_PTR 7409{ 7410 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 7411 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 7412 UCHAR ucTV_Mode_Num; 7413}ATOM_TV_MODE_SCALER_PTR; 7414 7415typedef struct _ATOM_STANDARD_VESA_TIMING 7416{ 7417 ATOM_COMMON_TABLE_HEADER sHeader; 7418 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 7419}ATOM_STANDARD_VESA_TIMING; 7420 7421 7422typedef struct _ATOM_STD_FORMAT 7423{ 7424 USHORT usSTD_HDisp; 7425 USHORT usSTD_VDisp; 7426 USHORT usSTD_RefreshRate; 7427 USHORT usReserved; 7428}ATOM_STD_FORMAT; 7429 7430typedef struct _ATOM_VESA_TO_EXTENDED_MODE 7431{ 7432 USHORT usVESA_ModeNumber; 7433 USHORT usExtendedModeNumber; 7434}ATOM_VESA_TO_EXTENDED_MODE; 7435 7436typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 7437{ 7438 ATOM_COMMON_TABLE_HEADER sHeader; 7439 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 7440}ATOM_VESA_TO_INTENAL_MODE_LUT; 7441 7442/*************** ATOM Memory Related Data Structure ***********************/ 7443typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 7444 UCHAR ucMemoryType; 7445 UCHAR ucMemoryVendor; 7446 UCHAR ucAdjMCId; 7447 UCHAR ucDynClkId; 7448 ULONG ulDllResetClkRange; 7449}ATOM_MEMORY_VENDOR_BLOCK; 7450 7451 7452typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 7453#if ATOM_BIG_ENDIAN 7454 ULONG ucMemBlkId:8; 7455 ULONG ulMemClockRange:24; 7456#else 7457 ULONG ulMemClockRange:24; 7458 ULONG ucMemBlkId:8; 7459#endif 7460}ATOM_MEMORY_SETTING_ID_CONFIG; 7461 7462typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 7463{ 7464 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 7465 ULONG ulAccess; 7466}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 7467 7468 7469typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 7470 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 7471 ULONG aulMemData[1]; 7472}ATOM_MEMORY_SETTING_DATA_BLOCK; 7473 7474 7475typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 7476 USHORT usRegIndex; // MC register index 7477 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 7478}ATOM_INIT_REG_INDEX_FORMAT; 7479 7480 7481typedef struct _ATOM_INIT_REG_BLOCK{ 7482 USHORT usRegIndexTblSize; //size of asRegIndexBuf 7483 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 7484 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 7485 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 7486}ATOM_INIT_REG_BLOCK; 7487 7488#define END_OF_REG_INDEX_BLOCK 0x0ffff 7489#define END_OF_REG_DATA_BLOCK 0x00000000 7490#define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 7491#define CLOCK_RANGE_HIGHEST 0x00ffffff 7492 7493#define VALUE_DWORD SIZEOF ULONG 7494#define VALUE_SAME_AS_ABOVE 0 7495#define VALUE_MASK_DWORD 0x84 7496 7497#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 7498#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 7499#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 7500//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 7501#define ACCESS_PLACEHOLDER 0x80 7502 7503 7504typedef struct _ATOM_MC_INIT_PARAM_TABLE 7505{ 7506 ATOM_COMMON_TABLE_HEADER sHeader; 7507 USHORT usAdjustARB_SEQDataOffset; 7508 USHORT usMCInitMemTypeTblOffset; 7509 USHORT usMCInitCommonTblOffset; 7510 USHORT usMCInitPowerDownTblOffset; 7511 ULONG ulARB_SEQDataBuf[32]; 7512 ATOM_INIT_REG_BLOCK asMCInitMemType; 7513 ATOM_INIT_REG_BLOCK asMCInitCommon; 7514}ATOM_MC_INIT_PARAM_TABLE; 7515 7516 7517typedef struct _ATOM_REG_INIT_SETTING 7518{ 7519 USHORT usRegIndex; 7520 ULONG ulRegValue; 7521}ATOM_REG_INIT_SETTING; 7522 7523typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 7524{ 7525 ATOM_COMMON_TABLE_HEADER sHeader; 7526 ULONG ulMCUcodeVersion; 7527 ULONG ulMCUcodeRomStartAddr; 7528 ULONG ulMCUcodeLength; 7529 USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings. 7530 USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting 7531}ATOM_MC_INIT_PARAM_TABLE_V2_1; 7532 7533 7534#define _4Mx16 0x2 7535#define _4Mx32 0x3 7536#define _8Mx16 0x12 7537#define _8Mx32 0x13 7538#define _8Mx128 0x15 7539#define _16Mx16 0x22 7540#define _16Mx32 0x23 7541#define _16Mx128 0x25 7542#define _32Mx16 0x32 7543#define _32Mx32 0x33 7544#define _32Mx128 0x35 7545#define _64Mx8 0x41 7546#define _64Mx16 0x42 7547#define _64Mx32 0x43 7548#define _64Mx128 0x45 7549#define _128Mx8 0x51 7550#define _128Mx16 0x52 7551#define _128Mx32 0x53 7552#define _256Mx8 0x61 7553#define _256Mx16 0x62 7554#define _256Mx32 0x63 7555#define _512Mx8 0x71 7556#define _512Mx16 0x72 7557 7558 7559#define SAMSUNG 0x1 7560#define INFINEON 0x2 7561#define ELPIDA 0x3 7562#define ETRON 0x4 7563#define NANYA 0x5 7564#define HYNIX 0x6 7565#define MOSEL 0x7 7566#define WINBOND 0x8 7567#define ESMT 0x9 7568#define MICRON 0xF 7569 7570#define QIMONDA INFINEON 7571#define PROMOS MOSEL 7572#define KRETON INFINEON 7573#define ELIXIR NANYA 7574#define MEZZA ELPIDA 7575 7576 7577/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 7578 7579#define UCODE_ROM_START_ADDRESS 0x1b800 7580#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 7581 7582//uCode block header for reference 7583 7584typedef struct _MCuCodeHeader 7585{ 7586 ULONG ulSignature; 7587 UCHAR ucRevision; 7588 UCHAR ucChecksum; 7589 UCHAR ucReserved1; 7590 UCHAR ucReserved2; 7591 USHORT usParametersLength; 7592 USHORT usUCodeLength; 7593 USHORT usReserved1; 7594 USHORT usReserved2; 7595} MCuCodeHeader; 7596 7597////////////////////////////////////////////////////////////////////////////////// 7598 7599#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 7600 7601#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 7602typedef struct _ATOM_VRAM_MODULE_V1 7603{ 7604 ULONG ulReserved; 7605 USHORT usEMRSValue; 7606 USHORT usMRSValue; 7607 USHORT usReserved; 7608 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7609 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 7610 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 7611 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 7612 UCHAR ucRow; // Number of Row,in power of 2; 7613 UCHAR ucColumn; // Number of Column,in power of 2; 7614 UCHAR ucBank; // Nunber of Bank; 7615 UCHAR ucRank; // Number of Rank, in power of 2 7616 UCHAR ucChannelNum; // Number of channel; 7617 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 7618 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 7619 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 7620 UCHAR ucReserved[2]; 7621}ATOM_VRAM_MODULE_V1; 7622 7623 7624typedef struct _ATOM_VRAM_MODULE_V2 7625{ 7626 ULONG ulReserved; 7627 ULONG ulFlags; // To enable/disable functionalities based on memory type 7628 ULONG ulEngineClock; // Override of default engine clock for particular memory type 7629 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 7630 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7631 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7632 USHORT usEMRSValue; 7633 USHORT usMRSValue; 7634 USHORT usReserved; 7635 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7636 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7637 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7638 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 7639 UCHAR ucRow; // Number of Row,in power of 2; 7640 UCHAR ucColumn; // Number of Column,in power of 2; 7641 UCHAR ucBank; // Nunber of Bank; 7642 UCHAR ucRank; // Number of Rank, in power of 2 7643 UCHAR ucChannelNum; // Number of channel; 7644 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 7645 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 7646 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 7647 UCHAR ucRefreshRateFactor; 7648 UCHAR ucReserved[3]; 7649}ATOM_VRAM_MODULE_V2; 7650 7651 7652typedef struct _ATOM_MEMORY_TIMING_FORMAT 7653{ 7654 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7655 union{ 7656 USHORT usMRS; // mode register 7657 USHORT usDDR3_MR0; 7658 }; 7659 union{ 7660 USHORT usEMRS; // extended mode register 7661 USHORT usDDR3_MR1; 7662 }; 7663 UCHAR ucCL; // CAS latency 7664 UCHAR ucWL; // WRITE Latency 7665 UCHAR uctRAS; // tRAS 7666 UCHAR uctRC; // tRC 7667 UCHAR uctRFC; // tRFC 7668 UCHAR uctRCDR; // tRCDR 7669 UCHAR uctRCDW; // tRCDW 7670 UCHAR uctRP; // tRP 7671 UCHAR uctRRD; // tRRD 7672 UCHAR uctWR; // tWR 7673 UCHAR uctWTR; // tWTR 7674 UCHAR uctPDIX; // tPDIX 7675 UCHAR uctFAW; // tFAW 7676 UCHAR uctAOND; // tAOND 7677 union 7678 { 7679 struct { 7680 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7681 UCHAR ucReserved; 7682 }; 7683 USHORT usDDR3_MR2; 7684 }; 7685}ATOM_MEMORY_TIMING_FORMAT; 7686 7687 7688typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 7689{ 7690 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7691 USHORT usMRS; // mode register 7692 USHORT usEMRS; // extended mode register 7693 UCHAR ucCL; // CAS latency 7694 UCHAR ucWL; // WRITE Latency 7695 UCHAR uctRAS; // tRAS 7696 UCHAR uctRC; // tRC 7697 UCHAR uctRFC; // tRFC 7698 UCHAR uctRCDR; // tRCDR 7699 UCHAR uctRCDW; // tRCDW 7700 UCHAR uctRP; // tRP 7701 UCHAR uctRRD; // tRRD 7702 UCHAR uctWR; // tWR 7703 UCHAR uctWTR; // tWTR 7704 UCHAR uctPDIX; // tPDIX 7705 UCHAR uctFAW; // tFAW 7706 UCHAR uctAOND; // tAOND 7707 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7708////////////////////////////////////GDDR parameters/////////////////////////////////// 7709 UCHAR uctCCDL; // 7710 UCHAR uctCRCRL; // 7711 UCHAR uctCRCWL; // 7712 UCHAR uctCKE; // 7713 UCHAR uctCKRSE; // 7714 UCHAR uctCKRSX; // 7715 UCHAR uctFAW32; // 7716 UCHAR ucMR5lo; // 7717 UCHAR ucMR5hi; // 7718 UCHAR ucTerminator; 7719}ATOM_MEMORY_TIMING_FORMAT_V1; 7720 7721 7722 7723 7724typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 7725{ 7726 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7727 USHORT usMRS; // mode register 7728 USHORT usEMRS; // extended mode register 7729 UCHAR ucCL; // CAS latency 7730 UCHAR ucWL; // WRITE Latency 7731 UCHAR uctRAS; // tRAS 7732 UCHAR uctRC; // tRC 7733 UCHAR uctRFC; // tRFC 7734 UCHAR uctRCDR; // tRCDR 7735 UCHAR uctRCDW; // tRCDW 7736 UCHAR uctRP; // tRP 7737 UCHAR uctRRD; // tRRD 7738 UCHAR uctWR; // tWR 7739 UCHAR uctWTR; // tWTR 7740 UCHAR uctPDIX; // tPDIX 7741 UCHAR uctFAW; // tFAW 7742 UCHAR uctAOND; // tAOND 7743 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7744////////////////////////////////////GDDR parameters/////////////////////////////////// 7745 UCHAR uctCCDL; // 7746 UCHAR uctCRCRL; // 7747 UCHAR uctCRCWL; // 7748 UCHAR uctCKE; // 7749 UCHAR uctCKRSE; // 7750 UCHAR uctCKRSX; // 7751 UCHAR uctFAW32; // 7752 UCHAR ucMR4lo; // 7753 UCHAR ucMR4hi; // 7754 UCHAR ucMR5lo; // 7755 UCHAR ucMR5hi; // 7756 UCHAR ucTerminator; 7757 UCHAR ucReserved; 7758}ATOM_MEMORY_TIMING_FORMAT_V2; 7759 7760 7761typedef struct _ATOM_MEMORY_FORMAT 7762{ 7763 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 7764 union{ 7765 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7766 USHORT usDDR3_Reserved; // Not used for DDR3 memory 7767 }; 7768 union{ 7769 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7770 USHORT usDDR3_MR3; // Used for DDR3 memory 7771 }; 7772 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7773 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7774 UCHAR ucRow; // Number of Row,in power of 2; 7775 UCHAR ucColumn; // Number of Column,in power of 2; 7776 UCHAR ucBank; // Nunber of Bank; 7777 UCHAR ucRank; // Number of Rank, in power of 2 7778 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 7779 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 7780 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 7781 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7782 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7783 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 7784 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock 7785}ATOM_MEMORY_FORMAT; 7786 7787 7788typedef struct _ATOM_VRAM_MODULE_V3 7789{ 7790 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 7791 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 7792 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 7793 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 7794 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7795 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 7796 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 7797 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 7798 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7799 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7800 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 7801}ATOM_VRAM_MODULE_V3; 7802 7803 7804//ATOM_VRAM_MODULE_V3.ucNPL_RT 7805#define NPL_RT_MASK 0x0f 7806#define BATTERY_ODT_MASK 0xc0 7807 7808#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 7809 7810typedef struct _ATOM_VRAM_MODULE_V4 7811{ 7812 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7813 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7814 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7815 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7816 USHORT usReserved; 7817 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7818 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7819 UCHAR ucChannelNum; // Number of channels present in this module config 7820 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7821 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7822 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7823 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7824 UCHAR ucVREFI; // board dependent parameter 7825 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7826 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7827 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7828 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7829 UCHAR ucReserved[3]; 7830 7831//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7832 union{ 7833 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7834 USHORT usDDR3_Reserved; 7835 }; 7836 union{ 7837 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7838 USHORT usDDR3_MR3; // Used for DDR3 memory 7839 }; 7840 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7841 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7842 UCHAR ucReserved2[2]; 7843 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7844}ATOM_VRAM_MODULE_V4; 7845 7846#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 7847#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 7848#define VRAM_MODULE_V4_MISC_BL_MASK 0x4 7849#define VRAM_MODULE_V4_MISC_BL8 0x4 7850#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 7851 7852typedef struct _ATOM_VRAM_MODULE_V5 7853{ 7854 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7855 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7856 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7857 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7858 USHORT usReserved; 7859 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7860 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7861 UCHAR ucChannelNum; // Number of channels present in this module config 7862 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7863 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7864 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7865 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7866 UCHAR ucVREFI; // board dependent parameter 7867 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7868 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7869 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7870 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7871 UCHAR ucReserved[3]; 7872 7873//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7874 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7875 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7876 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7877 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7878 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7879 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7880 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7881}ATOM_VRAM_MODULE_V5; 7882 7883 7884typedef struct _ATOM_VRAM_MODULE_V6 7885{ 7886 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7887 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7888 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7889 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7890 USHORT usReserved; 7891 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7892 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7893 UCHAR ucChannelNum; // Number of channels present in this module config 7894 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7895 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7896 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7897 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7898 UCHAR ucVREFI; // board dependent parameter 7899 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7900 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7901 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7902 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7903 UCHAR ucReserved[3]; 7904 7905//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7906 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7907 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7908 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7909 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7910 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7911 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7912 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7913}ATOM_VRAM_MODULE_V6; 7914 7915typedef struct _ATOM_VRAM_MODULE_V7 7916{ 7917// Design Specific Values 7918 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7919 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7920 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7921 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7922 UCHAR ucExtMemoryID; // Current memory module ID 7923 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7924 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7925 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7926 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7927 UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used. 7928 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7929 UCHAR ucVREFI; // Not used. 7930 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 7931 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7932 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7933 USHORT usSEQSettingOffset; 7934 UCHAR ucReserved; 7935// Memory Module specific values 7936 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7937 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7938 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7939 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7940 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7941 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7942 char strMemPNString[20]; // part number end with '0'. 7943}ATOM_VRAM_MODULE_V7; 7944 7945 7946typedef struct _ATOM_VRAM_MODULE_V8 7947{ 7948// Design Specific Values 7949 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7950 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7951 USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7952 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7953 UCHAR ucExtMemoryID; // Current memory module ID 7954 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7955 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7956 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7957 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7958 UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit ) 7959 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7960 UCHAR ucVREFI; // Not used. 7961 USHORT usReserved; // Not used 7962 USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 7963 UCHAR ucMcTunningSetId; // MC phy registers set per. 7964 UCHAR ucRowNum; 7965// Memory Module specific values 7966 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7967 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7968 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7969 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7970 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7971 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7972 7973 ULONG ulChannelMapCfg1; // channel mapping for channel8~15 7974 ULONG ulBankMapCfg; 7975 ULONG ulReserved; 7976 char strMemPNString[20]; // part number end with '0'. 7977}ATOM_VRAM_MODULE_V8; 7978 7979 7980typedef struct _ATOM_VRAM_INFO_V2 7981{ 7982 ATOM_COMMON_TABLE_HEADER sHeader; 7983 UCHAR ucNumOfVRAMModule; 7984 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7985}ATOM_VRAM_INFO_V2; 7986 7987typedef struct _ATOM_VRAM_INFO_V3 7988{ 7989 ATOM_COMMON_TABLE_HEADER sHeader; 7990 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7991 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7992 USHORT usRerseved; 7993 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 7994 UCHAR ucNumOfVRAMModule; 7995 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7996 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7997 7998}ATOM_VRAM_INFO_V3; 7999 8000#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 8001 8002typedef struct _ATOM_VRAM_INFO_V4 8003{ 8004 ATOM_COMMON_TABLE_HEADER sHeader; 8005 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 8006 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8007 USHORT usRerseved; 8008 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 8009 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 8010 UCHAR ucReservde[4]; 8011 UCHAR ucNumOfVRAMModule; 8012 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8013 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 8014}ATOM_VRAM_INFO_V4; 8015 8016typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 8017{ 8018 ATOM_COMMON_TABLE_HEADER sHeader; 8019 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 8020 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8021 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 8022 USHORT usReserved[3]; 8023 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 8024 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 8025 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 8026 UCHAR ucReserved; 8027 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8028}ATOM_VRAM_INFO_HEADER_V2_1; 8029 8030typedef struct _ATOM_VRAM_INFO_HEADER_V2_2 8031{ 8032 ATOM_COMMON_TABLE_HEADER sHeader; 8033 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 8034 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8035 USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 8036 USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set 8037 USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping 8038 USHORT usReserved1; 8039 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 8040 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 8041 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 8042 UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 8043 ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8044}ATOM_VRAM_INFO_HEADER_V2_2; 8045 8046 8047typedef struct _ATOM_DRAM_DATA_REMAP 8048{ 8049 UCHAR ucByteRemapCh0; 8050 UCHAR ucByteRemapCh1; 8051 ULONG ulByte0BitRemapCh0; 8052 ULONG ulByte1BitRemapCh0; 8053 ULONG ulByte2BitRemapCh0; 8054 ULONG ulByte3BitRemapCh0; 8055 ULONG ulByte0BitRemapCh1; 8056 ULONG ulByte1BitRemapCh1; 8057 ULONG ulByte2BitRemapCh1; 8058 ULONG ulByte3BitRemapCh1; 8059}ATOM_DRAM_DATA_REMAP; 8060 8061typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 8062{ 8063 ATOM_COMMON_TABLE_HEADER sHeader; 8064 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 8065}ATOM_VRAM_GPIO_DETECTION_INFO; 8066 8067 8068typedef struct _ATOM_MEMORY_TRAINING_INFO 8069{ 8070 ATOM_COMMON_TABLE_HEADER sHeader; 8071 UCHAR ucTrainingLoop; 8072 UCHAR ucReserved[3]; 8073 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 8074}ATOM_MEMORY_TRAINING_INFO; 8075 8076 8077typedef struct _ATOM_MEMORY_TRAINING_INFO_V3_1 8078{ 8079 ATOM_COMMON_TABLE_HEADER sHeader; 8080 ULONG ulMCUcodeVersion; 8081 USHORT usMCIOInitLen; //len of ATOM_REG_INIT_SETTING array 8082 USHORT usMCUcodeLen; //len of ATOM_MC_UCODE_DATA array 8083 USHORT usMCIORegInitOffset; //point of offset of ATOM_REG_INIT_SETTING array 8084 USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array. 8085}ATOM_MEMORY_TRAINING_INFO_V3_1; 8086 8087 8088typedef struct SW_I2C_CNTL_DATA_PARAMETERS 8089{ 8090 UCHAR ucControl; 8091 UCHAR ucData; 8092 UCHAR ucSatus; 8093 UCHAR ucTemp; 8094} SW_I2C_CNTL_DATA_PARAMETERS; 8095 8096#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 8097 8098typedef struct _SW_I2C_IO_DATA_PARAMETERS 8099{ 8100 USHORT GPIO_Info; 8101 UCHAR ucAct; 8102 UCHAR ucData; 8103 } SW_I2C_IO_DATA_PARAMETERS; 8104 8105#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 8106 8107/****************************SW I2C CNTL DEFINITIONS**********************/ 8108#define SW_I2C_IO_RESET 0 8109#define SW_I2C_IO_GET 1 8110#define SW_I2C_IO_DRIVE 2 8111#define SW_I2C_IO_SET 3 8112#define SW_I2C_IO_START 4 8113 8114#define SW_I2C_IO_CLOCK 0 8115#define SW_I2C_IO_DATA 0x80 8116 8117#define SW_I2C_IO_ZERO 0 8118#define SW_I2C_IO_ONE 0x100 8119 8120#define SW_I2C_CNTL_READ 0 8121#define SW_I2C_CNTL_WRITE 1 8122#define SW_I2C_CNTL_START 2 8123#define SW_I2C_CNTL_STOP 3 8124#define SW_I2C_CNTL_OPEN 4 8125#define SW_I2C_CNTL_CLOSE 5 8126#define SW_I2C_CNTL_WRITE1BIT 6 8127 8128//==============================VESA definition Portion=============================== 8129#define VESA_OEM_PRODUCT_REV '01.00' 8130#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 8131#define VESA_MODE_WIN_ATTRIBUTE 7 8132#define VESA_WIN_SIZE 64 8133 8134typedef struct _PTR_32_BIT_STRUCTURE 8135{ 8136 USHORT Offset16; 8137 USHORT Segment16; 8138} PTR_32_BIT_STRUCTURE; 8139 8140typedef union _PTR_32_BIT_UNION 8141{ 8142 PTR_32_BIT_STRUCTURE SegmentOffset; 8143 ULONG Ptr32_Bit; 8144} PTR_32_BIT_UNION; 8145 8146typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 8147{ 8148 UCHAR VbeSignature[4]; 8149 USHORT VbeVersion; 8150 PTR_32_BIT_UNION OemStringPtr; 8151 UCHAR Capabilities[4]; 8152 PTR_32_BIT_UNION VideoModePtr; 8153 USHORT TotalMemory; 8154} VBE_1_2_INFO_BLOCK_UPDATABLE; 8155 8156 8157typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 8158{ 8159 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 8160 USHORT OemSoftRev; 8161 PTR_32_BIT_UNION OemVendorNamePtr; 8162 PTR_32_BIT_UNION OemProductNamePtr; 8163 PTR_32_BIT_UNION OemProductRevPtr; 8164} VBE_2_0_INFO_BLOCK_UPDATABLE; 8165 8166typedef union _VBE_VERSION_UNION 8167{ 8168 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 8169 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 8170} VBE_VERSION_UNION; 8171 8172typedef struct _VBE_INFO_BLOCK 8173{ 8174 VBE_VERSION_UNION UpdatableVBE_Info; 8175 UCHAR Reserved[222]; 8176 UCHAR OemData[256]; 8177} VBE_INFO_BLOCK; 8178 8179typedef struct _VBE_FP_INFO 8180{ 8181 USHORT HSize; 8182 USHORT VSize; 8183 USHORT FPType; 8184 UCHAR RedBPP; 8185 UCHAR GreenBPP; 8186 UCHAR BlueBPP; 8187 UCHAR ReservedBPP; 8188 ULONG RsvdOffScrnMemSize; 8189 ULONG RsvdOffScrnMEmPtr; 8190 UCHAR Reserved[14]; 8191} VBE_FP_INFO; 8192 8193typedef struct _VESA_MODE_INFO_BLOCK 8194{ 8195// Mandatory information for all VBE revisions 8196 USHORT ModeAttributes; // dw ? ; mode attributes 8197 UCHAR WinAAttributes; // db ? ; window A attributes 8198 UCHAR WinBAttributes; // db ? ; window B attributes 8199 USHORT WinGranularity; // dw ? ; window granularity 8200 USHORT WinSize; // dw ? ; window size 8201 USHORT WinASegment; // dw ? ; window A start segment 8202 USHORT WinBSegment; // dw ? ; window B start segment 8203 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 8204 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 8205 8206//; Mandatory information for VBE 1.2 and above 8207 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 8208 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 8209 UCHAR XCharSize; // db ? ; character cell width in pixels 8210 UCHAR YCharSize; // db ? ; character cell height in pixels 8211 UCHAR NumberOfPlanes; // db ? ; number of memory planes 8212 UCHAR BitsPerPixel; // db ? ; bits per pixel 8213 UCHAR NumberOfBanks; // db ? ; number of banks 8214 UCHAR MemoryModel; // db ? ; memory model type 8215 UCHAR BankSize; // db ? ; bank size in KB 8216 UCHAR NumberOfImagePages;// db ? ; number of images 8217 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 8218 8219//; Direct Color fields(required for direct/6 and YUV/7 memory models) 8220 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 8221 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 8222 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 8223 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 8224 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 8225 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 8226 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 8227 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 8228 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 8229 8230//; Mandatory information for VBE 2.0 and above 8231 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 8232 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 8233 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 8234 8235//; Mandatory information for VBE 3.0 and above 8236 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 8237 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 8238 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 8239 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 8240 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 8241 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 8242 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 8243 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 8244 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 8245 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 8246 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 8247 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 8248 UCHAR Reserved; // db 190 dup (0) 8249} VESA_MODE_INFO_BLOCK; 8250 8251// BIOS function CALLS 8252#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 8253#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 8254#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 8255#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 8256#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 8257#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 8258#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 8259#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 8260#define ATOM_BIOS_FUNCTION_STV_STD 0x16 8261#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 8262#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 8263 8264#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 8265#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 8266#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 8267#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 8268#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 8269#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 8270#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 8271 8272#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 8273#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 8274#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 8275#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 8276#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 8277#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 8278#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 8279#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 8280#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 8281#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 8282 8283 8284#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 8285#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 8286#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 8287#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 8288#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 8289#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 8290#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 8291#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 8292 8293#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 8294#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 8295#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 8296 8297// structure used for VBIOS only 8298 8299//DispOutInfoTable 8300typedef struct _ASIC_TRANSMITTER_INFO 8301{ 8302 USHORT usTransmitterObjId; 8303 USHORT usSupportDevice; 8304 UCHAR ucTransmitterCmdTblId; 8305 UCHAR ucConfig; 8306 UCHAR ucEncoderID; //available 1st encoder ( default ) 8307 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 8308 UCHAR uc2ndEncoderID; 8309 UCHAR ucReserved; 8310}ASIC_TRANSMITTER_INFO; 8311 8312#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 8313#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 8314#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 8315#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 8316#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 8317#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 8318#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 8319#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 8320#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 8321 8322typedef struct _ASIC_ENCODER_INFO 8323{ 8324 UCHAR ucEncoderID; 8325 UCHAR ucEncoderConfig; 8326 USHORT usEncoderCmdTblId; 8327}ASIC_ENCODER_INFO; 8328 8329typedef struct _ATOM_DISP_OUT_INFO 8330{ 8331 ATOM_COMMON_TABLE_HEADER sHeader; 8332 USHORT ptrTransmitterInfo; 8333 USHORT ptrEncoderInfo; 8334 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 8335 ASIC_ENCODER_INFO asEncoderInfo[1]; 8336}ATOM_DISP_OUT_INFO; 8337 8338 8339typedef struct _ATOM_DISP_OUT_INFO_V2 8340{ 8341 ATOM_COMMON_TABLE_HEADER sHeader; 8342 USHORT ptrTransmitterInfo; 8343 USHORT ptrEncoderInfo; 8344 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 8345 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 8346 ASIC_ENCODER_INFO asEncoderInfo[1]; 8347}ATOM_DISP_OUT_INFO_V2; 8348 8349 8350typedef struct _ATOM_DISP_CLOCK_ID { 8351 UCHAR ucPpllId; 8352 UCHAR ucPpllAttribute; 8353}ATOM_DISP_CLOCK_ID; 8354 8355// ucPpllAttribute 8356#define CLOCK_SOURCE_SHAREABLE 0x01 8357#define CLOCK_SOURCE_DP_MODE 0x02 8358#define CLOCK_SOURCE_NONE_DP_MODE 0x04 8359 8360//DispOutInfoTable 8361typedef struct _ASIC_TRANSMITTER_INFO_V2 8362{ 8363 USHORT usTransmitterObjId; 8364 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 8365 UCHAR ucTransmitterCmdTblId; 8366 UCHAR ucConfig; 8367 UCHAR ucEncoderID; // available 1st encoder ( default ) 8368 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 8369 UCHAR uc2ndEncoderID; 8370 UCHAR ucReserved; 8371}ASIC_TRANSMITTER_INFO_V2; 8372 8373typedef struct _ATOM_DISP_OUT_INFO_V3 8374{ 8375 ATOM_COMMON_TABLE_HEADER sHeader; 8376 USHORT ptrTransmitterInfo; 8377 USHORT ptrEncoderInfo; 8378 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 8379 USHORT usReserved; 8380 UCHAR ucDCERevision; 8381 UCHAR ucMaxDispEngineNum; 8382 UCHAR ucMaxActiveDispEngineNum; 8383 UCHAR ucMaxPPLLNum; 8384 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 8385 UCHAR ucDispCaps; 8386 UCHAR ucReserved[2]; 8387 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 8388}ATOM_DISP_OUT_INFO_V3; 8389 8390//ucDispCaps 8391#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 8392#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 8393 8394typedef enum CORE_REF_CLK_SOURCE{ 8395 CLOCK_SRC_XTALIN=0, 8396 CLOCK_SRC_XO_IN=1, 8397 CLOCK_SRC_XO_IN2=2, 8398}CORE_REF_CLK_SOURCE; 8399 8400// DispDevicePriorityInfo 8401typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 8402{ 8403 ATOM_COMMON_TABLE_HEADER sHeader; 8404 USHORT asDevicePriority[16]; 8405}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 8406 8407//ProcessAuxChannelTransactionTable 8408typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 8409{ 8410 USHORT lpAuxRequest; 8411 USHORT lpDataOut; 8412 UCHAR ucChannelID; 8413 union 8414 { 8415 UCHAR ucReplyStatus; 8416 UCHAR ucDelay; 8417 }; 8418 UCHAR ucDataOutLen; 8419 UCHAR ucReserved; 8420}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 8421 8422//ProcessAuxChannelTransactionTable 8423typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 8424{ 8425 USHORT lpAuxRequest; 8426 USHORT lpDataOut; 8427 UCHAR ucChannelID; 8428 union 8429 { 8430 UCHAR ucReplyStatus; 8431 UCHAR ucDelay; 8432 }; 8433 UCHAR ucDataOutLen; 8434 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 8435}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 8436 8437#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 8438 8439//GetSinkType 8440 8441typedef struct _DP_ENCODER_SERVICE_PARAMETERS 8442{ 8443 USHORT ucLinkClock; 8444 union 8445 { 8446 UCHAR ucConfig; // for DP training command 8447 UCHAR ucI2cId; // use for GET_SINK_TYPE command 8448 }; 8449 UCHAR ucAction; 8450 UCHAR ucStatus; 8451 UCHAR ucLaneNum; 8452 UCHAR ucReserved[2]; 8453}DP_ENCODER_SERVICE_PARAMETERS; 8454 8455// ucAction 8456#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 8457 8458#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 8459 8460 8461typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 8462{ 8463 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 8464 UCHAR ucAuxId; 8465 UCHAR ucAction; 8466 UCHAR ucSinkType; // Iput and Output parameters. 8467 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 8468 UCHAR ucReserved[2]; 8469}DP_ENCODER_SERVICE_PARAMETERS_V2; 8470 8471typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 8472{ 8473 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 8474 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 8475}DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 8476 8477// ucAction 8478#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 8479#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 8480 8481 8482// DP_TRAINING_TABLE 8483#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 8484#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 8485#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 8486#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 8487#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 8488#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 8489#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 8490#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 8491#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 8492#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 8493#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 8494#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 8495#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 8496 8497 8498typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 8499{ 8500 UCHAR ucI2CSpeed; 8501 union 8502 { 8503 UCHAR ucRegIndex; 8504 UCHAR ucStatus; 8505 }; 8506 USHORT lpI2CDataOut; 8507 UCHAR ucFlag; 8508 UCHAR ucTransBytes; 8509 UCHAR ucSlaveAddr; 8510 UCHAR ucLineNumber; 8511}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 8512 8513#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 8514 8515//ucFlag 8516#define HW_I2C_WRITE 1 8517#define HW_I2C_READ 0 8518#define I2C_2BYTE_ADDR 0x02 8519 8520/****************************************************************************/ 8521// Structures used by HW_Misc_OperationTable 8522/****************************************************************************/ 8523typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 8524{ 8525 UCHAR ucCmd; // Input: To tell which action to take 8526 UCHAR ucReserved[3]; 8527 ULONG ulReserved; 8528}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 8529 8530typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 8531{ 8532 UCHAR ucReturnCode; // Output: Return value base on action was taken 8533 UCHAR ucReserved[3]; 8534 ULONG ulReserved; 8535}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 8536 8537// Actions code 8538#define ATOM_GET_SDI_SUPPORT 0xF0 8539 8540// Return code 8541#define ATOM_UNKNOWN_CMD 0 8542#define ATOM_FEATURE_NOT_SUPPORTED 1 8543#define ATOM_FEATURE_SUPPORTED 2 8544 8545typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 8546{ 8547 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 8548 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 8549}ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 8550 8551/****************************************************************************/ 8552 8553typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 8554{ 8555 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 8556 UCHAR ucReserved[3]; 8557}SET_HWBLOCK_INSTANCE_PARAMETER_V2; 8558 8559#define HWBLKINST_INSTANCE_MASK 0x07 8560#define HWBLKINST_HWBLK_MASK 0xF0 8561#define HWBLKINST_HWBLK_SHIFT 0x04 8562 8563//ucHWBlock 8564#define SELECT_DISP_ENGINE 0 8565#define SELECT_DISP_PLL 1 8566#define SELECT_DCIO_UNIPHY_LINK0 2 8567#define SELECT_DCIO_UNIPHY_LINK1 3 8568#define SELECT_DCIO_IMPCAL 4 8569#define SELECT_DCIO_DIG 6 8570#define SELECT_CRTC_PIXEL_RATE 7 8571#define SELECT_VGA_BLK 8 8572 8573// DIGTransmitterInfoTable structure used to program UNIPHY settings 8574typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 8575 ATOM_COMMON_TABLE_HEADER sHeader; 8576 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8577 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8578 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8579 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8580 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8581}DIG_TRANSMITTER_INFO_HEADER_V3_1; 8582 8583typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ 8584 ATOM_COMMON_TABLE_HEADER sHeader; 8585 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8586 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8587 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8588 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8589 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8590 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 8591 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 8592}DIG_TRANSMITTER_INFO_HEADER_V3_2; 8593 8594 8595typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{ 8596 ATOM_COMMON_TABLE_HEADER sHeader; 8597 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8598 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8599 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8600 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8601 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8602 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 8603 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 8604 USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock 8605 USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8606 USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8607 USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock 8608 USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8609 USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock 8610}DIG_TRANSMITTER_INFO_HEADER_V3_3; 8611 8612 8613typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 8614 USHORT usRegisterIndex; 8615 UCHAR ucStartBit; 8616 UCHAR ucEndBit; 8617}CLOCK_CONDITION_REGESTER_INFO; 8618 8619typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 8620 USHORT usMaxClockFreq; 8621 UCHAR ucEncodeMode; 8622 UCHAR ucPhySel; 8623 ULONG ulAnalogSetting[1]; 8624}CLOCK_CONDITION_SETTING_ENTRY; 8625 8626typedef struct _CLOCK_CONDITION_SETTING_INFO{ 8627 USHORT usEntrySize; 8628 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 8629}CLOCK_CONDITION_SETTING_INFO; 8630 8631typedef struct _PHY_CONDITION_REG_VAL{ 8632 ULONG ulCondition; 8633 ULONG ulRegVal; 8634}PHY_CONDITION_REG_VAL; 8635 8636typedef struct _PHY_CONDITION_REG_VAL_V2{ 8637 ULONG ulCondition; 8638 UCHAR ucCondition2; 8639 ULONG ulRegVal; 8640}PHY_CONDITION_REG_VAL_V2; 8641 8642typedef struct _PHY_CONDITION_REG_INFO{ 8643 USHORT usRegIndex; 8644 USHORT usSize; 8645 PHY_CONDITION_REG_VAL asRegVal[1]; 8646}PHY_CONDITION_REG_INFO; 8647 8648typedef struct _PHY_CONDITION_REG_INFO_V2{ 8649 USHORT usRegIndex; 8650 USHORT usSize; 8651 PHY_CONDITION_REG_VAL_V2 asRegVal[1]; 8652}PHY_CONDITION_REG_INFO_V2; 8653 8654typedef struct _PHY_ANALOG_SETTING_INFO{ 8655 UCHAR ucEncodeMode; 8656 UCHAR ucPhySel; 8657 USHORT usSize; 8658 PHY_CONDITION_REG_INFO asAnalogSetting[1]; 8659}PHY_ANALOG_SETTING_INFO; 8660 8661typedef struct _PHY_ANALOG_SETTING_INFO_V2{ 8662 UCHAR ucEncodeMode; 8663 UCHAR ucPhySel; 8664 USHORT usSize; 8665 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; 8666}PHY_ANALOG_SETTING_INFO_V2; 8667 8668 8669typedef struct _GFX_HAVESTING_PARAMETERS { 8670 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM 8671 UCHAR ucReserved; //reserved 8672 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array 8673 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array 8674} GFX_HAVESTING_PARAMETERS; 8675 8676//ucGfxBlkId 8677#define GFX_HARVESTING_CU_ID 0 8678#define GFX_HARVESTING_RB_ID 1 8679#define GFX_HARVESTING_PRIM_ID 2 8680 8681 8682typedef struct _VBIOS_ROM_HEADER{ 8683 UCHAR PciRomSignature[2]; 8684 UCHAR ucPciRomSizeIn512bytes; 8685 UCHAR ucJumpCoreMainInitBIOS; 8686 USHORT usLabelCoreMainInitBIOS; 8687 UCHAR PciReservedSpace[18]; 8688 USHORT usPciDataStructureOffset; 8689 UCHAR Rsvd1d_1a[4]; 8690 char strIbm[3]; 8691 UCHAR CheckSum[14]; 8692 UCHAR ucBiosMsgNumber; 8693 char str761295520[16]; 8694 USHORT usLabelCoreVPOSTNoMode; 8695 USHORT usSpecialPostOffset; 8696 UCHAR ucSpeicalPostImageSizeIn512Bytes; 8697 UCHAR Rsved47_45[3]; 8698 USHORT usROM_HeaderInformationTableOffset; 8699 UCHAR Rsved4f_4a[6]; 8700 char strBuildTimeStamp[20]; 8701 UCHAR ucJumpCoreXFuncFarHandler; 8702 USHORT usCoreXFuncFarHandlerOffset; 8703 UCHAR ucRsved67; 8704 UCHAR ucJumpCoreVFuncFarHandler; 8705 USHORT usCoreVFuncFarHandlerOffset; 8706 UCHAR Rsved6d_6b[3]; 8707 USHORT usATOM_BIOS_MESSAGE_Offset; 8708}VBIOS_ROM_HEADER; 8709 8710/****************************************************************************/ 8711//Portion VI: Definitinos for vbios MC scratch registers that driver used 8712/****************************************************************************/ 8713 8714#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 8715#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 8716#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 8717#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 8718#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 8719#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 8720#define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 8721#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 8722 8723#define ATOM_MEM_TYPE_DDR_STRING "DDR" 8724#define ATOM_MEM_TYPE_DDR2_STRING "DDR2" 8725#define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" 8726#define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" 8727#define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" 8728#define ATOM_MEM_TYPE_HBM_STRING "HBM" 8729#define ATOM_MEM_TYPE_DDR3_STRING "DDR3" 8730 8731/****************************************************************************/ 8732//Portion VII: Definitinos being oboselete 8733/****************************************************************************/ 8734 8735//========================================================================================== 8736//Remove the definitions below when driver is ready! 8737typedef struct _ATOM_DAC_INFO 8738{ 8739 ATOM_COMMON_TABLE_HEADER sHeader; 8740 USHORT usMaxFrequency; // in 10kHz unit 8741 USHORT usReserved; 8742}ATOM_DAC_INFO; 8743 8744 8745typedef struct _COMPASSIONATE_DATA 8746{ 8747 ATOM_COMMON_TABLE_HEADER sHeader; 8748 8749 //============================== DAC1 portion 8750 UCHAR ucDAC1_BG_Adjustment; 8751 UCHAR ucDAC1_DAC_Adjustment; 8752 USHORT usDAC1_FORCE_Data; 8753 //============================== DAC2 portion 8754 UCHAR ucDAC2_CRT2_BG_Adjustment; 8755 UCHAR ucDAC2_CRT2_DAC_Adjustment; 8756 USHORT usDAC2_CRT2_FORCE_Data; 8757 USHORT usDAC2_CRT2_MUX_RegisterIndex; 8758 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8759 UCHAR ucDAC2_NTSC_BG_Adjustment; 8760 UCHAR ucDAC2_NTSC_DAC_Adjustment; 8761 USHORT usDAC2_TV1_FORCE_Data; 8762 USHORT usDAC2_TV1_MUX_RegisterIndex; 8763 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8764 UCHAR ucDAC2_CV_BG_Adjustment; 8765 UCHAR ucDAC2_CV_DAC_Adjustment; 8766 USHORT usDAC2_CV_FORCE_Data; 8767 USHORT usDAC2_CV_MUX_RegisterIndex; 8768 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8769 UCHAR ucDAC2_PAL_BG_Adjustment; 8770 UCHAR ucDAC2_PAL_DAC_Adjustment; 8771 USHORT usDAC2_TV2_FORCE_Data; 8772}COMPASSIONATE_DATA; 8773 8774/****************************Supported Device Info Table Definitions**********************/ 8775// ucConnectInfo: 8776// [7:4] - connector type 8777// = 1 - VGA connector 8778// = 2 - DVI-I 8779// = 3 - DVI-D 8780// = 4 - DVI-A 8781// = 5 - SVIDEO 8782// = 6 - COMPOSITE 8783// = 7 - LVDS 8784// = 8 - DIGITAL LINK 8785// = 9 - SCART 8786// = 0xA - HDMI_type A 8787// = 0xB - HDMI_type B 8788// = 0xE - Special case1 (DVI+DIN) 8789// Others=TBD 8790// [3:0] - DAC Associated 8791// = 0 - no DAC 8792// = 1 - DACA 8793// = 2 - DACB 8794// = 3 - External DAC 8795// Others=TBD 8796// 8797 8798typedef struct _ATOM_CONNECTOR_INFO 8799{ 8800#if ATOM_BIG_ENDIAN 8801 UCHAR bfConnectorType:4; 8802 UCHAR bfAssociatedDAC:4; 8803#else 8804 UCHAR bfAssociatedDAC:4; 8805 UCHAR bfConnectorType:4; 8806#endif 8807}ATOM_CONNECTOR_INFO; 8808 8809typedef union _ATOM_CONNECTOR_INFO_ACCESS 8810{ 8811 ATOM_CONNECTOR_INFO sbfAccess; 8812 UCHAR ucAccess; 8813}ATOM_CONNECTOR_INFO_ACCESS; 8814 8815typedef struct _ATOM_CONNECTOR_INFO_I2C 8816{ 8817 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 8818 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 8819}ATOM_CONNECTOR_INFO_I2C; 8820 8821 8822typedef struct _ATOM_SUPPORTED_DEVICES_INFO 8823{ 8824 ATOM_COMMON_TABLE_HEADER sHeader; 8825 USHORT usDeviceSupport; 8826 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 8827}ATOM_SUPPORTED_DEVICES_INFO; 8828 8829#define NO_INT_SRC_MAPPED 0xFF 8830 8831typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 8832{ 8833 UCHAR ucIntSrcBitmap; 8834}ATOM_CONNECTOR_INC_SRC_BITMAP; 8835 8836typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 8837{ 8838 ATOM_COMMON_TABLE_HEADER sHeader; 8839 USHORT usDeviceSupport; 8840 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8841 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8842}ATOM_SUPPORTED_DEVICES_INFO_2; 8843 8844typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 8845{ 8846 ATOM_COMMON_TABLE_HEADER sHeader; 8847 USHORT usDeviceSupport; 8848 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8849 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8850}ATOM_SUPPORTED_DEVICES_INFO_2d1; 8851 8852#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 8853 8854 8855 8856typedef struct _ATOM_MISC_CONTROL_INFO 8857{ 8858 USHORT usFrequency; 8859 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 8860 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 8861 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 8862 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 8863}ATOM_MISC_CONTROL_INFO; 8864 8865 8866#define ATOM_MAX_MISC_INFO 4 8867 8868typedef struct _ATOM_TMDS_INFO 8869{ 8870 ATOM_COMMON_TABLE_HEADER sHeader; 8871 USHORT usMaxFrequency; // in 10Khz 8872 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 8873}ATOM_TMDS_INFO; 8874 8875 8876typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 8877{ 8878 UCHAR ucTVStandard; //Same as TV standards defined above, 8879 UCHAR ucPadding[1]; 8880}ATOM_ENCODER_ANALOG_ATTRIBUTE; 8881 8882typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 8883{ 8884 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 8885 UCHAR ucPadding[1]; 8886}ATOM_ENCODER_DIGITAL_ATTRIBUTE; 8887 8888typedef union _ATOM_ENCODER_ATTRIBUTE 8889{ 8890 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 8891 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 8892}ATOM_ENCODER_ATTRIBUTE; 8893 8894 8895typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 8896{ 8897 USHORT usPixelClock; 8898 USHORT usEncoderID; 8899 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 8900 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 8901 ATOM_ENCODER_ATTRIBUTE usDevAttr; 8902}DVO_ENCODER_CONTROL_PARAMETERS; 8903 8904typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 8905{ 8906 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 8907 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 8908}DVO_ENCODER_CONTROL_PS_ALLOCATION; 8909 8910 8911#define ATOM_XTMDS_ASIC_SI164_ID 1 8912#define ATOM_XTMDS_ASIC_SI178_ID 2 8913#define ATOM_XTMDS_ASIC_TFP513_ID 3 8914#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 8915#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 8916#define ATOM_XTMDS_MVPU_FPGA 0x00000004 8917 8918 8919typedef struct _ATOM_XTMDS_INFO 8920{ 8921 ATOM_COMMON_TABLE_HEADER sHeader; 8922 USHORT usSingleLinkMaxFrequency; 8923 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 8924 UCHAR ucXtransimitterID; 8925 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 8926 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 8927 // due to design. This ID is used to alert driver that the sequence is not "standard"! 8928 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 8929 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 8930}ATOM_XTMDS_INFO; 8931 8932typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 8933{ 8934 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 8935 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 8936 UCHAR ucPadding[2]; 8937}DFP_DPMS_STATUS_CHANGE_PARAMETERS; 8938 8939/****************************Legacy Power Play Table Definitions **********************/ 8940 8941//Definitions for ulPowerPlayMiscInfo 8942#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 8943#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 8944#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 8945 8946#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 8947#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 8948 8949#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 8950 8951#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 8952#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 8953#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 8954 8955#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 8956#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 8957#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 8958#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 8959#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 8960#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 8961#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 8962 8963#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 8964#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 8965#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 8966#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 8967#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 8968 8969#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 8970#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 8971 8972#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 8973#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 8974#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 8975#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 8976#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 8977#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 8978 8979#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 8980#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 8981#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 8982 8983#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 8984#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 8985#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 8986#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 8987#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 8988#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 8989#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 8990 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 8991#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 8992#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 8993#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 8994 8995//ucTableFormatRevision=1 8996//ucTableContentRevision=1 8997typedef struct _ATOM_POWERMODE_INFO 8998{ 8999 ULONG ulMiscInfo; //The power level should be arranged in ascending order 9000 ULONG ulReserved1; // must set to 0 9001 ULONG ulReserved2; // must set to 0 9002 USHORT usEngineClock; 9003 USHORT usMemoryClock; 9004 UCHAR ucVoltageDropIndex; // index to GPIO table 9005 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9006 UCHAR ucMinTemperature; 9007 UCHAR ucMaxTemperature; 9008 UCHAR ucNumPciELanes; // number of PCIE lanes 9009}ATOM_POWERMODE_INFO; 9010 9011//ucTableFormatRevision=2 9012//ucTableContentRevision=1 9013typedef struct _ATOM_POWERMODE_INFO_V2 9014{ 9015 ULONG ulMiscInfo; //The power level should be arranged in ascending order 9016 ULONG ulMiscInfo2; 9017 ULONG ulEngineClock; 9018 ULONG ulMemoryClock; 9019 UCHAR ucVoltageDropIndex; // index to GPIO table 9020 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9021 UCHAR ucMinTemperature; 9022 UCHAR ucMaxTemperature; 9023 UCHAR ucNumPciELanes; // number of PCIE lanes 9024}ATOM_POWERMODE_INFO_V2; 9025 9026//ucTableFormatRevision=2 9027//ucTableContentRevision=2 9028typedef struct _ATOM_POWERMODE_INFO_V3 9029{ 9030 ULONG ulMiscInfo; //The power level should be arranged in ascending order 9031 ULONG ulMiscInfo2; 9032 ULONG ulEngineClock; 9033 ULONG ulMemoryClock; 9034 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 9035 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9036 UCHAR ucMinTemperature; 9037 UCHAR ucMaxTemperature; 9038 UCHAR ucNumPciELanes; // number of PCIE lanes 9039 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 9040}ATOM_POWERMODE_INFO_V3; 9041 9042 9043#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 9044 9045#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 9046#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 9047 9048#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 9049#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 9050#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 9051#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 9052#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 9053#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 9054#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 9055 9056 9057typedef struct _ATOM_POWERPLAY_INFO 9058{ 9059 ATOM_COMMON_TABLE_HEADER sHeader; 9060 UCHAR ucOverdriveThermalController; 9061 UCHAR ucOverdriveI2cLine; 9062 UCHAR ucOverdriveIntBitmap; 9063 UCHAR ucOverdriveControllerAddress; 9064 UCHAR ucSizeOfPowerModeEntry; 9065 UCHAR ucNumOfPowerModeEntries; 9066 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9067}ATOM_POWERPLAY_INFO; 9068 9069typedef struct _ATOM_POWERPLAY_INFO_V2 9070{ 9071 ATOM_COMMON_TABLE_HEADER sHeader; 9072 UCHAR ucOverdriveThermalController; 9073 UCHAR ucOverdriveI2cLine; 9074 UCHAR ucOverdriveIntBitmap; 9075 UCHAR ucOverdriveControllerAddress; 9076 UCHAR ucSizeOfPowerModeEntry; 9077 UCHAR ucNumOfPowerModeEntries; 9078 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9079}ATOM_POWERPLAY_INFO_V2; 9080 9081typedef struct _ATOM_POWERPLAY_INFO_V3 9082{ 9083 ATOM_COMMON_TABLE_HEADER sHeader; 9084 UCHAR ucOverdriveThermalController; 9085 UCHAR ucOverdriveI2cLine; 9086 UCHAR ucOverdriveIntBitmap; 9087 UCHAR ucOverdriveControllerAddress; 9088 UCHAR ucSizeOfPowerModeEntry; 9089 UCHAR ucNumOfPowerModeEntries; 9090 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9091}ATOM_POWERPLAY_INFO_V3; 9092 9093 9094 9095/**************************************************************************/ 9096 9097 9098// Following definitions are for compatiblity issue in different SW components. 9099#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 9100#define Object_Info Object_Header 9101#define AdjustARB_SEQ MC_InitParameter 9102#define VRAM_GPIO_DetectionInfo VoltageObjectInfo 9103#define ASIC_VDDCI_Info ASIC_ProfilingInfo 9104#define ASIC_MVDDQ_Info MemoryTrainingInfo 9105#define SS_Info PPLL_SS_Info 9106#define ASIC_MVDDC_Info ASIC_InternalSS_Info 9107#define DispDevicePriorityInfo SaveRestoreInfo 9108#define DispOutInfo TV_VideoMode 9109 9110 9111#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 9112#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 9113 9114//New device naming, remove them when both DAL/VBIOS is ready 9115#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 9116#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 9117 9118#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 9119#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 9120 9121#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 9122#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 9123 9124#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 9125#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 9126 9127#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 9128#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 9129 9130#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 9131#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 9132 9133#define ATOM_S0_DFP1I ATOM_S0_DFP1 9134#define ATOM_S0_DFP1X ATOM_S0_DFP2 9135 9136#define ATOM_S0_DFP2I 0x00200000L 9137#define ATOM_S0_DFP2Ib2 0x20 9138 9139#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 9140#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 9141 9142#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 9143#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 9144 9145#define ATOM_S3_DFP2I_ACTIVEb1 0x02 9146 9147#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 9148#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 9149 9150#define ATOM_S3_DFP2I_ACTIVE 0x00000200L 9151 9152#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 9153#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 9154#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 9155 9156 9157#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 9158#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 9159 9160#define ATOM_S5_DOS_REQ_DFP2I 0x0200 9161#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 9162#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 9163 9164#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 9165#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 9166 9167#define TMDS1XEncoderControl DVOEncoderControl 9168#define DFP1XOutputControl DVOOutputControl 9169 9170#define ExternalDFPOutputControl DFP1XOutputControl 9171#define EnableExternalTMDS_Encoder TMDS1XEncoderControl 9172 9173#define DFP1IOutputControl TMDSAOutputControl 9174#define DFP2IOutputControl LVTMAOutputControl 9175 9176#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 9177#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 9178 9179#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 9180#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 9181 9182#define ucDac1Standard ucDacStandard 9183#define ucDac2Standard ucDacStandard 9184 9185#define TMDS1EncoderControl TMDSAEncoderControl 9186#define TMDS2EncoderControl LVTMAEncoderControl 9187 9188#define DFP1OutputControl TMDSAOutputControl 9189#define DFP2OutputControl LVTMAOutputControl 9190#define CRT1OutputControl DAC1OutputControl 9191#define CRT2OutputControl DAC2OutputControl 9192 9193//These two lines will be removed for sure in a few days, will follow up with Michael V. 9194#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 9195#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 9196 9197#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 9198#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9199#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9200#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9201#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9202 9203#define ATOM_S6_ACC_REQ_TV2 0x00400000L 9204#define ATOM_DEVICE_TV2_INDEX 0x00000006 9205#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 9206#define ATOM_S0_TV2 0x00100000L 9207#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 9208#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 9209 9210/*********************************************************************************/ 9211 9212#pragma pack() // BIOS data must use byte alignment 9213 9214#pragma pack(1) 9215 9216typedef struct _ATOM_HOLE_INFO 9217{ 9218 USHORT usOffset; // offset of the hole ( from the start of the binary ) 9219 USHORT usLength; // length of the hole ( in bytes ) 9220}ATOM_HOLE_INFO; 9221 9222typedef struct _ATOM_SERVICE_DESCRIPTION 9223{ 9224 UCHAR ucRevision; // Holes set revision 9225 UCHAR ucAlgorithm; // Hash algorithm 9226 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production ) 9227 UCHAR ucReserved; 9228 USHORT usSigOffset; // Signature offset ( from the start of the binary ) 9229 USHORT usSigLength; // Signature length 9230}ATOM_SERVICE_DESCRIPTION; 9231 9232 9233typedef struct _ATOM_SERVICE_INFO 9234{ 9235 ATOM_COMMON_TABLE_HEADER asHeader; 9236 ATOM_SERVICE_DESCRIPTION asDescr; 9237 UCHAR ucholesNo; // number of holes that follow 9238 ATOM_HOLE_INFO holes[1]; // array of hole descriptions 9239}ATOM_SERVICE_INFO; 9240 9241 9242 9243#pragma pack() // BIOS data must use byte alignment 9244 9245// 9246// AMD ACPI Table 9247// 9248#pragma pack(1) 9249 9250typedef struct { 9251 ULONG Signature; 9252 ULONG TableLength; //Length 9253 UCHAR Revision; 9254 UCHAR Checksum; 9255 UCHAR OemId[6]; 9256 UCHAR OemTableId[8]; //UINT64 OemTableId; 9257 ULONG OemRevision; 9258 ULONG CreatorId; 9259 ULONG CreatorRevision; 9260} AMD_ACPI_DESCRIPTION_HEADER; 9261/* 9262//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 9263typedef struct { 9264 UINT32 Signature; //0x0 9265 UINT32 Length; //0x4 9266 UINT8 Revision; //0x8 9267 UINT8 Checksum; //0x9 9268 UINT8 OemId[6]; //0xA 9269 UINT64 OemTableId; //0x10 9270 UINT32 OemRevision; //0x18 9271 UINT32 CreatorId; //0x1C 9272 UINT32 CreatorRevision; //0x20 9273}EFI_ACPI_DESCRIPTION_HEADER; 9274*/ 9275typedef struct { 9276 AMD_ACPI_DESCRIPTION_HEADER SHeader; 9277 UCHAR TableUUID[16]; //0x24 9278 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 9279 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 9280 ULONG Reserved[4]; //0x3C 9281}UEFI_ACPI_VFCT; 9282 9283typedef struct { 9284 ULONG PCIBus; //0x4C 9285 ULONG PCIDevice; //0x50 9286 ULONG PCIFunction; //0x54 9287 USHORT VendorID; //0x58 9288 USHORT DeviceID; //0x5A 9289 USHORT SSVID; //0x5C 9290 USHORT SSID; //0x5E 9291 ULONG Revision; //0x60 9292 ULONG ImageLength; //0x64 9293}VFCT_IMAGE_HEADER; 9294 9295 9296typedef struct { 9297 VFCT_IMAGE_HEADER VbiosHeader; 9298 UCHAR VbiosContent[1]; 9299}GOP_VBIOS_CONTENT; 9300 9301typedef struct { 9302 VFCT_IMAGE_HEADER Lib1Header; 9303 UCHAR Lib1Content[1]; 9304}GOP_LIB1_CONTENT; 9305 9306#pragma pack() 9307 9308 9309#endif /* _ATOMBIOS_H */ 9310 9311#include "pptable.h" 9312 9313