1/*
2	Copyright (c) 2002, Thomas Kurschel
3
4
5	Part of Radeon kernel driver
6
7	BIOS data structures
8*/
9
10#ifndef _RADEON_BIOS_H
11#define _RADEON_BIOS_H
12
13typedef struct {
14	uint8 clock_chip_type;
15	uint8 struct_size;
16	uint8 accelerator_entry;
17	uint8 VGA_entry;
18	uint16 VGA_table_offset;
19	uint16 POST_table_offset;
20	uint16 XCLK;
21	uint16 MCLK;
22	uint8 num_PLL_blocks;
23	uint8 size_PLL_blocks;
24	uint16 PCLK_ref_freq;
25	uint16 PCLK_ref_divider;
26	uint32 PCLK_min_freq;
27	uint32 PCLK_max_freq;
28	uint16 MCLK_ref_freq;
29	uint16 MCLK_ref_divider;
30	uint32 MCLK_min_freq;
31	uint32 MCLK_max_freq;
32	uint16 XCLK_ref_freq;
33	uint16 XCLK_ref_divider;
34	uint32 XCLK_min_freq;
35	uint32 XCLK_max_freq;
36} __attribute__ ((packed)) PLL_BLOCK;
37
38typedef struct {
39	uint8 dummy0;
40	char name[24];				// 1
41	uint16 panel_xres;			// 25
42	uint16 panel_yres;			// 27
43
44	uint8 dummy[15];
45
46	uint16 panel_pwr_delay;		// 44
47	uint16 ref_div;				// 46
48	uint8 post_div;				// 48
49	uint8 feedback_div;			// 49
50	uint8 dummy2[14];
51
52	uint16 fpi_timing_ofs[20];	// 64
53} __attribute__ ((packed)) FPI_BLOCK;
54
55typedef struct {
56	uint16 panel_xres;			// 0
57	uint16 panel_yres;			// 2
58	uint8 dummy4[5];
59
60	uint16 dot_clock;			// 9
61	uint8 dummy11[6];
62
63	uint16 h_total;				// 17
64	uint16 h_display;			// 19
65	uint16 h_sync_start;		// 21
66	uint8 h_sync_width;			// 23
67
68	uint16 v_total;				// 24
69	uint16 v_display;			// 26
70	uint16 v_sync;				// 28
71} __attribute__ ((packed)) FPI_TIMING_BLOCK;
72
73#endif
74