1/*
2	Copyright (c) 2002, Thomas Kurschel
3
4
5	Part of Radeon driver
6
7	DMA registers
8*/
9
10#ifndef _DMA_REGS_H
11#define _DMA_REGS_H
12
13typedef struct DMA_descriptor {
14	uint32	src_address;
15	uint32	dest_address;
16	uint32	command;
17	uint32	res;
18} DMA_descriptor;
19
20#define RADEON_DMA_COMMAND_EOL		(1 << 31)
21#define RADEON_DMA_COMMAND_INTDIS	(1 << 30)
22#define RADEON_DMA_COMMAND_DAIC		(1 << 29)
23#define RADEON_DMA_COMMAND_SAIC		(1 << 28)
24#define RADEON_DMA_COMMAND_DAS		(1 << 27)
25#define RADEON_DMA_COMMAND_SAS		(1 << 26)
26#define RADEON_DMA_COMMAND_DST_SWAP_SHIFT	24
27#define RADEON_DMA_COMMAND_SRC_SWAP_SHIFT	24
28#define RADEON_DMA_COMMAND_BYTE_COUNT_SHIFT	0
29
30#define	RADEON_DMA_DESC_MAX_SIZE	0x1fffff
31
32#define	RADEON_DMA_GUI_TABLE_ADDR		0x0780
33#define	RADEON_DMA_GUI_STATUS			0x0790
34#define	RADEON_DMA_STATUS_ACTIVE		(1 << 21)
35
36#define	RADEON_DMA_VID_TABLE_ADDR		0x07a0
37#define	RADEON_DMA_VID_STATUS			0x07b0
38
39#endif
40