1/******************************************************************************* 2/ 3/ File: PCI.h 4/ 5/ Description: Interface to the PCI bus. 6/ For more information, see "PCI Local Bus Specification, Revision 2.1", 7/ PCI Special Interest Group, 1995. 8/ 9/ Copyright 1993-98, Be Incorporated, All Rights Reserved. 10/ 11*******************************************************************************/ 12 13 14#ifndef _PCI_H 15#define _PCI_H 16 17//#include <BeBuild.h> 18//#include <SupportDefs.h> 19#include <bus_manager.h> 20 21#ifdef __cplusplus 22extern "C" { 23#endif 24 25 26/* ----- 27 pci device info 28----- */ 29 30typedef struct pci_info { 31 ushort vendor_id; /* vendor id */ 32 ushort device_id; /* device id */ 33 uchar bus; /* bus number */ 34 uchar device; /* device number on bus */ 35 uchar function; /* function number in device */ 36 uchar revision; /* revision id */ 37 uchar class_api; /* specific register interface type */ 38 uchar class_sub; /* specific device function */ 39 uchar class_base; /* device type (display vs network, etc) */ 40 uchar line_size; /* cache line size in 32 bit words */ 41 uchar latency; /* latency timer */ 42 uchar header_type; /* header type */ 43 uchar bist; /* built-in self-test */ 44 uchar reserved; /* filler, for alignment */ 45 union { 46 struct { 47 uint32 cardbus_cis; /* CardBus CIS pointer */ 48 ushort subsystem_id; /* subsystem (add-in card) id */ 49 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 50 uint32 rom_base; /* rom base address, viewed from host */ 51 uint32 rom_base_pci; /* rom base addr, viewed from pci */ 52 uint32 rom_size; /* rom size */ 53 uint32 base_registers[6]; /* base registers, viewed from host */ 54 uint32 base_registers_pci[6]; /* base registers, viewed from pci */ 55 uint32 base_register_sizes[6]; /* size of what base regs point to */ 56 uchar base_register_flags[6]; /* flags from base address fields */ 57 uchar interrupt_line; /* interrupt line */ 58 uchar interrupt_pin; /* interrupt pin */ 59 uchar min_grant; /* burst period @ 33 Mhz */ 60 uchar max_latency; /* how often PCI access needed */ 61 } h0; 62 struct { 63 uint32 base_registers[2]; /* base registers, viewed from host */ 64 uint32 base_registers_pci[2]; /* base registers, viewed from pci */ 65 uint32 base_register_sizes[2]; /* size of what base regs point to */ 66 uchar base_register_flags[2]; /* flags from base address fields */ 67 uchar primary_bus; 68 uchar secondary_bus; 69 uchar subordinate_bus; 70 uchar secondary_latency; 71 uchar io_base; 72 uchar io_limit; 73 ushort secondary_status; 74 ushort memory_base; 75 ushort memory_limit; 76 ushort prefetchable_memory_base; 77 ushort prefetchable_memory_limit; 78 uint32 prefetchable_memory_base_upper32; 79 uint32 prefetchable_memory_limit_upper32; 80 ushort io_base_upper16; 81 ushort io_limit_upper16; 82 uint32 rom_base; /* rom base address, viewed from host */ 83 uint32 rom_base_pci; /* rom base addr, viewed from pci */ 84 uchar interrupt_line; /* interrupt line */ 85 uchar interrupt_pin; /* interrupt pin */ 86 ushort bridge_control; 87 ushort subsystem_id; /* subsystem (add-in card) id */ 88 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 89 } h1; 90 struct { 91 ushort subsystem_id; /* subsystem (add-in card) id */ 92 ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ 93 94#ifdef __HAIKU_PCI_BUS_MANAGER_TESTING 95 // for testing only, not final (do not use!): 96 uchar primary_bus; 97 uchar secondary_bus; 98 uchar subordinate_bus; 99 uchar secondary_latency; 100 ushort reserved; 101 uint32 memory_base; 102 uint32 memory_limit; 103 uint32 memory_base_upper32; 104 uint32 memory_limit_upper32; 105 uint32 io_base; 106 uint32 io_limit; 107 uint32 io_base_upper32; 108 uint32 io_limit_upper32; 109 ushort secondary_status; 110 ushort bridge_control; 111#endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */ 112 } h2; 113 } u; 114} pci_info; 115 116 117typedef struct pci_module_info pci_module_info; 118 119struct pci_module_info { 120 bus_manager_info binfo; 121 122 uint8 (*read_io_8) (int mapped_io_addr); 123 void (*write_io_8) (int mapped_io_addr, uint8 value); 124 uint16 (*read_io_16) (int mapped_io_addr); 125 void (*write_io_16) (int mapped_io_addr, uint16 value); 126 uint32 (*read_io_32) (int mapped_io_addr); 127 void (*write_io_32) (int mapped_io_addr, uint32 value); 128 129 long (*get_nth_pci_info) ( 130 long index, /* index into pci device table */ 131 pci_info *info /* caller-supplied buffer for info */ 132 ); 133 uint32 (*read_pci_config) ( 134 uint8 bus, /* bus number */ 135 uint8 device, /* device # on bus */ 136 uint8 function, /* function # in device */ 137 uint16 offset, /* offset in configuration space */ 138 uint8 size /* # bytes to read (1, 2 or 4) */ 139 ); 140 void (*write_pci_config) ( 141 uint8 bus, /* bus number */ 142 uint8 device, /* device # on bus */ 143 uint8 function, /* function # in device */ 144 uint16 offset, /* offset in configuration space */ 145 uint8 size, /* # bytes to write (1, 2 or 4) */ 146 uint32 value /* value to write */ 147 ); 148 149 phys_addr_t (*ram_address) (phys_addr_t physical_address_in_system_memory); 150 151 status_t (*find_pci_capability) ( 152 uchar bus, 153 uchar device, 154 uchar function, 155 uchar cap_id, 156 uchar *offset 157 ); 158 159 status_t (*reserve_device) ( 160 uchar bus, 161 uchar device, 162 uchar function, 163 const char *driver_name, 164 void *cookie); 165 status_t (*unreserve_device) ( 166 uchar bus, 167 uchar device, 168 uchar function, 169 const char *driver_name, 170 void *cookie); 171 172 status_t (*update_interrupt_line) ( 173 uchar bus, 174 uchar device, 175 uchar function, 176 uchar newInterruptLineValue); 177 178 status_t (*find_pci_extended_capability) ( 179 uint8 bus, 180 uint8 device, 181 uint8 function, 182 uint16 cap_id, 183 uint16 *offset 184 ); 185 186 status_t (*get_powerstate)(uint8 bus, uint8 device, uint8 function, uint8* state); 187 status_t (*set_powerstate)(uint8 bus, uint8 device, uint8 function, uint8 newState); 188 189 uint32 (*get_msi_count)( 190 uint8 bus, /* bus number */ 191 uint8 device, /* device # on bus */ 192 uint8 function); /* function # in device */ 193 194 status_t (*configure_msi)( 195 uint8 bus, /* bus number */ 196 uint8 device, /* device # on bus */ 197 uint8 function, /* function # in device */ 198 uint32 count, /* count of vectors desired */ 199 uint32 *startVector); /* first configured vector */ 200 status_t (*unconfigure_msi)( 201 uint8 bus, /* bus number */ 202 uint8 device, /* device # on bus */ 203 uint8 function); /* function # in device */ 204 205 status_t (*enable_msi)( 206 uint8 bus, /* bus number */ 207 uint8 device, /* device # on bus */ 208 uint8 function); /* function # in device */ 209 status_t (*disable_msi)( 210 uint8 bus, /* bus number */ 211 uint8 device, /* device # on bus */ 212 uint8 function); /* function # in device */ 213 214 uint32 (*get_msix_count)( 215 uint8 bus, /* bus number */ 216 uint8 device, /* device # on bus */ 217 uint8 function); /* function # in device */ 218 219 status_t (*configure_msix)( 220 uint8 bus, /* bus number */ 221 uint8 device, /* device # on bus */ 222 uint8 function, /* function # in device */ 223 uint32 count, /* count of vectors desired */ 224 uint32 *startVector); /* first configured vector */ 225 status_t (*enable_msix)( 226 uint8 bus, /* bus number */ 227 uint8 device, /* device # on bus */ 228 uint8 function); /* function # in device */ 229}; 230 231#define B_PCI_MODULE_NAME "bus_managers/pci/v1" 232 233/* --- 234 offsets in PCI configuration space to the elements of the predefined 235 header common to all header types 236--- */ 237 238#define PCI_vendor_id 0x00 /* (2 byte) vendor id */ 239#define PCI_device_id 0x02 /* (2 byte) device id */ 240#define PCI_command 0x04 /* (2 byte) command */ 241#define PCI_status 0x06 /* (2 byte) status */ 242#define PCI_revision 0x08 /* (1 byte) revision id */ 243#define PCI_class_api 0x09 /* (1 byte) specific register interface type */ 244#define PCI_class_sub 0x0a /* (1 byte) specific device function */ 245#define PCI_class_base 0x0b /* (1 byte) device type (display vs network, etc) */ 246#define PCI_line_size 0x0c /* (1 byte) cache line size in 32 bit words */ 247#define PCI_latency 0x0d /* (1 byte) latency timer */ 248#define PCI_header_type 0x0e /* (1 byte) header type */ 249#define PCI_bist 0x0f /* (1 byte) built-in self-test */ 250 251#define PCI_extended_capability 0x100 /* (4 bytes) extended capability */ 252 253 254/* --- 255 offsets in PCI configuration space to the elements of the predefined 256 header common to header types 0x00 and 0x01 257--- */ 258#define PCI_base_registers 0x10 /* base registers (size varies) */ 259#define PCI_interrupt_line 0x3c /* (1 byte) interrupt line */ 260#define PCI_interrupt_pin 0x3d /* (1 byte) interrupt pin */ 261 262 263 264/* --- 265 offsets in PCI configuration space to the elements of header type 0x00 266--- */ 267 268#define PCI_cardbus_cis 0x28 /* (4 bytes) CardBus CIS (Card Information Structure) pointer (see PCMCIA v2.10 Spec) */ 269#define PCI_subsystem_vendor_id 0x2c /* (2 bytes) subsystem (add-in card) vendor id */ 270#define PCI_subsystem_id 0x2e /* (2 bytes) subsystem (add-in card) id */ 271#define PCI_rom_base 0x30 /* (4 bytes) expansion rom base address */ 272#define PCI_capabilities_ptr 0x34 /* (1 byte) pointer to the start of the capabilities list */ 273#define PCI_min_grant 0x3e /* (1 byte) burst period @ 33 Mhz */ 274#define PCI_max_latency 0x3f /* (1 byte) how often PCI access needed */ 275 276 277/* --- 278 offsets in PCI configuration space to the elements of header type 0x01 (PCI-to-PCI bridge) 279--- */ 280 281#define PCI_primary_bus 0x18 /* (1 byte) */ 282#define PCI_secondary_bus 0x19 /* (1 byte) */ 283#define PCI_subordinate_bus 0x1A /* (1 byte) */ 284#define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */ 285#define PCI_io_base 0x1C /* (1 byte) io base address register for 2ndry bus*/ 286#define PCI_io_limit 0x1D /* (1 byte) */ 287#define PCI_secondary_status 0x1E /* (2 bytes) */ 288#define PCI_memory_base 0x20 /* (2 bytes) */ 289#define PCI_memory_limit 0x22 /* (2 bytes) */ 290#define PCI_prefetchable_memory_base 0x24 /* (2 bytes) */ 291#define PCI_prefetchable_memory_limit 0x26 /* (2 bytes) */ 292#define PCI_prefetchable_memory_base_upper32 0x28 293#define PCI_prefetchable_memory_limit_upper32 0x2C 294#define PCI_io_base_upper16 0x30 /* (2 bytes) */ 295#define PCI_io_limit_upper16 0x32 /* (2 bytes) */ 296#define PCI_sub_vendor_id_1 0x34 /* (2 bytes) */ 297#define PCI_sub_device_id_1 0x36 /* (2 bytes) */ 298#define PCI_bridge_rom_base 0x38 299#define PCI_bridge_control 0x3E /* (2 bytes) */ 300 301 302/* PCI type 2 header offsets */ 303#define PCI_capabilities_ptr_2 0x14 /* (1 byte) */ 304#define PCI_secondary_status_2 0x16 /* (2 bytes) */ 305#define PCI_primary_bus_2 0x18 /* (1 byte) */ 306#define PCI_secondary_bus_2 0x19 /* (1 byte) */ 307#define PCI_subordinate_bus_2 0x1A /* (1 byte) */ 308#define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */ 309#define PCI_memory_base0_2 0x1C /* (4 bytes) */ 310#define PCI_memory_limit0_2 0x20 /* (4 bytes) */ 311#define PCI_memory_base1_2 0x24 /* (4 bytes) */ 312#define PCI_memory_limit1_2 0x28 /* (4 bytes) */ 313#define PCI_io_base0_2 0x2c /* (4 bytes) */ 314#define PCI_io_limit0_2 0x30 /* (4 bytes) */ 315#define PCI_io_base1_2 0x34 /* (4 bytes) */ 316#define PCI_io_limit1_2 0x38 /* (4 bytes) */ 317#define PCI_bridge_control_2 0x3E /* (2 bytes) */ 318 319#define PCI_sub_vendor_id_2 0x40 /* (2 bytes) */ 320#define PCI_sub_device_id_2 0x42 /* (2 bytes) */ 321 322#define PCI_card_interface_2 0x44 /* ?? */ 323 324/* --- 325 values for the class_base field in the common header 326--- */ 327 328#define PCI_early 0x00 /* built before class codes defined */ 329#define PCI_mass_storage 0x01 /* mass storage_controller */ 330#define PCI_network 0x02 /* network controller */ 331#define PCI_display 0x03 /* display controller */ 332#define PCI_multimedia 0x04 /* multimedia device */ 333#define PCI_memory 0x05 /* memory controller */ 334#define PCI_bridge 0x06 /* bridge controller */ 335#define PCI_simple_communications 0x07 /* simple communications controller */ 336#define PCI_base_peripheral 0x08 /* base system peripherals */ 337#define PCI_input 0x09 /* input devices */ 338#define PCI_docking_station 0x0a /* docking stations */ 339#define PCI_processor 0x0b /* processors */ 340#define PCI_serial_bus 0x0c /* serial bus controllers */ 341#define PCI_wireless 0x0d /* wireless controllers */ 342#define PCI_intelligent_io 0x0e 343#define PCI_satellite_communications 0x0f 344#define PCI_encryption_decryption 0x10 345#define PCI_data_acquisition 0x11 /* data acquisition and 346 signal processing controllers */ 347#define PCI_processing_accelerator 0x12 /* processing accelerators */ 348#define PCI_nonessential_function 0x13 /* non-essential instrumentation 349 function */ 350 351#define PCI_undefined 0xFF /* not in any defined class */ 352 353 354/* --- 355 values for the class_sub field for class_base = 0x00 (built before 356 class codes were defined) 357--- */ 358 359#define PCI_early_not_vga 0x00 /* all except vga */ 360#define PCI_early_vga 0x01 /* vga devices */ 361 362 363/* --- 364 values for the class_sub field for class_base = 0x01 (mass storage) 365--- */ 366 367#define PCI_scsi 0x00 /* SCSI controller */ 368#define PCI_ide 0x01 /* IDE controller */ 369#define PCI_floppy 0x02 /* floppy disk controller */ 370#define PCI_ipi 0x03 /* IPI bus controller */ 371#define PCI_raid 0x04 /* RAID controller */ 372#define PCI_ata 0x05 /* ATA controller with ADMA interface */ 373#define PCI_sata 0x06 /* Serial ATA controller */ 374#define PCI_sas 0x07 /* Serial Attached SCSI controller */ 375#define PCI_nvm 0x08 /* NVM Express controller */ 376#define PCI_ufs 0x09 /* Universal Flash Storage controller */ 377#define PCI_mass_storage_other 0x80 /* other mass storage controller */ 378 379/* --- 380 bit mask of the class_api field for 381 class_base = 0x01 (mass storage) 382 class_sub = 0x01 (IDE controller) 383--- */ 384 385#define PCI_ide_primary_native 0x01 /* primary channel is in native mode */ 386#define PCI_ide_primary_fixed 0x02 /* primary channel can be switched to native mode */ 387#define PCI_ide_secondary_native 0x04 /* secondary channel is in native mode */ 388#define PCI_ide_secondary_fixed 0x08 /* secondary channel can be switched to native mode */ 389#define PCI_ide_master 0x80 /* master device */ 390 391/* --- 392 values of the class_api field for 393 class_base = 0x01 (mass storage) 394 class_sub = 0x06 (Serial ATA controller) 395--- */ 396 397#define PCI_sata_other 0x00 /* vendor specific interface */ 398#define PCI_sata_ahci 0x01 /* AHCI interface */ 399 400/* --- 401 values of the class_api field for 402 class_base = 0x01 (mass storage) 403 class_sub = 0x08 (NVM Express controller) 404--- */ 405 406#define PCI_nvm_other 0x00 /* vendor specific interface */ 407#define PCI_nvm_hci 0x01 /* NVMHCI interface 1.0 */ 408#define PCI_nvm_hci_enterprise 0x02 /* NVMHCI enterprise */ 409 410/* --- 411 values of the class_api field for 412 class_base = 0x01 (mass storage) 413 class_sub = 0x09 (Universal Flash Storage controller) 414--- */ 415 416#define PCI_ufs_other 0x00 /* vendor specific interface */ 417#define PCI_ufs_hci 0x01 /* UFSHCI interface */ 418 419/* --- 420 values for the class_sub field for class_base = 0x02 (network) 421--- */ 422 423#define PCI_ethernet 0x00 /* Ethernet controller */ 424#define PCI_token_ring 0x01 /* Token Ring controller */ 425#define PCI_fddi 0x02 /* FDDI controller */ 426#define PCI_atm 0x03 /* ATM controller */ 427#define PCI_isdn 0x04 /* ISDN controller */ 428#define PCI_worldfip 0x05 /* WorldFip controller */ 429#define PCI_picmg 0x06 /* PICMG controller */ 430#define PCI_network_infiniband 0x07 /* InfiniBand controller */ 431#define PCI_hfc 0x08 /* Host fabric controller */ 432#define PCI_network_other 0x80 /* other network controller */ 433 434 435/* --- 436 values for the class_sub field for class_base = 0x03 (display) 437--- */ 438 439#define PCI_vga 0x00 /* VGA controller */ 440#define PCI_xga 0x01 /* XGA controller */ 441#define PCI_3d 0x02 /* 3d controller */ 442#define PCI_display_other 0x80 /* other display controller */ 443 444 445/* --- 446 values for the class_sub field for class_base = 0x04 (multimedia device) 447--- */ 448 449#define PCI_video 0x00 /* video */ 450#define PCI_audio 0x01 /* audio */ 451#define PCI_telephony 0x02 /* computer telephony device */ 452#define PCI_hd_audio 0x03 /* HD audio */ 453#define PCI_multimedia_other 0x80 /* other multimedia device */ 454 455 456/* --- 457 values of the class_api field for 458 class_base = 0x04 (multimedia device) 459 class_sub = 0x03 (HD audio) 460--- */ 461 462#define PCI_hd_audio_vendor 0x80 /* with additional vendor specific extensions */ 463 464/* --- 465 values for the class_sub field for class_base = 0x05 (memory) 466--- */ 467 468#define PCI_ram 0x00 /* RAM */ 469#define PCI_flash 0x01 /* flash */ 470#define PCI_memory_other 0x80 /* other memory controller */ 471 472 473/* --- 474 values for the class_sub field for class_base = 0x06 (bridge) 475--- */ 476 477#define PCI_host 0x00 /* host bridge */ 478#define PCI_isa 0x01 /* ISA bridge */ 479#define PCI_eisa 0x02 /* EISA bridge */ 480#define PCI_microchannel 0x03 /* MicroChannel bridge */ 481#define PCI_pci 0x04 /* PCI-to-PCI bridge */ 482#define PCI_pcmcia 0x05 /* PCMCIA bridge */ 483#define PCI_nubus 0x06 /* NuBus bridge */ 484#define PCI_cardbus 0x07 /* CardBus bridge */ 485#define PCI_raceway 0x08 /* RACEway bridge */ 486#define PCI_bridge_transparent 0x09 /* PCI transparent */ 487#define PCI_bridge_infiniband 0x0a /* Infiniband */ 488#define PCI_bridge_as_pci 0x0b /* Advanced Switching to PCI host bridge */ 489#define PCI_bridge_other 0x80 /* other bridge device */ 490 491/* --- 492 values of the class_api field for 493 class_base = 0x06 (bridge), and 494 class_sub = 0x0b (Advanced Switching to PCI host bridge) 495--- */ 496 497#define PCI_bridge_as_pci_asi_sig 0x01 /* ASI-SIG Defined Portal Interface */ 498 499/* --- 500 values for the class_sub field for class_base = 0x07 (simple 501 communications controllers) 502--- */ 503 504#define PCI_serial 0x00 /* serial port controller */ 505#define PCI_parallel 0x01 /* parallel port */ 506#define PCI_multiport_serial 0x02 /* multiport serial controller */ 507#define PCI_modem 0x03 /* modem */ 508#define PCI_gpib 0x04 /* GPIB controller */ 509#define PCI_smart_card 0x05 /* Smard Card controller */ 510#define PCI_simple_communications_other 0x80 /* other communications device */ 511 512/* --- 513 values of the class_api field for 514 class_base = 0x07 (simple communications), and 515 class_sub = 0x00 (serial port controller) 516--- */ 517 518#define PCI_serial_xt 0x00 /* XT-compatible serial controller */ 519#define PCI_serial_16450 0x01 /* 16450-compatible serial controller */ 520#define PCI_serial_16550 0x02 /* 16550-compatible serial controller */ 521 522 523/* --- 524 values of the class_api field for 525 class_base = 0x07 (simple communications), and 526 class_sub = 0x01 (parallel port) 527--- */ 528 529#define PCI_parallel_simple 0x00 /* simple (output-only) parallel port */ 530#define PCI_parallel_bidirectional 0x01 /* bidirectional parallel port */ 531#define PCI_parallel_ecp 0x02 /* ECP 1.x compliant parallel port */ 532 533 534/* --- 535 values for the class_sub field for class_base = 0x08 (generic 536 system peripherals) 537--- */ 538 539#define PCI_pic 0x00 /* peripheral interrupt controller */ 540#define PCI_dma 0x01 /* dma controller */ 541#define PCI_timer 0x02 /* timers */ 542#define PCI_rtc 0x03 /* real time clock */ 543#define PCI_generic_hot_plug 0x04 /* generic PCI hot-plug controller */ 544#define PCI_sd_host 0x05 /* SD Host controller */ 545#define PCI_iommu 0x06 /* IOMMU */ 546#define PCI_rcec 0x07 /* Root Complex Event Collector */ 547#define PCI_system_peripheral_other 0x80 /* other generic system peripheral */ 548 549/* --- 550 values of the class_api field for 551 class_base = 0x08 (generic system peripherals) 552 class_sub = 0x00 (peripheral interrupt controller) 553--- */ 554 555#define PCI_pic_8259 0x00 /* generic 8259 */ 556#define PCI_pic_isa 0x01 /* ISA pic */ 557#define PCI_pic_eisa 0x02 /* EISA pic */ 558 559/* --- 560 values of the class_api field for 561 class_base = 0x08 (generic system peripherals) 562 class_sub = 0x01 (dma controller) 563--- */ 564 565#define PCI_dma_8237 0x00 /* generic 8237 */ 566#define PCI_dma_isa 0x01 /* ISA dma */ 567#define PCI_dma_eisa 0x02 /* EISA dma */ 568 569/* --- 570 values of the class_api field for 571 class_base = 0x08 (generic system peripherals) 572 class_sub = 0x02 (timer) 573--- */ 574 575#define PCI_timer_8254 0x00 /* generic 8254 */ 576#define PCI_timer_isa 0x01 /* ISA timer */ 577#define PCI_timer_eisa 0x02 /* EISA timers (2 timers) */ 578 579 580/* --- 581 values of the class_api field for 582 class_base = 0x08 (generic system peripherals) 583 class_sub = 0x03 (real time clock 584--- */ 585 586#define PCI_rtc_generic 0x00 /* generic real time clock */ 587#define PCI_rtc_isa 0x01 /* ISA real time clock */ 588 589 590/* --- 591 values for the class_sub field for class_base = 0x09 (input devices) 592--- */ 593 594#define PCI_keyboard 0x00 /* keyboard controller */ 595#define PCI_pen 0x01 /* pen */ 596#define PCI_mouse 0x02 /* mouse controller */ 597#define PCI_scanner 0x03 /* scanner controller */ 598#define PCI_gameport 0x04 /* gameport controller */ 599#define PCI_input_other 0x80 /* other input controller */ 600 601 602/* --- 603 values for the class_sub field for class_base = 0x0a (docking stations) 604--- */ 605 606#define PCI_docking_generic 0x00 /* generic docking station */ 607#define PCI_docking_other 0x80 /* other docking stations */ 608 609/* --- 610 values for the class_sub field for class_base = 0x0b (processor) 611--- */ 612 613#define PCI_386 0x00 /* 386 */ 614#define PCI_486 0x01 /* 486 */ 615#define PCI_pentium 0x02 /* Pentium */ 616#define PCI_alpha 0x10 /* Alpha */ 617#define PCI_PowerPC 0x20 /* PowerPC */ 618#define PCI_mips 0x30 /* MIPS */ 619#define PCI_coprocessor 0x40 /* co-processor */ 620 621/* --- 622 values for the class_sub field for class_base = 0x0c (serial bus 623 controller) 624--- */ 625 626#define PCI_firewire 0x00 /* FireWire (IEEE 1394) */ 627#define PCI_access 0x01 /* ACCESS bus */ 628#define PCI_ssa 0x02 /* SSA */ 629#define PCI_usb 0x03 /* Universal Serial Bus */ 630#define PCI_fibre_channel 0x04 /* Fibre channel */ 631#define PCI_smbus 0x05 632#define PCI_infiniband 0x06 633#define PCI_ipmi 0x07 634#define PCI_sercos 0x08 635#define PCI_canbus 0x09 636#define PCI_mipi_i3c 0x0a /* MIPI I3C Host Controller Interface */ 637 638/* --- 639 values of the class_api field for 640 class_base = 0x0c ( serial bus controller ) 641 class_sub = 0x03 ( Universal Serial Bus ) 642--- */ 643 644#define PCI_usb_uhci 0x00 /* Universal Host Controller Interface */ 645#define PCI_usb_ohci 0x10 /* Open Host Controller Interface */ 646#define PCI_usb_ehci 0x20 /* Enhanced Host Controller Interface */ 647#define PCI_usb_xhci 0x30 /* Extensible Host Controller Interface */ 648#define PCI_usb_usb4 0x40 /* USB4 Host Interface */ 649 650/* --- 651 values for the class_sub field for class_base = 0x0d (wireless controller) 652--- */ 653#define PCI_wireless_irda 0x00 654#define PCI_wireless_consumer_ir 0x01 655#define PCI_wireless_rf 0x10 656#define PCI_wireless_bluetooth 0x11 657#define PCI_wireless_broadband 0x12 658#define PCI_wireless_80211A 0x20 659#define PCI_wireless_80211B 0x21 660#define PCI_wireless_cellular 0x40 661#define PCI_wireless_cellular_ethernet 0x41 662#define PCI_wireless_other 0x80 663 664/* --- 665 values for the class_sub field for class_base = 0x10 (encryption decryption) 666--- */ 667#define PCI_encryption_decryption_network_computing 0x00 668#define PCI_encryption_decryption_entertainment 0x10 669#define PCI_encryption_decryption_other 0x80 670 671/* --- 672 values for the class_sub field for class_base = 0x11 (data acquisition) 673--- */ 674#define PCI_data_acquisition_dpio 0x00 675#define PCI_data_acquisition_performance_counters 0x01 676#define PCI_data_acquisition_communication_synchroniser 0x10 677#define PCI_data_acquisition_management 0x20 678#define PCI_data_acquisition_other 0x80 679 680/* --- 681 masks for command register bits 682--- */ 683 684#define PCI_command_io 0x001 /* 1/0 i/o space en/disabled */ 685#define PCI_command_memory 0x002 /* 1/0 memory space en/disabled */ 686#define PCI_command_master 0x004 /* 1/0 pci master en/disabled */ 687#define PCI_command_special 0x008 /* 1/0 pci special cycles en/disabled */ 688#define PCI_command_mwi 0x010 /* 1/0 memory write & invalidate en/disabled */ 689#define PCI_command_vga_snoop 0x020 /* 1/0 vga pallette snoop en/disabled */ 690#define PCI_command_parity 0x040 /* 1/0 parity check en/disabled */ 691#define PCI_command_address_step 0x080 /* 1/0 address stepping en/disabled */ 692#define PCI_command_serr 0x100 /* 1/0 SERR# en/disabled */ 693#define PCI_command_fastback 0x200 /* 1/0 fast back-to-back en/disabled */ 694#define PCI_command_int_disable 0x400 /* 1/0 interrupt generation dis/enabled */ 695 696 697/* --- 698 masks for status register bits 699--- */ 700 701#define PCI_status_capabilities 0x0010 /* capabilities list */ 702#define PCI_status_66_MHz_capable 0x0020 /* 66 Mhz capable */ 703#define PCI_status_udf_supported 0x0040 /* user-definable-features (udf) supported */ 704#define PCI_status_fastback 0x0080 /* fast back-to-back capable */ 705#define PCI_status_parity_signalled 0x0100 /* parity error signalled */ 706#define PCI_status_devsel 0x0600 /* devsel timing (see below) */ 707#define PCI_status_target_abort_signalled 0x0800 /* signaled a target abort */ 708#define PCI_status_target_abort_received 0x1000 /* received a target abort */ 709#define PCI_status_master_abort_received 0x2000 /* received a master abort */ 710#define PCI_status_serr_signalled 0x4000 /* signalled SERR# */ 711#define PCI_status_parity_error_detected 0x8000 /* parity error detected */ 712 713 714/* --- 715 masks for devsel field in status register 716--- */ 717 718#define PCI_status_devsel_fast 0x0000 /* fast */ 719#define PCI_status_devsel_medium 0x0200 /* medium */ 720#define PCI_status_devsel_slow 0x0400 /* slow */ 721 722 723/* --- 724 masks for header type register 725--- */ 726 727#define PCI_header_type_mask 0x7F /* header type field */ 728#define PCI_multifunction 0x80 /* multifunction device flag */ 729 730 731/** types of PCI header */ 732 733#define PCI_header_type_generic 0x00 734#define PCI_header_type_PCI_to_PCI_bridge 0x01 735#define PCI_header_type_cardbus 0x02 736 737 738/* --- 739 masks for built in self test (bist) register bits 740--- */ 741 742#define PCI_bist_code 0x0F /* self-test completion code, 0 = success */ 743#define PCI_bist_start 0x40 /* 1 = start self-test */ 744#define PCI_bist_capable 0x80 /* 1 = self-test capable */ 745 746 747/** masks for flags in the various base address registers */ 748 749#define PCI_address_space 0x01 /* 0 = memory space, 1 = i/o space */ 750#define PCI_register_start 0x10 751#define PCI_register_end 0x24 752#define PCI_register_ppb_end 0x18 753#define PCI_register_pcb_end 0x14 754 755/** masks for flags in memory space base address registers */ 756 757#define PCI_address_type_32 0x00 /* locate anywhere in 32 bit space */ 758#define PCI_address_type_32_low 0x02 /* locate below 1 Meg */ 759#define PCI_address_type_64 0x04 /* locate anywhere in 64 bit space */ 760#define PCI_address_type 0x06 /* type (see below) */ 761#define PCI_address_prefetchable 0x08 /* 1 if prefetchable (see PCI spec) */ 762 763#define PCI_address_memory_32_mask 0xFFFFFFF0 /* mask to get 32bit memory space base address */ 764 765 766/* --- 767 masks for flags in i/o space base address registers 768--- */ 769 770#define PCI_address_io_mask 0xFFFFFFFC /* mask to get i/o space base address */ 771 772#define PCI_range_memory_mask 0xFFFFFFF0 /* mask to get memory ranges */ 773 774 775/* --- 776 masks for flags in expansion rom base address registers 777--- */ 778 779#define PCI_rom_enable 0x00000001 /* 1 expansion rom decode enabled */ 780#define PCI_rom_shadow 0x00000010 /* 2 rom copied at shadow (C0000) */ 781#define PCI_rom_copy 0x00000100 /* 4 rom is allocated copy */ 782#define PCI_rom_bios 0x00001000 /* 8 rom is bios copy */ 783#define PCI_rom_address_mask 0xFFFFF800 /* mask to get expansion rom addr */ 784 785/** PCI interrupt pin values */ 786#define PCI_pin_mask 0x07 787#define PCI_pin_none 0x00 788#define PCI_pin_a 0x01 789#define PCI_pin_b 0x02 790#define PCI_pin_c 0x03 791#define PCI_pin_d 0x04 792#define PCI_pin_max 0x04 793 794/** PCI bridge control register bits */ 795#define PCI_bridge_parity_error_response 0x0001 /* 1/0 Parity Error Response */ 796#define PCI_bridge_serr 0x0002 /* 1/0 SERR# en/disabled */ 797#define PCI_bridge_isa 0x0004 /* 1/0 ISA en/disabled */ 798#define PCI_bridge_vga 0x0008 /* 1/0 VGA en/disabled */ 799#define PCI_bridge_master_abort 0x0020 /* 1/0 Master Abort mode */ 800#define PCI_bridge_secondary_bus_reset 0x0040 /* 1/0 Secondary bus reset */ 801#define PCI_bridge_secondary_bus_fastback 0x0080 /* 1/0 fast back-to-back en/disabled */ 802#define PCI_bridge_primary_discard_timeout 0x0100 /* 1/0 primary discard timeout */ 803#define PCI_bridge_secondary_discard_timeout 0x0200 /* 1/0 secondary discard timeout */ 804#define PCI_bridge_discard_timer_status 0x0400 /* 1/0 discard timer status */ 805#define PCI_bridge_discard_timer_serr 0x0800 /* 1/0 discard timer serr */ 806 807/** PCI Capability Codes */ 808#define PCI_cap_id_reserved 0x00 809#define PCI_cap_id_pm 0x01 /* Power management */ 810#define PCI_cap_id_agp 0x02 /* AGP */ 811#define PCI_cap_id_vpd 0x03 /* Vital product data */ 812#define PCI_cap_id_slotid 0x04 /* Slot ID */ 813#define PCI_cap_id_msi 0x05 /* Message signalled interrupt */ 814#define PCI_cap_id_chswp 0x06 /* Compact PCI HotSwap */ 815#define PCI_cap_id_pcix 0x07 /* PCI-X */ 816#define PCI_cap_id_ht 0x08 /* HyperTransport */ 817#define PCI_cap_id_vendspec 0x09 818#define PCI_cap_id_debugport 0x0a 819#define PCI_cap_id_cpci_rsrcctl 0x0b 820#define PCI_cap_id_hotplug 0x0c 821#define PCI_cap_id_subvendor 0x0d 822#define PCI_cap_id_agp8x 0x0e 823#define PCI_cap_id_secure_dev 0x0f 824#define PCI_cap_id_pcie 0x10 /* PCIe (PCI express) */ 825#define PCI_cap_id_msix 0x11 /* MSI-X */ 826#define PCI_cap_id_sata 0x12 /* Serial ATA Capability */ 827#define PCI_cap_id_pciaf 0x13 /* PCI Advanced Features */ 828#define PCI_cap_id_ea 0x14 /* Extended Allocation */ 829#define PCI_cap_id_fpb 0x15 /* Flattening Portal Bridge */ 830 831/** PCI Extended Capabilities */ 832#define PCI_extcap_id(x) (x & 0x0000ffff) 833#define PCI_extcap_version(x) ((x & 0x000f0000) >> 16) 834#define PCI_extcap_next_ptr(x) ((x & 0xfff00000) >> 20) 835 836#define PCI_extcap_id_aer 0x0001 /* Advanced Error Reporting */ 837#define PCI_extcap_id_vc 0x0002 /* Virtual Channel */ 838#define PCI_extcap_id_serial 0x0003 /* Serial Number */ 839#define PCI_extcap_id_power_budget 0x0004 /* Power Budgeting */ 840#define PCI_extcap_id_rcl_decl 0x0005 /* Root Complex Link Declaration */ 841#define PCI_extcap_id_rcil_ctl 0x0006 /* Root Complex Internal Link Control */ 842#define PCI_extcap_id_rcec_assoc 0x0007 /* Root Complex Event Collector Association */ 843#define PCI_extcap_id_mfvc 0x0008 /* MultiFunction Virtual Channel */ 844#define PCI_extcap_id_vc2 0x0009 /* Virtual Channel 2 */ 845#define PCI_extcap_id_rcrb_header 0x000a /* RCRB Header */ 846#define PCI_extcap_id_vendor 0x000b /* Vendor Unique */ 847#define PCI_extcap_id_acs 0x000d /* Access Control Services */ 848#define PCI_extcap_id_ari 0x000e /* Alternative Routing Id Interpretation */ 849#define PCI_extcap_id_ats 0x000f /* Address Translation Services */ 850#define PCI_extcap_id_srio_virtual 0x0010 /* Single Root I/O Virtualization */ 851#define PCI_extcap_id_mrio_virtual 0x0011 /* Multiple Root I/O Virtual */ 852#define PCI_extcap_id_multicast 0x0012 /* Multicast */ 853#define PCI_extcap_id_page_request 0x0013 /* Page Request */ 854#define PCI_extcap_id_amd 0x0014 /* AMD Reserved */ 855#define PCI_extcap_id_resizable_bar 0x0015 /* Resizable Bar */ 856#define PCI_extcap_id_dyn_power_alloc 0x0016 /* Dynamic Power Allocation */ 857#define PCI_extcap_id_tph_requester 0x0017 /* TPH Requester */ 858#define PCI_extcap_id_latency_tolerance 0x0018 /* Latency Tolerance Reporting */ 859#define PCI_extcap_id_2ndpcie 0x0019 /* Secondary PCIe */ 860#define PCI_extcap_id_pmux 0x001a /* Protocol Multiplexing */ 861#define PCI_extcap_id_pasid 0x001b /* Process Address Space Id */ 862#define PCI_extcap_id_ln_requester 0x001c /* LN Requester */ 863#define PCI_extcap_id_dpc 0x001d /* Downstream Porto Containment */ 864#define PCI_extcap_id_l1pm 0x001e /* L1 Power Management Substates */ 865#define PCI_extcap_id_ptm 0x001f /* Precision Time Measurement */ 866#define PCI_extcap_id_m_pcie 0x0020 /* PCIe over M-PHY */ 867#define PCI_extcap_id_frs 0x0021 /* FRS Queuing */ 868#define PCI_extcap_id_rtr 0x0022 /* Readiness Time Reporting */ 869#define PCI_extcap_id_dvsec 0x0023 /* Designated Vendor-Specific */ 870#define PCI_extcap_id_vf_resizable_bar 0x0024 /* VF Resizable BAR */ 871#define PCI_extcap_id_datalink 0x0025 /* Data Link Feature */ 872#define PCI_extcap_id_16gt 0x0026 /* Physical Layer 16.0 GT/s */ 873#define PCI_extcap_id_lmr 0x0027 /* Lane Marging at the Receiver */ 874#define PCI_extcap_id_hierarchy_id 0x0028 /* Hierarchy ID */ 875#define PCI_extcap_id_npem 0x0029 /* Native PCIe Enclosure Management */ 876#define PCI_extcap_id_pl32 0x002a /* Physical Layer 32.0 GT/s */ 877#define PCI_extcap_id_ap 0x002b /* Alternate Protocol */ 878#define PCI_extcap_id_sfi 0x002c /* System Firmware Intermediary */ 879#define PCI_extcap_id_sf 0x002d /* Shadow Functions */ 880#define PCI_extcap_id_doe 0x002e /* Data Object Exchange */ 881 882/** Power Management Control Status Register settings */ 883#define PCI_pm_mask 0x03 884#define PCI_pm_ctrl 0x02 885#define PCI_pm_d1supp 0x0200 886#define PCI_pm_d2supp 0x0400 887#define PCI_pm_status 0x04 888#define PCI_pm_state_d0 0x00 889#define PCI_pm_state_d1 0x01 890#define PCI_pm_state_d2 0x02 891#define PCI_pm_state_d3 0x03 892 893/** MSI registers **/ 894#define PCI_msi_control 0x02 895#define PCI_msi_address 0x04 896#define PCI_msi_address_high 0x08 897#define PCI_msi_data 0x08 898#define PCI_msi_data_64bit 0x0c 899#define PCI_msi_mask 0x10 900#define PCI_msi_pending 0x14 901 902/** MSI control register values **/ 903#define PCI_msi_control_enable 0x0001 904#define PCI_msi_control_vector 0x0100 905#define PCI_msi_control_64bit 0x0080 906#define PCI_msi_control_mme_mask 0x0070 907#define PCI_msi_control_mme_1 0x0000 908#define PCI_msi_control_mme_2 0x0010 909#define PCI_msi_control_mme_4 0x0020 910#define PCI_msi_control_mme_8 0x0030 911#define PCI_msi_control_mme_16 0x0040 912#define PCI_msi_control_mme_32 0x0050 913#define PCI_msi_control_mmc_mask 0x000e 914#define PCI_msi_control_mmc_1 0x0000 915#define PCI_msi_control_mmc_2 0x0002 916#define PCI_msi_control_mmc_4 0x0004 917#define PCI_msi_control_mmc_8 0x0006 918#define PCI_msi_control_mmc_16 0x0008 919#define PCI_msi_control_mmc_32 0x000a 920 921/** MSI-X registers **/ 922#define PCI_msix_control 0x02 923#define PCI_msix_table 0x04 924#define PCI_msix_pba 0x08 925 926#define PCI_msix_control_table_size 0x07ff 927#define PCI_msix_control_function_mask 0x4000 928#define PCI_msix_control_enable 0x8000 929#define PCI_msix_bir_mask 0x0007 930#define PCI_msix_bir_0 0x10 931#define PCI_msix_bir_1 0x14 932#define PCI_msix_bir_2 0x18 933#define PCI_msix_bir_3 0x1c 934#define PCI_msix_bir_4 0x20 935#define PCI_msix_bir_5 0x24 936#define PCI_msix_offset_mask 0xfff8 937 938#define PCI_msix_vctrl_mask 0x0001 939 940/** HyperTransport registers **/ 941#define PCI_ht_command 0x02 942#define PCI_ht_msi_address_low 0x04 943#define PCI_ht_msi_address_high 0x08 944 945#define PCI_ht_command_cap_mask_3_bits 0xe000 946#define PCI_ht_command_cap_mask_5_bits 0xf800 947#define PCI_ht_command_cap_slave 0x0000 948#define PCI_ht_command_cap_host 0x2000 949#define PCI_ht_command_cap_switch 0x4000 950#define PCI_ht_command_cap_interrupt 0x8000 951#define PCI_ht_command_cap_revision_id 0x8800 952#define PCI_ht_command_cap_unit_id_clumping 0x9000 953#define PCI_ht_command_cap_ext_config_space 0x9800 954#define PCI_ht_command_cap_address_mapping 0xa000 955#define PCI_ht_command_cap_msi_mapping 0xa800 956#define PCI_ht_command_cap_direct_route 0xb000 957#define PCI_ht_command_cap_vcset 0xb800 958#define PCI_ht_command_cap_retry_mode 0xc000 959#define PCI_ht_command_cap_x86_encoding 0xc800 960#define PCI_ht_command_cap_gen3 0xd000 961#define PCI_ht_command_cap_fle 0xd800 962#define PCI_ht_command_cap_pm 0xe000 963#define PCI_ht_command_cap_high_node_count 0xe800 964 965#define PCI_ht_command_msi_enable 0x0001 966#define PCI_ht_command_msi_fixed 0x0002 967 968#ifdef __cplusplus 969} 970#endif 971 972#endif /* _PCI_H */ 973