1/* longlong.h -- definitions for mixed size 32/64 bit arithmetic. 2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000 3 Free Software Foundation, Inc. 4 5 This file is part of the GNU C Library. 6 7 The GNU C Library is free software; you can redistribute it and/or 8 modify it under the terms of the GNU Lesser General Public 9 License as published by the Free Software Foundation; either 10 version 2.1 of the License, or (at your option) any later version. 11 12 The GNU C Library is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 Lesser General Public License for more details. 16 17 You should have received a copy of the GNU Lesser General Public 18 License along with the GNU C Library; if not, write to the Free 19 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 20 02111-1307 USA. */ 21 22/* You have to define the following before including this file: 23 24 UWtype -- An unsigned type, default type for operations (typically a "word") 25 UHWtype -- An unsigned type, at least half the size of UWtype. 26 UDWtype -- An unsigned type, at least twice as large a UWtype 27 W_TYPE_SIZE -- size in bits of UWtype 28 29 UQItype -- Unsigned 8 bit type. 30 SItype, USItype -- Signed and unsigned 32 bit types. 31 DItype, UDItype -- Signed and unsigned 64 bit types. 32 33 On a 32 bit machine UWtype should typically be USItype; 34 on a 64 bit machine, UWtype should typically be UDItype. 35*/ 36 37#define __BITS4 (W_TYPE_SIZE / 4) 38#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2)) 39#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1)) 40#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2)) 41 42#ifndef W_TYPE_SIZE 43#define W_TYPE_SIZE 32 44#define UWtype USItype 45#define UHWtype USItype 46#define UDWtype UDItype 47#endif 48 49/* Define auxiliary asm macros. 50 51 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two 52 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype 53 word product in HIGH_PROD and LOW_PROD. 54 55 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a 56 UDWtype product. This is just a variant of umul_ppmm. 57 58 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, 59 denominator) divides a UDWtype, composed by the UWtype integers 60 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient 61 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less 62 than DENOMINATOR for correct operation. If, in addition, the most 63 significant bit of DENOMINATOR must be 1, then the pre-processor symbol 64 UDIV_NEEDS_NORMALIZATION is defined to 1. 65 66 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, 67 denominator). Like udiv_qrnnd but the numbers are signed. The quotient 68 is rounded towards 0. 69 70 5) count_leading_zeros(count, x) counts the number of zero-bits from the 71 msb to the first nonzero bit in the UWtype X. This is the number of 72 steps X needs to be shifted left to set the msb. Undefined for X == 0, 73 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value. 74 75 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts 76 from the least significant end. 77 78 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, 79 high_addend_2, low_addend_2) adds two UWtype integers, composed by 80 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2 81 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow 82 (i.e. carry out) is not stored anywhere, and is lost. 83 84 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend, 85 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers, 86 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and 87 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE 88 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, 89 and is lost. 90 91 If any of these macros are left undefined for a particular CPU, 92 C macros are used. */ 93 94/* The CPUs come in alphabetical order below. 95 96 Please add support for more CPUs here, or improve the current support 97 for the CPUs below! 98 (E.g. WE32100, IBM360.) */ 99 100#if defined (__GNUC__) && !defined (NO_ASM) 101 102/* We sometimes need to clobber "cc" with gcc2, but that would not be 103 understood by gcc1. Use cpp to avoid major code duplication. */ 104#if __GNUC__ < 2 105#define __CLOBBER_CC 106#define __AND_CLOBBER_CC 107#else /* __GNUC__ >= 2 */ 108#define __CLOBBER_CC : "cc" 109#define __AND_CLOBBER_CC , "cc" 110#endif /* __GNUC__ < 2 */ 111 112#if defined (__alpha) && W_TYPE_SIZE == 64 113#define umul_ppmm(ph, pl, m0, m1) \ 114 do { \ 115 UDItype __m0 = (m0), __m1 = (m1); \ 116 __asm__ ("umulh %r1,%2,%0" \ 117 : "=r" ((UDItype) ph) \ 118 : "%rJ" (__m0), \ 119 "rI" (__m1)); \ 120 (pl) = __m0 * __m1; \ 121 } while (0) 122#define UMUL_TIME 46 123#ifndef LONGLONG_STANDALONE 124#define udiv_qrnnd(q, r, n1, n0, d) \ 125 do { UDItype __r; \ 126 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \ 127 (r) = __r; \ 128 } while (0) 129extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); 130#define UDIV_TIME 220 131#endif /* LONGLONG_STANDALONE */ 132#ifdef __alpha_cix__ 133#define count_leading_zeros(COUNT,X) \ 134 __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X)) 135#define count_trailing_zeros(COUNT,X) \ 136 __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X)) 137#define COUNT_LEADING_ZEROS_0 64 138#else 139extern const UQItype __clz_tab[]; 140#define count_leading_zeros(COUNT,X) \ 141 do { \ 142 UDItype __xr = (X), __t, __a; \ 143 __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \ 144 __a = __clz_tab[__t ^ 0xff] - 1; \ 145 __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \ 146 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \ 147 } while (0) 148#define count_trailing_zeros(COUNT,X) \ 149 do { \ 150 UDItype __xr = (X), __t, __a; \ 151 __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \ 152 __t = ~__t & -~__t; \ 153 __a = ((__t & 0xCC) != 0) * 2; \ 154 __a += ((__t & 0xF0) != 0) * 4; \ 155 __a += ((__t & 0xAA) != 0); \ 156 __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \ 157 __a <<= 3; \ 158 __t &= -__t; \ 159 __a += ((__t & 0xCC) != 0) * 2; \ 160 __a += ((__t & 0xF0) != 0) * 4; \ 161 __a += ((__t & 0xAA) != 0); \ 162 (COUNT) = __a; \ 163 } while (0) 164#endif /* __alpha_cix__ */ 165#endif /* __alpha */ 166 167#if defined (__arc__) && W_TYPE_SIZE == 32 168#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 169 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \ 170 : "=r" ((USItype) (sh)), \ 171 "=&r" ((USItype) (sl)) \ 172 : "%r" ((USItype) (ah)), \ 173 "rIJ" ((USItype) (bh)), \ 174 "%r" ((USItype) (al)), \ 175 "rIJ" ((USItype) (bl))) 176#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 177 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \ 178 : "=r" ((USItype) (sh)), \ 179 "=&r" ((USItype) (sl)) \ 180 : "r" ((USItype) (ah)), \ 181 "rIJ" ((USItype) (bh)), \ 182 "r" ((USItype) (al)), \ 183 "rIJ" ((USItype) (bl))) 184/* Call libgcc routine. */ 185#define umul_ppmm(w1, w0, u, v) \ 186do { \ 187 DWunion __w; \ 188 __w.ll = __umulsidi3 (u, v); \ 189 w1 = __w.s.high; \ 190 w0 = __w.s.low; \ 191} while (0) 192#define __umulsidi3 __umulsidi3 193UDItype __umulsidi3 (USItype, USItype); 194#endif 195 196#if defined (__arm__) && W_TYPE_SIZE == 32 197#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 198 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \ 199 : "=r" ((USItype) (sh)), \ 200 "=&r" ((USItype) (sl)) \ 201 : "%r" ((USItype) (ah)), \ 202 "rI" ((USItype) (bh)), \ 203 "%r" ((USItype) (al)), \ 204 "rI" ((USItype) (bl))) 205#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 206 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \ 207 : "=r" ((USItype) (sh)), \ 208 "=&r" ((USItype) (sl)) \ 209 : "r" ((USItype) (ah)), \ 210 "rI" ((USItype) (bh)), \ 211 "r" ((USItype) (al)), \ 212 "rI" ((USItype) (bl))) 213#define umul_ppmm(xh, xl, a, b) \ 214{register USItype __t0, __t1, __t2; \ 215 __asm__ ("%@ Inlined umul_ppmm\n" \ 216 " mov %2, %5, lsr #16\n" \ 217 " mov %0, %6, lsr #16\n" \ 218 " bic %3, %5, %2, lsl #16\n" \ 219 " bic %4, %6, %0, lsl #16\n" \ 220 " mul %1, %3, %4\n" \ 221 " mul %4, %2, %4\n" \ 222 " mul %3, %0, %3\n" \ 223 " mul %0, %2, %0\n" \ 224 " adds %3, %4, %3\n" \ 225 " addcs %0, %0, #65536\n" \ 226 " adds %1, %1, %3, lsl #16\n" \ 227 " adc %0, %0, %3, lsr #16" \ 228 : "=&r" ((USItype) (xh)), \ 229 "=r" ((USItype) (xl)), \ 230 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ 231 : "r" ((USItype) (a)), \ 232 "r" ((USItype) (b)));} 233#define UMUL_TIME 20 234#define UDIV_TIME 100 235#endif /* __arm__ */ 236 237#if defined (__hppa) && W_TYPE_SIZE == 32 238#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 239 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \ 240 : "=r" ((USItype) (sh)), \ 241 "=&r" ((USItype) (sl)) \ 242 : "%rM" ((USItype) (ah)), \ 243 "rM" ((USItype) (bh)), \ 244 "%rM" ((USItype) (al)), \ 245 "rM" ((USItype) (bl))) 246#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 247 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \ 248 : "=r" ((USItype) (sh)), \ 249 "=&r" ((USItype) (sl)) \ 250 : "rM" ((USItype) (ah)), \ 251 "rM" ((USItype) (bh)), \ 252 "rM" ((USItype) (al)), \ 253 "rM" ((USItype) (bl))) 254#if defined (_PA_RISC1_1) 255#define umul_ppmm(w1, w0, u, v) \ 256 do { \ 257 union \ 258 { \ 259 UDItype __f; \ 260 struct {USItype __w1, __w0;} __w1w0; \ 261 } __t; \ 262 __asm__ ("xmpyu %1,%2,%0" \ 263 : "=x" (__t.__f) \ 264 : "x" ((USItype) (u)), \ 265 "x" ((USItype) (v))); \ 266 (w1) = __t.__w1w0.__w1; \ 267 (w0) = __t.__w1w0.__w0; \ 268 } while (0) 269#define UMUL_TIME 8 270#else 271#define UMUL_TIME 30 272#endif 273#define UDIV_TIME 40 274#define count_leading_zeros(count, x) \ 275 do { \ 276 USItype __tmp; \ 277 __asm__ ( \ 278 "ldi 1,%0\n" \ 279" extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \ 280" extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\ 281" ldo 16(%0),%0 ; Yes. Perform add.\n" \ 282" extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \ 283" extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\ 284" ldo 8(%0),%0 ; Yes. Perform add.\n" \ 285" extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \ 286" extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\ 287" ldo 4(%0),%0 ; Yes. Perform add.\n" \ 288" extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \ 289" extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\ 290" ldo 2(%0),%0 ; Yes. Perform add.\n" \ 291" extru %1,30,1,%1 ; Extract bit 1.\n" \ 292" sub %0,%1,%0 ; Subtract it.\n" \ 293 : "=r" (count), "=r" (__tmp) : "1" (x)); \ 294 } while (0) 295#endif 296 297#if (defined (__i370__) || defined (__mvs__)) && W_TYPE_SIZE == 32 298#define umul_ppmm(xh, xl, m0, m1) \ 299 do { \ 300 union {UDItype __ll; \ 301 struct {USItype __h, __l;} __i; \ 302 } __xx; \ 303 USItype __m0 = (m0), __m1 = (m1); \ 304 __asm__ ("mr %0,%3" \ 305 : "=r" (__xx.__i.__h), \ 306 "=r" (__xx.__i.__l) \ 307 : "%1" (__m0), \ 308 "r" (__m1)); \ 309 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ 310 (xh) += ((((SItype) __m0 >> 31) & __m1) \ 311 + (((SItype) __m1 >> 31) & __m0)); \ 312 } while (0) 313#define smul_ppmm(xh, xl, m0, m1) \ 314 do { \ 315 union {DItype __ll; \ 316 struct {USItype __h, __l;} __i; \ 317 } __xx; \ 318 __asm__ ("mr %0,%3" \ 319 : "=r" (__xx.__i.__h), \ 320 "=r" (__xx.__i.__l) \ 321 : "%1" (m0), \ 322 "r" (m1)); \ 323 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ 324 } while (0) 325#define sdiv_qrnnd(q, r, n1, n0, d) \ 326 do { \ 327 union {DItype __ll; \ 328 struct {USItype __h, __l;} __i; \ 329 } __xx; \ 330 __xx.__i.__h = n1; __xx.__i.__l = n0; \ 331 __asm__ ("dr %0,%2" \ 332 : "=r" (__xx.__ll) \ 333 : "0" (__xx.__ll), "r" (d)); \ 334 (q) = __xx.__i.__l; (r) = __xx.__i.__h; \ 335 } while (0) 336#endif 337 338#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 339#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 340 __asm__ ("addl %5,%1\n\tadcl %3,%0" \ 341 : "=r" ((USItype) (sh)), \ 342 "=&r" ((USItype) (sl)) \ 343 : "%0" ((USItype) (ah)), \ 344 "g" ((USItype) (bh)), \ 345 "%1" ((USItype) (al)), \ 346 "g" ((USItype) (bl))) 347#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 348 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \ 349 : "=r" ((USItype) (sh)), \ 350 "=&r" ((USItype) (sl)) \ 351 : "0" ((USItype) (ah)), \ 352 "g" ((USItype) (bh)), \ 353 "1" ((USItype) (al)), \ 354 "g" ((USItype) (bl))) 355#define umul_ppmm(w1, w0, u, v) \ 356 __asm__ ("mull %3" \ 357 : "=a" ((USItype) (w0)), \ 358 "=d" ((USItype) (w1)) \ 359 : "%0" ((USItype) (u)), \ 360 "rm" ((USItype) (v))) 361#define udiv_qrnnd(q, r, n1, n0, dv) \ 362 __asm__ ("divl %4" \ 363 : "=a" ((USItype) (q)), \ 364 "=d" ((USItype) (r)) \ 365 : "0" ((USItype) (n0)), \ 366 "1" ((USItype) (n1)), \ 367 "rm" ((USItype) (dv))) 368#define count_leading_zeros(count, x) \ 369 do { \ 370 USItype __cbtmp; \ 371 __asm__ ("bsrl %1,%0" \ 372 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \ 373 (count) = __cbtmp ^ 31; \ 374 } while (0) 375#define count_trailing_zeros(count, x) \ 376 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x))) 377#define UMUL_TIME 40 378#define UDIV_TIME 40 379#endif /* 80x86 */ 380 381#if defined (__i960__) && W_TYPE_SIZE == 32 382#define umul_ppmm(w1, w0, u, v) \ 383 ({union {UDItype __ll; \ 384 struct {USItype __l, __h;} __i; \ 385 } __xx; \ 386 __asm__ ("emul %2,%1,%0" \ 387 : "=d" (__xx.__ll) \ 388 : "%dI" ((USItype) (u)), \ 389 "dI" ((USItype) (v))); \ 390 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) 391#define __umulsidi3(u, v) \ 392 ({UDItype __w; \ 393 __asm__ ("emul %2,%1,%0" \ 394 : "=d" (__w) \ 395 : "%dI" ((USItype) (u)), \ 396 "dI" ((USItype) (v))); \ 397 __w; }) 398#endif /* __i960__ */ 399 400#if defined (__M32R__) && W_TYPE_SIZE == 32 401#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 402 /* The cmp clears the condition bit. */ \ 403 __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0" \ 404 : "=r" ((USItype) (sh)), \ 405 "=&r" ((USItype) (sl)) \ 406 : "%0" ((USItype) (ah)), \ 407 "r" ((USItype) (bh)), \ 408 "%1" ((USItype) (al)), \ 409 "r" ((USItype) (bl)) \ 410 : "cbit") 411#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 412 /* The cmp clears the condition bit. */ \ 413 __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0" \ 414 : "=r" ((USItype) (sh)), \ 415 "=&r" ((USItype) (sl)) \ 416 : "0" ((USItype) (ah)), \ 417 "r" ((USItype) (bh)), \ 418 "1" ((USItype) (al)), \ 419 "r" ((USItype) (bl)) \ 420 : "cbit") 421#endif /* __M32R__ */ 422 423#if defined (__mc68000__) && W_TYPE_SIZE == 32 424#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 425 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \ 426 : "=d" ((USItype) (sh)), \ 427 "=&d" ((USItype) (sl)) \ 428 : "%0" ((USItype) (ah)), \ 429 "d" ((USItype) (bh)), \ 430 "%1" ((USItype) (al)), \ 431 "g" ((USItype) (bl))) 432#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 433 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \ 434 : "=d" ((USItype) (sh)), \ 435 "=&d" ((USItype) (sl)) \ 436 : "0" ((USItype) (ah)), \ 437 "d" ((USItype) (bh)), \ 438 "1" ((USItype) (al)), \ 439 "g" ((USItype) (bl))) 440 441/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */ 442#if defined (__mc68020__) || defined(mc68020) \ 443 || defined(__mc68030__) || defined(mc68030) \ 444 || defined(__mc68040__) || defined(mc68040) \ 445 || defined(__mcpu32__) || defined(mcpu32) 446#define umul_ppmm(w1, w0, u, v) \ 447 __asm__ ("mulu%.l %3,%1:%0" \ 448 : "=d" ((USItype) (w0)), \ 449 "=d" ((USItype) (w1)) \ 450 : "%0" ((USItype) (u)), \ 451 "dmi" ((USItype) (v))) 452#define UMUL_TIME 45 453#define udiv_qrnnd(q, r, n1, n0, d) \ 454 __asm__ ("divu%.l %4,%1:%0" \ 455 : "=d" ((USItype) (q)), \ 456 "=d" ((USItype) (r)) \ 457 : "0" ((USItype) (n0)), \ 458 "1" ((USItype) (n1)), \ 459 "dmi" ((USItype) (d))) 460#define UDIV_TIME 90 461#define sdiv_qrnnd(q, r, n1, n0, d) \ 462 __asm__ ("divs%.l %4,%1:%0" \ 463 : "=d" ((USItype) (q)), \ 464 "=d" ((USItype) (r)) \ 465 : "0" ((USItype) (n0)), \ 466 "1" ((USItype) (n1)), \ 467 "dmi" ((USItype) (d))) 468 469#else /* not mc68020 */ 470#if !defined(__mcf5200__) 471/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */ 472#define umul_ppmm(xh, xl, a, b) \ 473 __asm__ ("| Inlined umul_ppmm\n" \ 474 " move%.l %2,%/d0\n" \ 475 " move%.l %3,%/d1\n" \ 476 " move%.l %/d0,%/d2\n" \ 477 " swap %/d0\n" \ 478 " move%.l %/d1,%/d3\n" \ 479 " swap %/d1\n" \ 480 " move%.w %/d2,%/d4\n" \ 481 " mulu %/d3,%/d4\n" \ 482 " mulu %/d1,%/d2\n" \ 483 " mulu %/d0,%/d3\n" \ 484 " mulu %/d0,%/d1\n" \ 485 " move%.l %/d4,%/d0\n" \ 486 " eor%.w %/d0,%/d0\n" \ 487 " swap %/d0\n" \ 488 " add%.l %/d0,%/d2\n" \ 489 " add%.l %/d3,%/d2\n" \ 490 " jcc 1f\n" \ 491 " add%.l %#65536,%/d1\n" \ 492 "1: swap %/d2\n" \ 493 " moveq %#0,%/d0\n" \ 494 " move%.w %/d2,%/d0\n" \ 495 " move%.w %/d4,%/d2\n" \ 496 " move%.l %/d2,%1\n" \ 497 " add%.l %/d1,%/d0\n" \ 498 " move%.l %/d0,%0" \ 499 : "=g" ((USItype) (xh)), \ 500 "=g" ((USItype) (xl)) \ 501 : "g" ((USItype) (a)), \ 502 "g" ((USItype) (b)) \ 503 : "d0", "d1", "d2", "d3", "d4") 504#define UMUL_TIME 100 505#define UDIV_TIME 400 506#endif /* not mcf5200 */ 507#endif /* not mc68020 */ 508 509/* The '020, '030, '040 and '060 have bitfield insns. */ 510#if defined (__mc68020__) || defined(mc68020) \ 511 || defined(__mc68030__) || defined(mc68030) \ 512 || defined(__mc68040__) || defined(mc68040) \ 513 || defined(__mc68060__) || defined(mc68060) 514#define count_leading_zeros(count, x) \ 515 __asm__ ("bfffo %1{%b2:%b2},%0" \ 516 : "=d" ((USItype) (count)) \ 517 : "od" ((USItype) (x)), "n" (0)) 518#endif 519#endif /* mc68000 */ 520 521#if defined (__m88000__) && W_TYPE_SIZE == 32 522#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 523 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \ 524 : "=r" ((USItype) (sh)), \ 525 "=&r" ((USItype) (sl)) \ 526 : "%rJ" ((USItype) (ah)), \ 527 "rJ" ((USItype) (bh)), \ 528 "%rJ" ((USItype) (al)), \ 529 "rJ" ((USItype) (bl))) 530#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 531 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \ 532 : "=r" ((USItype) (sh)), \ 533 "=&r" ((USItype) (sl)) \ 534 : "rJ" ((USItype) (ah)), \ 535 "rJ" ((USItype) (bh)), \ 536 "rJ" ((USItype) (al)), \ 537 "rJ" ((USItype) (bl))) 538#define count_leading_zeros(count, x) \ 539 do { \ 540 USItype __cbtmp; \ 541 __asm__ ("ff1 %0,%1" \ 542 : "=r" (__cbtmp) \ 543 : "r" ((USItype) (x))); \ 544 (count) = __cbtmp ^ 31; \ 545 } while (0) 546#define COUNT_LEADING_ZEROS_0 63 /* sic */ 547#if defined (__mc88110__) 548#define umul_ppmm(wh, wl, u, v) \ 549 do { \ 550 union {UDItype __ll; \ 551 struct {USItype __h, __l;} __i; \ 552 } __xx; \ 553 __asm__ ("mulu.d %0,%1,%2" \ 554 : "=r" (__xx.__ll) \ 555 : "r" ((USItype) (u)), \ 556 "r" ((USItype) (v))); \ 557 (wh) = __xx.__i.__h; \ 558 (wl) = __xx.__i.__l; \ 559 } while (0) 560#define udiv_qrnnd(q, r, n1, n0, d) \ 561 ({union {UDItype __ll; \ 562 struct {USItype __h, __l;} __i; \ 563 } __xx; \ 564 USItype __q; \ 565 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ 566 __asm__ ("divu.d %0,%1,%2" \ 567 : "=r" (__q) \ 568 : "r" (__xx.__ll), \ 569 "r" ((USItype) (d))); \ 570 (r) = (n0) - __q * (d); (q) = __q; }) 571#define UMUL_TIME 5 572#define UDIV_TIME 25 573#else 574#define UMUL_TIME 17 575#define UDIV_TIME 150 576#endif /* __mc88110__ */ 577#endif /* __m88000__ */ 578 579#if defined (__mips__) && W_TYPE_SIZE == 32 580#define umul_ppmm(w1, w0, u, v) \ 581 __asm__ ("multu %2,%3" \ 582 : "=l" ((USItype) (w0)), \ 583 "=h" ((USItype) (w1)) \ 584 : "d" ((USItype) (u)), \ 585 "d" ((USItype) (v))) 586#define UMUL_TIME 10 587#define UDIV_TIME 100 588#endif /* __mips__ */ 589 590#if defined (__ns32000__) && W_TYPE_SIZE == 32 591#define umul_ppmm(w1, w0, u, v) \ 592 ({union {UDItype __ll; \ 593 struct {USItype __l, __h;} __i; \ 594 } __xx; \ 595 __asm__ ("meid %2,%0" \ 596 : "=g" (__xx.__ll) \ 597 : "%0" ((USItype) (u)), \ 598 "g" ((USItype) (v))); \ 599 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) 600#define __umulsidi3(u, v) \ 601 ({UDItype __w; \ 602 __asm__ ("meid %2,%0" \ 603 : "=g" (__w) \ 604 : "%0" ((USItype) (u)), \ 605 "g" ((USItype) (v))); \ 606 __w; }) 607#define udiv_qrnnd(q, r, n1, n0, d) \ 608 ({union {UDItype __ll; \ 609 struct {USItype __l, __h;} __i; \ 610 } __xx; \ 611 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ 612 __asm__ ("deid %2,%0" \ 613 : "=g" (__xx.__ll) \ 614 : "0" (__xx.__ll), \ 615 "g" ((USItype) (d))); \ 616 (r) = __xx.__i.__l; (q) = __xx.__i.__h; }) 617#define count_trailing_zeros(count,x) \ 618 do { \ 619 __asm__ ("ffsd %2,%0" \ 620 : "=r" ((USItype) (count)) \ 621 : "0" ((USItype) 0), \ 622 "r" ((USItype) (x))); \ 623 } while (0) 624#endif /* __ns32000__ */ 625 626/* FIXME: We should test _IBMR2 here when we add assembly support for the 627 system vendor compilers. 628 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good 629 enough, since that hits ARM and m68k too. */ 630#if (defined (_ARCH_PPC) /* AIX */ \ 631 || defined (_ARCH_PWR) /* AIX */ \ 632 || defined (_ARCH_COM) /* AIX */ \ 633 || defined (__powerpc__) /* gcc */ \ 634 || defined (__POWERPC__) /* BEOS */ \ 635 || defined (__ppc__) /* Darwin */ \ 636 || defined (PPC) /* GNU/Linux, SysV */ \ 637 ) && W_TYPE_SIZE == 32 638#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 639 do { \ 640 if (__builtin_constant_p (bh) && (bh) == 0) \ 641 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ 642 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 643 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ 644 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ 645 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 646 else \ 647 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ 648 : "=r" (sh), "=&r" (sl) \ 649 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ 650 } while (0) 651#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 652 do { \ 653 if (__builtin_constant_p (ah) && (ah) == 0) \ 654 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ 655 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 656 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \ 657 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ 658 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 659 else if (__builtin_constant_p (bh) && (bh) == 0) \ 660 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ 661 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 662 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ 663 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ 664 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 665 else \ 666 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ 667 : "=r" (sh), "=&r" (sl) \ 668 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ 669 } while (0) 670#define count_leading_zeros(count, x) \ 671 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x)) 672#define COUNT_LEADING_ZEROS_0 32 673#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \ 674 || defined (__ppc__) || defined (PPC) || defined (__vxworks__) 675#define umul_ppmm(ph, pl, m0, m1) \ 676 do { \ 677 USItype __m0 = (m0), __m1 = (m1); \ 678 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 679 (pl) = __m0 * __m1; \ 680 } while (0) 681#define UMUL_TIME 15 682#define smul_ppmm(ph, pl, m0, m1) \ 683 do { \ 684 SItype __m0 = (m0), __m1 = (m1); \ 685 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 686 (pl) = __m0 * __m1; \ 687 } while (0) 688#define SMUL_TIME 14 689#define UDIV_TIME 120 690#elif defined (_ARCH_PWR) 691#define UMUL_TIME 8 692#define smul_ppmm(xh, xl, m0, m1) \ 693 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1)) 694#define SMUL_TIME 4 695#define sdiv_qrnnd(q, r, nh, nl, d) \ 696 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d)) 697#define UDIV_TIME 100 698#endif 699#endif /* 32-bit POWER architecture variants. */ 700 701/* We should test _IBMR2 here when we add assembly support for the system 702 vendor compilers. */ 703#if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64 704#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 705 do { \ 706 if (__builtin_constant_p (bh) && (bh) == 0) \ 707 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ 708 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 709 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ 710 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ 711 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 712 else \ 713 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ 714 : "=r" (sh), "=&r" (sl) \ 715 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ 716 } while (0) 717#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 718 do { \ 719 if (__builtin_constant_p (ah) && (ah) == 0) \ 720 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ 721 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 722 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \ 723 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ 724 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 725 else if (__builtin_constant_p (bh) && (bh) == 0) \ 726 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ 727 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 728 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ 729 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ 730 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 731 else \ 732 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ 733 : "=r" (sh), "=&r" (sl) \ 734 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ 735 } while (0) 736#define count_leading_zeros(count, x) \ 737 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x)) 738#define COUNT_LEADING_ZEROS_0 64 739#define umul_ppmm(ph, pl, m0, m1) \ 740 do { \ 741 UDItype __m0 = (m0), __m1 = (m1); \ 742 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 743 (pl) = __m0 * __m1; \ 744 } while (0) 745#define UMUL_TIME 15 746#define smul_ppmm(ph, pl, m0, m1) \ 747 do { \ 748 DItype __m0 = (m0), __m1 = (m1); \ 749 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 750 (pl) = __m0 * __m1; \ 751 } while (0) 752#define SMUL_TIME 14 /* ??? */ 753#define UDIV_TIME 120 /* ??? */ 754#endif /* 64-bit PowerPC. */ 755 756#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 757#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 758 __asm__ ("a %1,%5\n\tae %0,%3" \ 759 : "=r" ((USItype) (sh)), \ 760 "=&r" ((USItype) (sl)) \ 761 : "%0" ((USItype) (ah)), \ 762 "r" ((USItype) (bh)), \ 763 "%1" ((USItype) (al)), \ 764 "r" ((USItype) (bl))) 765#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 766 __asm__ ("s %1,%5\n\tse %0,%3" \ 767 : "=r" ((USItype) (sh)), \ 768 "=&r" ((USItype) (sl)) \ 769 : "0" ((USItype) (ah)), \ 770 "r" ((USItype) (bh)), \ 771 "1" ((USItype) (al)), \ 772 "r" ((USItype) (bl))) 773#define umul_ppmm(ph, pl, m0, m1) \ 774 do { \ 775 USItype __m0 = (m0), __m1 = (m1); \ 776 __asm__ ( \ 777 "s r2,r2\n" \ 778" mts r10,%2\n" \ 779" m r2,%3\n" \ 780" m r2,%3\n" \ 781" m r2,%3\n" \ 782" m r2,%3\n" \ 783" m r2,%3\n" \ 784" m r2,%3\n" \ 785" m r2,%3\n" \ 786" m r2,%3\n" \ 787" m r2,%3\n" \ 788" m r2,%3\n" \ 789" m r2,%3\n" \ 790" m r2,%3\n" \ 791" m r2,%3\n" \ 792" m r2,%3\n" \ 793" m r2,%3\n" \ 794" m r2,%3\n" \ 795" cas %0,r2,r0\n" \ 796" mfs r10,%1" \ 797 : "=r" ((USItype) (ph)), \ 798 "=r" ((USItype) (pl)) \ 799 : "%r" (__m0), \ 800 "r" (__m1) \ 801 : "r2"); \ 802 (ph) += ((((SItype) __m0 >> 31) & __m1) \ 803 + (((SItype) __m1 >> 31) & __m0)); \ 804 } while (0) 805#define UMUL_TIME 20 806#define UDIV_TIME 200 807#define count_leading_zeros(count, x) \ 808 do { \ 809 if ((x) >= 0x10000) \ 810 __asm__ ("clz %0,%1" \ 811 : "=r" ((USItype) (count)) \ 812 : "r" ((USItype) (x) >> 16)); \ 813 else \ 814 { \ 815 __asm__ ("clz %0,%1" \ 816 : "=r" ((USItype) (count)) \ 817 : "r" ((USItype) (x))); \ 818 (count) += 16; \ 819 } \ 820 } while (0) 821#endif 822 823#if defined (__sh2__) && W_TYPE_SIZE == 32 824#define umul_ppmm(w1, w0, u, v) \ 825 __asm__ ( \ 826 "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \ 827 : "=r" ((USItype)(w1)), \ 828 "=r" ((USItype)(w0)) \ 829 : "r" ((USItype)(u)), \ 830 "r" ((USItype)(v)) \ 831 : "macl", "mach") 832#define UMUL_TIME 5 833#endif 834 835#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32 836#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v) 837#define count_leading_zeros(count, x) \ 838 do \ 839 { \ 840 UDItype x_ = (USItype)(x); \ 841 SItype c_; \ 842 \ 843 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \ 844 (count) = c_ - 31; \ 845 } \ 846 while (0) 847#define COUNT_LEADING_ZEROS_0 32 848#endif 849 850#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \ 851 && W_TYPE_SIZE == 32 852#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 853 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \ 854 : "=r" ((USItype) (sh)), \ 855 "=&r" ((USItype) (sl)) \ 856 : "%rJ" ((USItype) (ah)), \ 857 "rI" ((USItype) (bh)), \ 858 "%rJ" ((USItype) (al)), \ 859 "rI" ((USItype) (bl)) \ 860 __CLOBBER_CC) 861#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 862 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \ 863 : "=r" ((USItype) (sh)), \ 864 "=&r" ((USItype) (sl)) \ 865 : "rJ" ((USItype) (ah)), \ 866 "rI" ((USItype) (bh)), \ 867 "rJ" ((USItype) (al)), \ 868 "rI" ((USItype) (bl)) \ 869 __CLOBBER_CC) 870#if defined (__sparc_v8__) 871#define umul_ppmm(w1, w0, u, v) \ 872 __asm__ ("umul %2,%3,%1;rd %%y,%0" \ 873 : "=r" ((USItype) (w1)), \ 874 "=r" ((USItype) (w0)) \ 875 : "r" ((USItype) (u)), \ 876 "r" ((USItype) (v))) 877#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ 878 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\ 879 : "=&r" ((USItype) (__q)), \ 880 "=&r" ((USItype) (__r)) \ 881 : "r" ((USItype) (__n1)), \ 882 "r" ((USItype) (__n0)), \ 883 "r" ((USItype) (__d))) 884#else 885#if defined (__sparclite__) 886/* This has hardware multiply but not divide. It also has two additional 887 instructions scan (ffs from high bit) and divscc. */ 888#define umul_ppmm(w1, w0, u, v) \ 889 __asm__ ("umul %2,%3,%1;rd %%y,%0" \ 890 : "=r" ((USItype) (w1)), \ 891 "=r" ((USItype) (w0)) \ 892 : "r" ((USItype) (u)), \ 893 "r" ((USItype) (v))) 894#define udiv_qrnnd(q, r, n1, n0, d) \ 895 __asm__ ("! Inlined udiv_qrnnd\n" \ 896" wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \ 897" tst %%g0\n" \ 898" divscc %3,%4,%%g1\n" \ 899" divscc %%g1,%4,%%g1\n" \ 900" divscc %%g1,%4,%%g1\n" \ 901" divscc %%g1,%4,%%g1\n" \ 902" divscc %%g1,%4,%%g1\n" \ 903" divscc %%g1,%4,%%g1\n" \ 904" divscc %%g1,%4,%%g1\n" \ 905" divscc %%g1,%4,%%g1\n" \ 906" divscc %%g1,%4,%%g1\n" \ 907" divscc %%g1,%4,%%g1\n" \ 908" divscc %%g1,%4,%%g1\n" \ 909" divscc %%g1,%4,%%g1\n" \ 910" divscc %%g1,%4,%%g1\n" \ 911" divscc %%g1,%4,%%g1\n" \ 912" divscc %%g1,%4,%%g1\n" \ 913" divscc %%g1,%4,%%g1\n" \ 914" divscc %%g1,%4,%%g1\n" \ 915" divscc %%g1,%4,%%g1\n" \ 916" divscc %%g1,%4,%%g1\n" \ 917" divscc %%g1,%4,%%g1\n" \ 918" divscc %%g1,%4,%%g1\n" \ 919" divscc %%g1,%4,%%g1\n" \ 920" divscc %%g1,%4,%%g1\n" \ 921" divscc %%g1,%4,%%g1\n" \ 922" divscc %%g1,%4,%%g1\n" \ 923" divscc %%g1,%4,%%g1\n" \ 924" divscc %%g1,%4,%%g1\n" \ 925" divscc %%g1,%4,%%g1\n" \ 926" divscc %%g1,%4,%%g1\n" \ 927" divscc %%g1,%4,%%g1\n" \ 928" divscc %%g1,%4,%%g1\n" \ 929" divscc %%g1,%4,%0\n" \ 930" rd %%y,%1\n" \ 931" bl,a 1f\n" \ 932" add %1,%4,%1\n" \ 933"1: ! End of inline udiv_qrnnd" \ 934 : "=r" ((USItype) (q)), \ 935 "=r" ((USItype) (r)) \ 936 : "r" ((USItype) (n1)), \ 937 "r" ((USItype) (n0)), \ 938 "rI" ((USItype) (d)) \ 939 : "g1" __AND_CLOBBER_CC) 940#define UDIV_TIME 37 941#define count_leading_zeros(count, x) \ 942 do { \ 943 __asm__ ("scan %1,1,%0" \ 944 : "=r" ((USItype) (count)) \ 945 : "r" ((USItype) (x))); \ 946 } while (0) 947/* Early sparclites return 63 for an argument of 0, but they warn that future 948 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0 949 undefined. */ 950#else 951/* SPARC without integer multiplication and divide instructions. 952 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */ 953#define umul_ppmm(w1, w0, u, v) \ 954 __asm__ ("! Inlined umul_ppmm\n" \ 955" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\ 956" sra %3,31,%%o5 ! Don't move this insn\n" \ 957" and %2,%%o5,%%o5 ! Don't move this insn\n" \ 958" andcc %%g0,0,%%g1 ! Don't move this insn\n" \ 959" mulscc %%g1,%3,%%g1\n" \ 960" mulscc %%g1,%3,%%g1\n" \ 961" mulscc %%g1,%3,%%g1\n" \ 962" mulscc %%g1,%3,%%g1\n" \ 963" mulscc %%g1,%3,%%g1\n" \ 964" mulscc %%g1,%3,%%g1\n" \ 965" mulscc %%g1,%3,%%g1\n" \ 966" mulscc %%g1,%3,%%g1\n" \ 967" mulscc %%g1,%3,%%g1\n" \ 968" mulscc %%g1,%3,%%g1\n" \ 969" mulscc %%g1,%3,%%g1\n" \ 970" mulscc %%g1,%3,%%g1\n" \ 971" mulscc %%g1,%3,%%g1\n" \ 972" mulscc %%g1,%3,%%g1\n" \ 973" mulscc %%g1,%3,%%g1\n" \ 974" mulscc %%g1,%3,%%g1\n" \ 975" mulscc %%g1,%3,%%g1\n" \ 976" mulscc %%g1,%3,%%g1\n" \ 977" mulscc %%g1,%3,%%g1\n" \ 978" mulscc %%g1,%3,%%g1\n" \ 979" mulscc %%g1,%3,%%g1\n" \ 980" mulscc %%g1,%3,%%g1\n" \ 981" mulscc %%g1,%3,%%g1\n" \ 982" mulscc %%g1,%3,%%g1\n" \ 983" mulscc %%g1,%3,%%g1\n" \ 984" mulscc %%g1,%3,%%g1\n" \ 985" mulscc %%g1,%3,%%g1\n" \ 986" mulscc %%g1,%3,%%g1\n" \ 987" mulscc %%g1,%3,%%g1\n" \ 988" mulscc %%g1,%3,%%g1\n" \ 989" mulscc %%g1,%3,%%g1\n" \ 990" mulscc %%g1,%3,%%g1\n" \ 991" mulscc %%g1,0,%%g1\n" \ 992" add %%g1,%%o5,%0\n" \ 993" rd %%y,%1" \ 994 : "=r" ((USItype) (w1)), \ 995 "=r" ((USItype) (w0)) \ 996 : "%rI" ((USItype) (u)), \ 997 "r" ((USItype) (v)) \ 998 : "g1", "o5" __AND_CLOBBER_CC) 999#define UMUL_TIME 39 /* 39 instructions */ 1000/* It's quite necessary to add this much assembler for the sparc. 1001 The default udiv_qrnnd (in C) is more than 10 times slower! */ 1002#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ 1003 __asm__ ("! Inlined udiv_qrnnd\n" \ 1004" mov 32,%%g1\n" \ 1005" subcc %1,%2,%%g0\n" \ 1006"1: bcs 5f\n" \ 1007" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ 1008" sub %1,%2,%1 ! this kills msb of n\n" \ 1009" addx %1,%1,%1 ! so this can't give carry\n" \ 1010" subcc %%g1,1,%%g1\n" \ 1011"2: bne 1b\n" \ 1012" subcc %1,%2,%%g0\n" \ 1013" bcs 3f\n" \ 1014" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ 1015" b 3f\n" \ 1016" sub %1,%2,%1 ! this kills msb of n\n" \ 1017"4: sub %1,%2,%1\n" \ 1018"5: addxcc %1,%1,%1\n" \ 1019" bcc 2b\n" \ 1020" subcc %%g1,1,%%g1\n" \ 1021"! Got carry from n. Subtract next step to cancel this carry.\n" \ 1022" bne 4b\n" \ 1023" addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \ 1024" sub %1,%2,%1\n" \ 1025"3: xnor %0,0,%0\n" \ 1026" ! End of inline udiv_qrnnd" \ 1027 : "=&r" ((USItype) (__q)), \ 1028 "=&r" ((USItype) (__r)) \ 1029 : "r" ((USItype) (__d)), \ 1030 "1" ((USItype) (__n1)), \ 1031 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC) 1032#define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */ 1033#endif /* __sparclite__ */ 1034#endif /* __sparc_v8__ */ 1035#endif /* sparc32 */ 1036 1037#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \ 1038 && W_TYPE_SIZE == 64 1039#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1040 __asm__ ("addcc %r4,%5,%1\n\t" \ 1041 "add %r2,%3,%0\n\t" \ 1042 "bcs,a,pn %%xcc, 1f\n\t" \ 1043 "add %0, 1, %0\n" \ 1044 "1:" \ 1045 : "=r" ((UDItype)(sh)), \ 1046 "=&r" ((UDItype)(sl)) \ 1047 : "%rJ" ((UDItype)(ah)), \ 1048 "rI" ((UDItype)(bh)), \ 1049 "%rJ" ((UDItype)(al)), \ 1050 "rI" ((UDItype)(bl)) \ 1051 __CLOBBER_CC) 1052 1053#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1054 __asm__ ("subcc %r4,%5,%1\n\t" \ 1055 "sub %r2,%3,%0\n\t" \ 1056 "bcs,a,pn %%xcc, 1f\n\t" \ 1057 "sub %0, 1, %0\n\t" \ 1058 "1:" \ 1059 : "=r" ((UDItype)(sh)), \ 1060 "=&r" ((UDItype)(sl)) \ 1061 : "rJ" ((UDItype)(ah)), \ 1062 "rI" ((UDItype)(bh)), \ 1063 "rJ" ((UDItype)(al)), \ 1064 "rI" ((UDItype)(bl)) \ 1065 __CLOBBER_CC) 1066 1067#define umul_ppmm(wh, wl, u, v) \ 1068 do { \ 1069 UDItype tmp1, tmp2, tmp3, tmp4; \ 1070 __asm__ __volatile__ ( \ 1071 "srl %7,0,%3\n\t" \ 1072 "mulx %3,%6,%1\n\t" \ 1073 "srlx %6,32,%2\n\t" \ 1074 "mulx %2,%3,%4\n\t" \ 1075 "sllx %4,32,%5\n\t" \ 1076 "srl %6,0,%3\n\t" \ 1077 "sub %1,%5,%5\n\t" \ 1078 "srlx %5,32,%5\n\t" \ 1079 "addcc %4,%5,%4\n\t" \ 1080 "srlx %7,32,%5\n\t" \ 1081 "mulx %3,%5,%3\n\t" \ 1082 "mulx %2,%5,%5\n\t" \ 1083 "sethi %%hi(0x80000000),%2\n\t" \ 1084 "addcc %4,%3,%4\n\t" \ 1085 "srlx %4,32,%4\n\t" \ 1086 "add %2,%2,%2\n\t" \ 1087 "movcc %%xcc,%%g0,%2\n\t" \ 1088 "addcc %5,%4,%5\n\t" \ 1089 "sllx %3,32,%3\n\t" \ 1090 "add %1,%3,%1\n\t" \ 1091 "add %5,%2,%0" \ 1092 : "=r" ((UDItype)(wh)), \ 1093 "=&r" ((UDItype)(wl)), \ 1094 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \ 1095 : "r" ((UDItype)(u)), \ 1096 "r" ((UDItype)(v)) \ 1097 __CLOBBER_CC); \ 1098 } while (0) 1099#define UMUL_TIME 96 1100#define UDIV_TIME 230 1101#endif /* sparc64 */ 1102 1103#if defined (__vax__) && W_TYPE_SIZE == 32 1104#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1105 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \ 1106 : "=g" ((USItype) (sh)), \ 1107 "=&g" ((USItype) (sl)) \ 1108 : "%0" ((USItype) (ah)), \ 1109 "g" ((USItype) (bh)), \ 1110 "%1" ((USItype) (al)), \ 1111 "g" ((USItype) (bl))) 1112#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1113 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \ 1114 : "=g" ((USItype) (sh)), \ 1115 "=&g" ((USItype) (sl)) \ 1116 : "0" ((USItype) (ah)), \ 1117 "g" ((USItype) (bh)), \ 1118 "1" ((USItype) (al)), \ 1119 "g" ((USItype) (bl))) 1120#define umul_ppmm(xh, xl, m0, m1) \ 1121 do { \ 1122 union { \ 1123 UDItype __ll; \ 1124 struct {USItype __l, __h;} __i; \ 1125 } __xx; \ 1126 USItype __m0 = (m0), __m1 = (m1); \ 1127 __asm__ ("emul %1,%2,$0,%0" \ 1128 : "=r" (__xx.__ll) \ 1129 : "g" (__m0), \ 1130 "g" (__m1)); \ 1131 (xh) = __xx.__i.__h; \ 1132 (xl) = __xx.__i.__l; \ 1133 (xh) += ((((SItype) __m0 >> 31) & __m1) \ 1134 + (((SItype) __m1 >> 31) & __m0)); \ 1135 } while (0) 1136#define sdiv_qrnnd(q, r, n1, n0, d) \ 1137 do { \ 1138 union {DItype __ll; \ 1139 struct {SItype __l, __h;} __i; \ 1140 } __xx; \ 1141 __xx.__i.__h = n1; __xx.__i.__l = n0; \ 1142 __asm__ ("ediv %3,%2,%0,%1" \ 1143 : "=g" (q), "=g" (r) \ 1144 : "g" (__xx.__ll), "g" (d)); \ 1145 } while (0) 1146#endif /* __vax__ */ 1147 1148#if defined (__z8000__) && W_TYPE_SIZE == 16 1149#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1150 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \ 1151 : "=r" ((unsigned int)(sh)), \ 1152 "=&r" ((unsigned int)(sl)) \ 1153 : "%0" ((unsigned int)(ah)), \ 1154 "r" ((unsigned int)(bh)), \ 1155 "%1" ((unsigned int)(al)), \ 1156 "rQR" ((unsigned int)(bl))) 1157#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1158 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \ 1159 : "=r" ((unsigned int)(sh)), \ 1160 "=&r" ((unsigned int)(sl)) \ 1161 : "0" ((unsigned int)(ah)), \ 1162 "r" ((unsigned int)(bh)), \ 1163 "1" ((unsigned int)(al)), \ 1164 "rQR" ((unsigned int)(bl))) 1165#define umul_ppmm(xh, xl, m0, m1) \ 1166 do { \ 1167 union {long int __ll; \ 1168 struct {unsigned int __h, __l;} __i; \ 1169 } __xx; \ 1170 unsigned int __m0 = (m0), __m1 = (m1); \ 1171 __asm__ ("mult %S0,%H3" \ 1172 : "=r" (__xx.__i.__h), \ 1173 "=r" (__xx.__i.__l) \ 1174 : "%1" (__m0), \ 1175 "rQR" (__m1)); \ 1176 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ 1177 (xh) += ((((signed int) __m0 >> 15) & __m1) \ 1178 + (((signed int) __m1 >> 15) & __m0)); \ 1179 } while (0) 1180#endif /* __z8000__ */ 1181 1182#endif /* __GNUC__ */ 1183 1184/* If this machine has no inline assembler, use C macros. */ 1185 1186#if !defined (add_ssaaaa) 1187#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1188 do { \ 1189 UWtype __x; \ 1190 __x = (al) + (bl); \ 1191 (sh) = (ah) + (bh) + (__x < (al)); \ 1192 (sl) = __x; \ 1193 } while (0) 1194#endif 1195 1196#if !defined (sub_ddmmss) 1197#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1198 do { \ 1199 UWtype __x; \ 1200 __x = (al) - (bl); \ 1201 (sh) = (ah) - (bh) - (__x > (al)); \ 1202 (sl) = __x; \ 1203 } while (0) 1204#endif 1205 1206#if !defined (umul_ppmm) 1207#define umul_ppmm(w1, w0, u, v) \ 1208 do { \ 1209 UWtype __x0, __x1, __x2, __x3; \ 1210 UHWtype __ul, __vl, __uh, __vh; \ 1211 \ 1212 __ul = __ll_lowpart (u); \ 1213 __uh = __ll_highpart (u); \ 1214 __vl = __ll_lowpart (v); \ 1215 __vh = __ll_highpart (v); \ 1216 \ 1217 __x0 = (UWtype) __ul * __vl; \ 1218 __x1 = (UWtype) __ul * __vh; \ 1219 __x2 = (UWtype) __uh * __vl; \ 1220 __x3 = (UWtype) __uh * __vh; \ 1221 \ 1222 __x1 += __ll_highpart (__x0);/* this can't give carry */ \ 1223 __x1 += __x2; /* but this indeed can */ \ 1224 if (__x1 < __x2) /* did we get it? */ \ 1225 __x3 += __ll_B; /* yes, add it in the proper pos. */ \ 1226 \ 1227 (w1) = __x3 + __ll_highpart (__x1); \ 1228 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ 1229 } while (0) 1230#endif 1231 1232#if !defined (__umulsidi3) 1233#define __umulsidi3(u, v) \ 1234 ({DWunion __w; \ 1235 umul_ppmm (__w.s.high, __w.s.low, u, v); \ 1236 __w.ll; }) 1237#endif 1238 1239/* Define this unconditionally, so it can be used for debugging. */ 1240#define __udiv_qrnnd_c(q, r, n1, n0, d) \ 1241 do { \ 1242 UWtype __d1, __d0, __q1, __q0; \ 1243 UWtype __r1, __r0, __m; \ 1244 __d1 = __ll_highpart (d); \ 1245 __d0 = __ll_lowpart (d); \ 1246 \ 1247 __r1 = (n1) % __d1; \ 1248 __q1 = (n1) / __d1; \ 1249 __m = (UWtype) __q1 * __d0; \ 1250 __r1 = __r1 * __ll_B | __ll_highpart (n0); \ 1251 if (__r1 < __m) \ 1252 { \ 1253 __q1--, __r1 += (d); \ 1254 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\ 1255 if (__r1 < __m) \ 1256 __q1--, __r1 += (d); \ 1257 } \ 1258 __r1 -= __m; \ 1259 \ 1260 __r0 = __r1 % __d1; \ 1261 __q0 = __r1 / __d1; \ 1262 __m = (UWtype) __q0 * __d0; \ 1263 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ 1264 if (__r0 < __m) \ 1265 { \ 1266 __q0--, __r0 += (d); \ 1267 if (__r0 >= (d)) \ 1268 if (__r0 < __m) \ 1269 __q0--, __r0 += (d); \ 1270 } \ 1271 __r0 -= __m; \ 1272 \ 1273 (q) = (UWtype) __q1 * __ll_B | __q0; \ 1274 (r) = __r0; \ 1275 } while (0) 1276 1277/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through 1278 __udiv_w_sdiv (defined in libgcc or elsewhere). */ 1279#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd) 1280#define udiv_qrnnd(q, r, nh, nl, d) \ 1281 do { \ 1282 USItype __r; \ 1283 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \ 1284 (r) = __r; \ 1285 } while (0) 1286#endif 1287 1288/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */ 1289#if !defined (udiv_qrnnd) 1290#define UDIV_NEEDS_NORMALIZATION 1 1291#define udiv_qrnnd __udiv_qrnnd_c 1292#endif 1293 1294#if !defined (count_leading_zeros) 1295extern const UQItype __clz_tab[]; 1296#define count_leading_zeros(count, x) \ 1297 do { \ 1298 UWtype __xr = (x); \ 1299 UWtype __a; \ 1300 \ 1301 if (W_TYPE_SIZE <= 32) \ 1302 { \ 1303 __a = __xr < ((UWtype)1<<2*__BITS4) \ 1304 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \ 1305 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \ 1306 } \ 1307 else \ 1308 { \ 1309 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \ 1310 if (((__xr >> __a) & 0xff) != 0) \ 1311 break; \ 1312 } \ 1313 \ 1314 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \ 1315 } while (0) 1316#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE 1317#endif 1318 1319#if !defined (count_trailing_zeros) 1320/* Define count_trailing_zeros using count_leading_zeros. The latter might be 1321 defined in asm, but if it is not, the C version above is good enough. */ 1322#define count_trailing_zeros(count, x) \ 1323 do { \ 1324 UWtype __ctz_x = (x); \ 1325 UWtype __ctz_c; \ 1326 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \ 1327 (count) = W_TYPE_SIZE - 1 - __ctz_c; \ 1328 } while (0) 1329#endif 1330 1331#ifndef UDIV_NEEDS_NORMALIZATION 1332#define UDIV_NEEDS_NORMALIZATION 0 1333#endif 1334