1/*
2 * Copyright 2007, François Revol, revol@free.fr.
3 * Distributed under the terms of the MIT License.
4 *
5 * Copyright 2003-2005, Axel Dörfler, axeld@pinc-software.de.
6 * Distributed under the terms of the MIT License.
7 *
8 * Copyright 2001, Travis Geiselbrecht. All rights reserved.
9 * Distributed under the terms of the NewOS License.
10 */
11
12
13#include <KernelExport.h>
14
15#include <arch/cpu.h>
16#include <boot/kernel_args.h>
17#include <commpage.h>
18#include <elf.h>
19
20
21int arch_cpu_type;
22int arch_fpu_type;
23int arch_mmu_type;
24int arch_platform;
25
26status_t
27arch_cpu_preboot_init_percpu(kernel_args *args, int curr_cpu)
28{
29	// enable FPU
30	//ppc:set_msr(get_msr() | MSR_FP_AVAILABLE);
31
32	// The current thread must be NULL for all CPUs till we have threads.
33	// Some boot code relies on this.
34	arch_thread_set_current_thread(NULL);
35
36	return B_OK;
37}
38
39
40status_t
41arch_cpu_init_percpu(kernel_args *args, int curr_cpu)
42{
43	if (curr_cpu != 0)
44		panic("No SMP support on ARM yet!\n");
45
46	return 0;
47}
48
49
50status_t
51arch_cpu_init(kernel_args *args)
52{
53	arch_cpu_type = args->arch_args.cpu_type;
54	arch_fpu_type = args->arch_args.fpu_type;
55	arch_mmu_type = args->arch_args.mmu_type;
56	arch_platform = args->arch_args.platform;
57	arch_platform = args->arch_args.machine;
58
59	return B_OK;
60}
61
62
63status_t
64arch_cpu_init_post_vm(kernel_args *args)
65{
66	return B_OK;
67}
68
69
70status_t
71arch_cpu_init_post_modules(kernel_args *args)
72{
73	// add the functions to the commpage image
74	image_id image = get_commpage_image();
75
76	return B_OK;
77}
78
79
80void
81arch_cpu_idle(void)
82{
83	uint32 Rd = 0;
84	asm volatile("mcr p15, 0, %[c7format], c7, c0, 4" : : [c7format] "r" (Rd) );
85}
86
87
88status_t
89arch_cpu_shutdown(bool reboot)
90{
91	while(1)
92		arch_cpu_idle();
93
94	// never reached
95	return B_ERROR;
96}
97
98
99void
100arch_cpu_sync_icache(void *address, size_t len)
101{
102	uint32 Rd = 0;
103	asm volatile ("mcr p15, 0, %[c7format], c7, c5, 0"
104		: : [c7format] "r" (Rd) );
105}
106
107
108void
109arch_cpu_memory_read_barrier(void)
110{
111	asm volatile ("" : : : "memory");
112}
113
114
115void
116arch_cpu_memory_write_barrier(void)
117{
118	asm volatile ("" : : : "memory");
119}
120
121
122void
123arch_cpu_invalidate_TLB_range(addr_t start, addr_t end)
124{
125	int32 num_pages = end / B_PAGE_SIZE - start / B_PAGE_SIZE;
126	while (num_pages-- >= 0) {
127		asm volatile ("mcr p15, 0, %[c8format], c8, c6, 1"
128			: : [c8format] "r" (start) );
129		start += B_PAGE_SIZE;
130	}
131}
132
133
134void
135arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages)
136{
137	for (int i = 0; i < num_pages; i++) {
138		asm volatile ("mcr p15, 0, %[c8format], c8, c6, 1":
139			: [c8format] "r" (pages[i]) );
140	}
141}
142
143
144void
145arch_cpu_global_TLB_invalidate(void)
146{
147	uint32 Rd = 0;
148	asm volatile ("mcr p15, 0, %[c8format], c8, c7, 0"
149		: : [c8format] "r" (Rd) );
150}
151
152
153void
154arch_cpu_user_TLB_invalidate(void)
155{/*
156	cpu_ops.flush_insn_pipeline();
157	cpu_ops.flush_atc_user();
158	cpu_ops.flush_insn_pipeline();
159*/
160#warning WRITEME
161}
162