1/* Disassembler interface for targets using CGEN. -*- C -*- 2 CGEN: Cpu tools GENerator 3 4THIS FILE IS MACHINE GENERATED WITH CGEN. 5- the resultant file is machine generated, cgen-dis.in isn't 6 7Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 8Free Software Foundation, Inc. 9 10This file is part of the GNU Binutils and GDB, the GNU debugger. 11 12This program is free software; you can redistribute it and/or modify 13it under the terms of the GNU General Public License as published by 14the Free Software Foundation; either version 2, or (at your option) 15any later version. 16 17This program is distributed in the hope that it will be useful, 18but WITHOUT ANY WARRANTY; without even the implied warranty of 19MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20GNU General Public License for more details. 21 22You should have received a copy of the GNU General Public License 23along with this program; if not, write to the Free Software Foundation, Inc., 2459 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 25 26/* ??? Eventually more and more of this stuff can go to cpu-independent files. 27 Keep that in mind. */ 28 29#include "sysdep.h" 30#include <stdio.h> 31#include "ansidecl.h" 32#include "dis-asm.h" 33#include "bfd.h" 34#include "symcat.h" 35#include "libiberty.h" 36#include "xstormy16-desc.h" 37#include "xstormy16-opc.h" 38#include "opintl.h" 39 40/* Default text to print if an instruction isn't recognized. */ 41#define UNKNOWN_INSN_MSG _("*unknown*") 42 43static void print_normal 44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 45static void print_address 46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); 47static void print_keyword 48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); 49static void print_insn_normal 50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 51static int print_insn 52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); 53static int default_print_insn 54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *); 55static int read_insn 56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, 57 unsigned long *); 58 59/* -- disassembler routines inserted here */ 60 61 62void xstormy16_cgen_print_operand 63 PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, 64 void const *, bfd_vma, int)); 65 66/* Main entry point for printing operands. 67 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 68 of dis-asm.h on cgen.h. 69 70 This function is basically just a big switch statement. Earlier versions 71 used tables to look up the function to use, but 72 - if the table contains both assembler and disassembler functions then 73 the disassembler contains much of the assembler and vice-versa, 74 - there's a lot of inlining possibilities as things grow, 75 - using a switch statement avoids the function call overhead. 76 77 This function could be moved into `print_insn_normal', but keeping it 78 separate makes clear the interface between `print_insn_normal' and each of 79 the handlers. */ 80 81void 82xstormy16_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) 83 CGEN_CPU_DESC cd; 84 int opindex; 85 PTR xinfo; 86 CGEN_FIELDS *fields; 87 void const *attrs ATTRIBUTE_UNUSED; 88 bfd_vma pc; 89 int length; 90{ 91 disassemble_info *info = (disassemble_info *) xinfo; 92 93 switch (opindex) 94 { 95 case XSTORMY16_OPERAND_RB : 96 print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0); 97 break; 98 case XSTORMY16_OPERAND_RBJ : 99 print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0); 100 break; 101 case XSTORMY16_OPERAND_RD : 102 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0); 103 break; 104 case XSTORMY16_OPERAND_RDM : 105 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0); 106 break; 107 case XSTORMY16_OPERAND_RM : 108 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0); 109 break; 110 case XSTORMY16_OPERAND_RS : 111 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0); 112 break; 113 case XSTORMY16_OPERAND_ABS24 : 114 print_normal (cd, info, fields->f_abs24, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 115 break; 116 case XSTORMY16_OPERAND_BCOND2 : 117 print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0); 118 break; 119 case XSTORMY16_OPERAND_BCOND5 : 120 print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0); 121 break; 122 case XSTORMY16_OPERAND_HMEM8 : 123 print_normal (cd, info, fields->f_hmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 124 break; 125 case XSTORMY16_OPERAND_IMM12 : 126 print_normal (cd, info, fields->f_imm12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 127 break; 128 case XSTORMY16_OPERAND_IMM16 : 129 print_normal (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); 130 break; 131 case XSTORMY16_OPERAND_IMM2 : 132 print_normal (cd, info, fields->f_imm2, 0, pc, length); 133 break; 134 case XSTORMY16_OPERAND_IMM3 : 135 print_normal (cd, info, fields->f_imm3, 0, pc, length); 136 break; 137 case XSTORMY16_OPERAND_IMM3B : 138 print_normal (cd, info, fields->f_imm3b, 0, pc, length); 139 break; 140 case XSTORMY16_OPERAND_IMM4 : 141 print_normal (cd, info, fields->f_imm4, 0, pc, length); 142 break; 143 case XSTORMY16_OPERAND_IMM8 : 144 print_normal (cd, info, fields->f_imm8, 0, pc, length); 145 break; 146 case XSTORMY16_OPERAND_IMM8SMALL : 147 print_normal (cd, info, fields->f_imm8, 0, pc, length); 148 break; 149 case XSTORMY16_OPERAND_LMEM8 : 150 print_normal (cd, info, fields->f_lmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 151 break; 152 case XSTORMY16_OPERAND_REL12 : 153 print_normal (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 154 break; 155 case XSTORMY16_OPERAND_REL12A : 156 print_normal (cd, info, fields->f_rel12a, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 157 break; 158 case XSTORMY16_OPERAND_REL8_2 : 159 print_normal (cd, info, fields->f_rel8_2, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 160 break; 161 case XSTORMY16_OPERAND_REL8_4 : 162 print_normal (cd, info, fields->f_rel8_4, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 163 break; 164 case XSTORMY16_OPERAND_WS2 : 165 print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0); 166 break; 167 168 default : 169 /* xgettext:c-format */ 170 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), 171 opindex); 172 abort (); 173 } 174} 175 176cgen_print_fn * const xstormy16_cgen_print_handlers[] = 177{ 178 print_insn_normal, 179}; 180 181 182void 183xstormy16_cgen_init_dis (cd) 184 CGEN_CPU_DESC cd; 185{ 186 xstormy16_cgen_init_opcode_table (cd); 187 xstormy16_cgen_init_ibld_table (cd); 188 cd->print_handlers = & xstormy16_cgen_print_handlers[0]; 189 cd->print_operand = xstormy16_cgen_print_operand; 190} 191 192 193/* Default print handler. */ 194 195static void 196print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 197 void *dis_info, 198 long value, 199 unsigned int attrs, 200 bfd_vma pc ATTRIBUTE_UNUSED, 201 int length ATTRIBUTE_UNUSED) 202{ 203 disassemble_info *info = (disassemble_info *) dis_info; 204 205#ifdef CGEN_PRINT_NORMAL 206 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); 207#endif 208 209 /* Print the operand as directed by the attributes. */ 210 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 211 ; /* nothing to do */ 212 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 213 (*info->fprintf_func) (info->stream, "%ld", value); 214 else 215 (*info->fprintf_func) (info->stream, "0x%lx", value); 216} 217 218/* Default address handler. */ 219 220static void 221print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 222 void *dis_info, 223 bfd_vma value, 224 unsigned int attrs, 225 bfd_vma pc ATTRIBUTE_UNUSED, 226 int length ATTRIBUTE_UNUSED) 227{ 228 disassemble_info *info = (disassemble_info *) dis_info; 229 230#ifdef CGEN_PRINT_ADDRESS 231 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); 232#endif 233 234 /* Print the operand as directed by the attributes. */ 235 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 236 ; /* nothing to do */ 237 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 238 (*info->print_address_func) (value, info); 239 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 240 (*info->print_address_func) (value, info); 241 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 242 (*info->fprintf_func) (info->stream, "%ld", (long) value); 243 else 244 (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 245} 246 247/* Keyword print handler. */ 248 249static void 250print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 251 void *dis_info, 252 CGEN_KEYWORD *keyword_table, 253 long value, 254 unsigned int attrs ATTRIBUTE_UNUSED) 255{ 256 disassemble_info *info = (disassemble_info *) dis_info; 257 const CGEN_KEYWORD_ENTRY *ke; 258 259 ke = cgen_keyword_lookup_value (keyword_table, value); 260 if (ke != NULL) 261 (*info->fprintf_func) (info->stream, "%s", ke->name); 262 else 263 (*info->fprintf_func) (info->stream, "???"); 264} 265 266/* Default insn printer. 267 268 DIS_INFO is defined as `void *' so the disassembler needn't know anything 269 about disassemble_info. */ 270 271static void 272print_insn_normal (CGEN_CPU_DESC cd, 273 void *dis_info, 274 const CGEN_INSN *insn, 275 CGEN_FIELDS *fields, 276 bfd_vma pc, 277 int length) 278{ 279 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 280 disassemble_info *info = (disassemble_info *) dis_info; 281 const CGEN_SYNTAX_CHAR_TYPE *syn; 282 283 CGEN_INIT_PRINT (cd); 284 285 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 286 { 287 if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 288 { 289 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 290 continue; 291 } 292 if (CGEN_SYNTAX_CHAR_P (*syn)) 293 { 294 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 295 continue; 296 } 297 298 /* We have an operand. */ 299 xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 300 fields, CGEN_INSN_ATTRS (insn), pc, length); 301 } 302} 303 304/* Subroutine of print_insn. Reads an insn into the given buffers and updates 305 the extract info. 306 Returns 0 if all is well, non-zero otherwise. */ 307 308static int 309read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 310 bfd_vma pc, 311 disassemble_info *info, 312 char *buf, 313 int buflen, 314 CGEN_EXTRACT_INFO *ex_info, 315 unsigned long *insn_value) 316{ 317 int status = (*info->read_memory_func) (pc, buf, buflen, info); 318 if (status != 0) 319 { 320 (*info->memory_error_func) (status, pc, info); 321 return -1; 322 } 323 324 ex_info->dis_info = info; 325 ex_info->valid = (1 << buflen) - 1; 326 ex_info->insn_bytes = buf; 327 328 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 329 return 0; 330} 331 332/* Utility to print an insn. 333 BUF is the base part of the insn, target byte order, BUFLEN bytes long. 334 The result is the size of the insn in bytes or zero for an unknown insn 335 or -1 if an error occurs fetching data (memory_error_func will have 336 been called). */ 337 338static int 339print_insn (CGEN_CPU_DESC cd, 340 bfd_vma pc, 341 disassemble_info *info, 342 char *buf, 343 unsigned int buflen) 344{ 345 CGEN_INSN_INT insn_value; 346 const CGEN_INSN_LIST *insn_list; 347 CGEN_EXTRACT_INFO ex_info; 348 int basesize; 349 350 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 351 basesize = cd->base_insn_bitsize < buflen * 8 ? 352 cd->base_insn_bitsize : buflen * 8; 353 insn_value = cgen_get_insn_value (cd, buf, basesize); 354 355 356 /* Fill in ex_info fields like read_insn would. Don't actually call 357 read_insn, since the incoming buffer is already read (and possibly 358 modified a la m32r). */ 359 ex_info.valid = (1 << buflen) - 1; 360 ex_info.dis_info = info; 361 ex_info.insn_bytes = buf; 362 363 /* The instructions are stored in hash lists. 364 Pick the first one and keep trying until we find the right one. */ 365 366 insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); 367 while (insn_list != NULL) 368 { 369 const CGEN_INSN *insn = insn_list->insn; 370 CGEN_FIELDS fields; 371 int length; 372 unsigned long insn_value_cropped; 373 374#ifdef CGEN_VALIDATE_INSN_SUPPORTED 375 /* Not needed as insn shouldn't be in hash lists if not supported. */ 376 /* Supported by this cpu? */ 377 if (! xstormy16_cgen_insn_supported (cd, insn)) 378 { 379 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 380 continue; 381 } 382#endif 383 384 /* Basic bit mask must be correct. */ 385 /* ??? May wish to allow target to defer this check until the extract 386 handler. */ 387 388 /* Base size may exceed this instruction's size. Extract the 389 relevant part from the buffer. */ 390 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 391 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 392 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 393 info->endian == BFD_ENDIAN_BIG); 394 else 395 insn_value_cropped = insn_value; 396 397 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 398 == CGEN_INSN_BASE_VALUE (insn)) 399 { 400 /* Printing is handled in two passes. The first pass parses the 401 machine insn and extracts the fields. The second pass prints 402 them. */ 403 404 /* Make sure the entire insn is loaded into insn_value, if it 405 can fit. */ 406 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 407 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 408 { 409 unsigned long full_insn_value; 410 int rc = read_insn (cd, pc, info, buf, 411 CGEN_INSN_BITSIZE (insn) / 8, 412 & ex_info, & full_insn_value); 413 if (rc != 0) 414 return rc; 415 length = CGEN_EXTRACT_FN (cd, insn) 416 (cd, insn, &ex_info, full_insn_value, &fields, pc); 417 } 418 else 419 length = CGEN_EXTRACT_FN (cd, insn) 420 (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 421 422 /* length < 0 -> error */ 423 if (length < 0) 424 return length; 425 if (length > 0) 426 { 427 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 428 /* length is in bits, result is in bytes */ 429 return length / 8; 430 } 431 } 432 433 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 434 } 435 436 return 0; 437} 438 439/* Default value for CGEN_PRINT_INSN. 440 The result is the size of the insn in bytes or zero for an unknown insn 441 or -1 if an error occured fetching bytes. */ 442 443#ifndef CGEN_PRINT_INSN 444#define CGEN_PRINT_INSN default_print_insn 445#endif 446 447static int 448default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 449{ 450 char buf[CGEN_MAX_INSN_SIZE]; 451 int buflen; 452 int status; 453 454 /* Attempt to read the base part of the insn. */ 455 buflen = cd->base_insn_bitsize / 8; 456 status = (*info->read_memory_func) (pc, buf, buflen, info); 457 458 /* Try again with the minimum part, if min < base. */ 459 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 460 { 461 buflen = cd->min_insn_bitsize / 8; 462 status = (*info->read_memory_func) (pc, buf, buflen, info); 463 } 464 465 if (status != 0) 466 { 467 (*info->memory_error_func) (status, pc, info); 468 return -1; 469 } 470 471 return print_insn (cd, pc, info, buf, buflen); 472} 473 474/* Main entry point. 475 Print one instruction from PC on INFO->STREAM. 476 Return the size of the instruction (in bytes). */ 477 478typedef struct cpu_desc_list { 479 struct cpu_desc_list *next; 480 int isa; 481 int mach; 482 int endian; 483 CGEN_CPU_DESC cd; 484} cpu_desc_list; 485 486int 487print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) 488{ 489 static cpu_desc_list *cd_list = 0; 490 cpu_desc_list *cl = 0; 491 static CGEN_CPU_DESC cd = 0; 492 static int prev_isa; 493 static int prev_mach; 494 static int prev_endian; 495 int length; 496 int isa,mach; 497 int endian = (info->endian == BFD_ENDIAN_BIG 498 ? CGEN_ENDIAN_BIG 499 : CGEN_ENDIAN_LITTLE); 500 enum bfd_architecture arch; 501 502 /* ??? gdb will set mach but leave the architecture as "unknown" */ 503#ifndef CGEN_BFD_ARCH 504#define CGEN_BFD_ARCH bfd_arch_xstormy16 505#endif 506 arch = info->arch; 507 if (arch == bfd_arch_unknown) 508 arch = CGEN_BFD_ARCH; 509 510 /* There's no standard way to compute the machine or isa number 511 so we leave it to the target. */ 512#ifdef CGEN_COMPUTE_MACH 513 mach = CGEN_COMPUTE_MACH (info); 514#else 515 mach = info->mach; 516#endif 517 518#ifdef CGEN_COMPUTE_ISA 519 isa = CGEN_COMPUTE_ISA (info); 520#else 521 isa = info->insn_sets; 522#endif 523 524 /* If we've switched cpu's, try to find a handle we've used before */ 525 if (cd 526 && (isa != prev_isa 527 || mach != prev_mach 528 || endian != prev_endian)) 529 { 530 cd = 0; 531 for (cl = cd_list; cl; cl = cl->next) 532 { 533 if (cl->isa == isa && 534 cl->mach == mach && 535 cl->endian == endian) 536 { 537 cd = cl->cd; 538 break; 539 } 540 } 541 } 542 543 /* If we haven't initialized yet, initialize the opcode table. */ 544 if (! cd) 545 { 546 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 547 const char *mach_name; 548 549 if (!arch_type) 550 abort (); 551 mach_name = arch_type->printable_name; 552 553 prev_isa = isa; 554 prev_mach = mach; 555 prev_endian = endian; 556 cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 557 CGEN_CPU_OPEN_BFDMACH, mach_name, 558 CGEN_CPU_OPEN_ENDIAN, prev_endian, 559 CGEN_CPU_OPEN_END); 560 if (!cd) 561 abort (); 562 563 /* save this away for future reference */ 564 cl = xmalloc (sizeof (struct cpu_desc_list)); 565 cl->cd = cd; 566 cl->isa = isa; 567 cl->mach = mach; 568 cl->endian = endian; 569 cl->next = cd_list; 570 cd_list = cl; 571 572 xstormy16_cgen_init_dis (cd); 573 } 574 575 /* We try to have as much common code as possible. 576 But at this point some targets need to take over. */ 577 /* ??? Some targets may need a hook elsewhere. Try to avoid this, 578 but if not possible try to move this hook elsewhere rather than 579 have two hooks. */ 580 length = CGEN_PRINT_INSN (cd, pc, info); 581 if (length > 0) 582 return length; 583 if (length < 0) 584 return -1; 585 586 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 587 return cd->default_insn_bitsize / 8; 588} 589