1/* ia64.h -- Header file for ia64 opcode table 2 Copyright (C) 1998, 1999, 2002 Free Software Foundation, Inc. 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ 4 5#ifndef opcode_ia64_h 6#define opcode_ia64_h 7 8#include <sys/types.h> 9 10#include "bfd.h" 11 12 13typedef BFD_HOST_U_64_BIT ia64_insn; 14 15enum ia64_insn_type 16 { 17 IA64_TYPE_NIL = 0, /* illegal type */ 18 IA64_TYPE_A, /* integer alu (I- or M-unit) */ 19 IA64_TYPE_I, /* non-alu integer (I-unit) */ 20 IA64_TYPE_M, /* memory (M-unit) */ 21 IA64_TYPE_B, /* branch (B-unit) */ 22 IA64_TYPE_F, /* floating-point (F-unit) */ 23 IA64_TYPE_X, /* long encoding (X-unit) */ 24 IA64_TYPE_DYN, /* Dynamic opcode */ 25 IA64_NUM_TYPES 26 }; 27 28enum ia64_unit 29 { 30 IA64_UNIT_NIL = 0, /* illegal unit */ 31 IA64_UNIT_I, /* integer unit */ 32 IA64_UNIT_M, /* memory unit */ 33 IA64_UNIT_B, /* branching unit */ 34 IA64_UNIT_F, /* floating-point unit */ 35 IA64_UNIT_L, /* long "unit" */ 36 IA64_UNIT_X, /* may be integer or branch unit */ 37 IA64_NUM_UNITS 38 }; 39 40/* Changes to this enumeration must be propagated to the operand table in 41 bfd/cpu-ia64-opc.c 42 */ 43enum ia64_opnd 44 { 45 IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 46 47 /* constants */ 48 IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ 49 IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ 50 IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ 51 IA64_OPND_C1, /* the constant 1 */ 52 IA64_OPND_C8, /* the constant 8 */ 53 IA64_OPND_C16, /* the constant 16 */ 54 IA64_OPND_GR0, /* gr0 */ 55 IA64_OPND_IP, /* instruction pointer (ip) */ 56 IA64_OPND_PR, /* predicate register (pr) */ 57 IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ 58 IA64_OPND_PSR, /* processor status register (psr) */ 59 IA64_OPND_PSR_L, /* processor status register L (psr.l) */ 60 IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ 61 62 /* register operands: */ 63 IA64_OPND_AR3, /* third application register # (bits 20-26) */ 64 IA64_OPND_B1, /* branch register # (bits 6-8) */ 65 IA64_OPND_B2, /* branch register # (bits 13-15) */ 66 IA64_OPND_CR3, /* third control register # (bits 20-26) */ 67 IA64_OPND_F1, /* first floating-point register # */ 68 IA64_OPND_F2, /* second floating-point register # */ 69 IA64_OPND_F3, /* third floating-point register # */ 70 IA64_OPND_F4, /* fourth floating-point register # */ 71 IA64_OPND_P1, /* first predicate # */ 72 IA64_OPND_P2, /* second predicate # */ 73 IA64_OPND_R1, /* first register # */ 74 IA64_OPND_R2, /* second register # */ 75 IA64_OPND_R3, /* third register # */ 76 IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ 77 78 /* indirect operands: */ 79 IA64_OPND_CPUID_R3, /* cpuid[reg] */ 80 IA64_OPND_DBR_R3, /* dbr[reg] */ 81 IA64_OPND_DTR_R3, /* dtr[reg] */ 82 IA64_OPND_ITR_R3, /* itr[reg] */ 83 IA64_OPND_IBR_R3, /* ibr[reg] */ 84 IA64_OPND_MR3, /* memory at addr of third register # */ 85 IA64_OPND_MSR_R3, /* msr[reg] */ 86 IA64_OPND_PKR_R3, /* pkr[reg] */ 87 IA64_OPND_PMC_R3, /* pmc[reg] */ 88 IA64_OPND_PMD_R3, /* pmd[reg] */ 89 IA64_OPND_RR_R3, /* rr[reg] */ 90 91 /* immediate operands: */ 92 IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ 93 IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ 94 IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ 95 IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ 96 IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ 97 IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ 98 IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ 99 IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ 100 IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ 101 IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ 102 IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ 103 IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ 104 IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ 105 IA64_OPND_SOF, /* 8-bit stack frame size */ 106 IA64_OPND_SOL, /* 8-bit size of locals */ 107 IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ 108 IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ 109 IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ 110 IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ 111 IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ 112 IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ 113 IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ 114 IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ 115 IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ 116 IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ 117 IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ 118 IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ 119 IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ 120 IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ 121 IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ 122 IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ 123 IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ 124 IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ 125 IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ 126 IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ 127 IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ 128 IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ 129 IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ 130 IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ 131 IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ 132 IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ 133 IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ 134 IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ 135 IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ 136 IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ 137 138 IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ 139 }; 140 141enum ia64_dependency_mode 142{ 143 IA64_DV_RAW, 144 IA64_DV_WAW, 145 IA64_DV_WAR, 146}; 147 148enum ia64_dependency_semantics 149{ 150 IA64_DVS_NONE, 151 IA64_DVS_IMPLIED, 152 IA64_DVS_IMPLIEDF, 153 IA64_DVS_DATA, 154 IA64_DVS_INSTR, 155 IA64_DVS_SPECIFIC, 156 IA64_DVS_STOP, 157 IA64_DVS_OTHER, 158}; 159 160enum ia64_resource_specifier 161{ 162 IA64_RS_ANY, 163 IA64_RS_AR_K, 164 IA64_RS_AR_UNAT, 165 IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ 166 IA64_RS_ARb, /* 48-63, 112-127 */ 167 IA64_RS_BR, 168 IA64_RS_CFM, 169 IA64_RS_CPUID, 170 IA64_RS_CR_IRR, 171 IA64_RS_CR_LRR, 172 IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */ 173 IA64_RS_DBR, 174 IA64_RS_FR, 175 IA64_RS_FRb, 176 IA64_RS_GR0, 177 IA64_RS_GR, 178 IA64_RS_IBR, 179 IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ 180 IA64_RS_MSR, 181 IA64_RS_PKR, 182 IA64_RS_PMC, 183 IA64_RS_PMD, 184 IA64_RS_PR, /* non-rotating, 1-15 */ 185 IA64_RS_PRr, /* rotating, 16-62 */ 186 IA64_RS_PR63, 187 IA64_RS_RR, 188 189 IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ 190 IA64_RS_CRX, /* CRs not in RS_CR */ 191 IA64_RS_PSR, /* PSR bits */ 192 IA64_RS_RSE, /* implementation-specific RSE resources */ 193 IA64_RS_AR_FPSR, 194}; 195 196enum ia64_rse_resource 197{ 198 IA64_RSE_N_STACKED_PHYS, 199 IA64_RSE_BOF, 200 IA64_RSE_STORE_REG, 201 IA64_RSE_LOAD_REG, 202 IA64_RSE_BSPLOAD, 203 IA64_RSE_RNATBITINDEX, 204 IA64_RSE_CFLE, 205 IA64_RSE_NDIRTY, 206}; 207 208/* Information about a given resource dependency */ 209struct ia64_dependency 210{ 211 /* Name of the resource */ 212 const char *name; 213 /* Does this dependency need further specification? */ 214 enum ia64_resource_specifier specifier; 215 /* Mode of dependency */ 216 enum ia64_dependency_mode mode; 217 /* Dependency semantics */ 218 enum ia64_dependency_semantics semantics; 219 /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ 220#define REG_NONE (-1) 221 int regindex; 222 /* Special info on semantics */ 223 const char *info; 224}; 225 226/* Two arrays of indexes into the ia64_dependency table. 227 chks are dependencies to check for conflicts when an opcode is 228 encountered; regs are dependencies to register (mark as used) when an 229 opcode is used. chks correspond to readers (RAW) or writers (WAW or 230 WAR) of a resource, while regs correspond to writers (RAW or WAW) and 231 readers (WAR) of a resource. */ 232struct ia64_opcode_dependency 233{ 234 int nchks; 235 const unsigned short *chks; 236 int nregs; 237 const unsigned short *regs; 238}; 239 240/* encode/extract the note/index for a dependency */ 241#define RDEP(N,X) (((N)<<11)|(X)) 242#define NOTE(X) (((X)>>11)&0x1F) 243#define DEP(X) ((X)&0x7FF) 244 245/* A template descriptor describes the execution units that are active 246 for each of the three slots. It also specifies the location of 247 instruction group boundaries that may be present between two slots. */ 248struct ia64_templ_desc 249 { 250 int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ 251 enum ia64_unit exec_unit[3]; 252 const char *name; 253 }; 254 255/* The opcode table is an array of struct ia64_opcode. */ 256 257struct ia64_opcode 258 { 259 /* The opcode name. */ 260 const char *name; 261 262 /* The type of the instruction: */ 263 enum ia64_insn_type type; 264 265 /* Number of output operands: */ 266 int num_outputs; 267 268 /* The opcode itself. Those bits which will be filled in with 269 operands are zeroes. */ 270 ia64_insn opcode; 271 272 /* The opcode mask. This is used by the disassembler. This is a 273 mask containing ones indicating those bits which must match the 274 opcode field, and zeroes indicating those bits which need not 275 match (and are presumably filled in by operands). */ 276 ia64_insn mask; 277 278 /* An array of operand codes. Each code is an index into the 279 operand table. They appear in the order which the operands must 280 appear in assembly code, and are terminated by a zero. */ 281 enum ia64_opnd operands[5]; 282 283 /* One bit flags for the opcode. These are primarily used to 284 indicate specific processors and environments support the 285 instructions. The defined values are listed below. */ 286 unsigned int flags; 287 288 /* Used by ia64_find_next_opcode (). */ 289 short ent_index; 290 291 /* Opcode dependencies. */ 292 const struct ia64_opcode_dependency *dependencies; 293 }; 294 295/* Values defined for the flags field of a struct ia64_opcode. */ 296 297#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ 298#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ 299#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ 300#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ 301#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ 302#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ 303#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ 304#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ 305#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ 306#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ 307#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ 308 309/* A macro to extract the major opcode from an instruction. */ 310#define IA64_OP(i) (((i) >> 37) & 0xf) 311 312enum ia64_operand_class 313 { 314 IA64_OPND_CLASS_CST, /* constant */ 315 IA64_OPND_CLASS_REG, /* register */ 316 IA64_OPND_CLASS_IND, /* indirect register */ 317 IA64_OPND_CLASS_ABS, /* absolute value */ 318 IA64_OPND_CLASS_REL, /* IP-relative value */ 319 }; 320 321/* The operands table is an array of struct ia64_operand. */ 322 323struct ia64_operand 324{ 325 enum ia64_operand_class class; 326 327 /* Set VALUE as the operand bits for the operand of type SELF in the 328 instruction pointed to by CODE. If an error occurs, *CODE is not 329 modified and the returned string describes the cause of the 330 error. If no error occurs, NULL is returned. */ 331 const char *(*insert) (const struct ia64_operand *self, ia64_insn value, 332 ia64_insn *code); 333 334 /* Extract the operand bits for an operand of type SELF from 335 instruction CODE store them in *VALUE. If an error occurs, the 336 cause of the error is described by the string returned. If no 337 error occurs, NULL is returned. */ 338 const char *(*extract) (const struct ia64_operand *self, ia64_insn code, 339 ia64_insn *value); 340 341 /* A string whose meaning depends on the operand class. */ 342 343 const char *str; 344 345 struct bit_field 346 { 347 /* The number of bits in the operand. */ 348 int bits; 349 350 /* How far the operand is left shifted in the instruction. */ 351 int shift; 352 } 353 field[4]; /* no operand has more than this many bit-fields */ 354 355 unsigned int flags; 356 357 const char *desc; /* brief description */ 358}; 359 360/* Values defined for the flags field of a struct ia64_operand. */ 361 362/* Disassemble as signed decimal (instead of hex): */ 363#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) 364/* Disassemble as unsigned decimal (instead of hex): */ 365#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) 366 367extern const struct ia64_templ_desc ia64_templ_desc[16]; 368 369/* The tables are sorted by major opcode number and are otherwise in 370 the order in which the disassembler should consider instructions. */ 371extern struct ia64_opcode ia64_opcodes_a[]; 372extern struct ia64_opcode ia64_opcodes_i[]; 373extern struct ia64_opcode ia64_opcodes_m[]; 374extern struct ia64_opcode ia64_opcodes_b[]; 375extern struct ia64_opcode ia64_opcodes_f[]; 376extern struct ia64_opcode ia64_opcodes_d[]; 377 378 379extern struct ia64_opcode *ia64_find_opcode (const char *name); 380extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent); 381 382extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn, 383 enum ia64_insn_type type); 384 385extern void ia64_free_opcode (struct ia64_opcode *ent); 386extern const struct ia64_dependency *ia64_find_dependency (int index); 387 388/* To avoid circular library dependencies, this array is implemented 389 in bfd/cpu-ia64-opc.c: */ 390extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; 391 392#endif /* opcode_ia64_h */ 393