1/* Target-dependent code for Renesas D10V, for GDB. 2 3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software 4 Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23/* Contributed by Martin Hunt, hunt@cygnus.com */ 24 25#include "defs.h" 26#include "frame.h" 27#include "frame-unwind.h" 28#include "frame-base.h" 29#include "symtab.h" 30#include "gdbtypes.h" 31#include "gdbcmd.h" 32#include "gdbcore.h" 33#include "gdb_string.h" 34#include "value.h" 35#include "inferior.h" 36#include "dis-asm.h" 37#include "symfile.h" 38#include "objfiles.h" 39#include "language.h" 40#include "arch-utils.h" 41#include "regcache.h" 42#include "remote.h" 43#include "floatformat.h" 44#include "gdb/sim-d10v.h" 45#include "sim-regno.h" 46#include "disasm.h" 47#include "trad-frame.h" 48 49#include "gdb_assert.h" 50 51struct gdbarch_tdep 52 { 53 int a0_regnum; 54 int nr_dmap_regs; 55 unsigned long (*dmap_register) (void *regcache, int nr); 56 unsigned long (*imap_register) (void *regcache, int nr); 57 }; 58 59/* These are the addresses the D10V-EVA board maps data and 60 instruction memory to. */ 61 62enum memspace { 63 DMEM_START = 0x2000000, 64 IMEM_START = 0x1000000, 65 STACK_START = 0x200bffe 66}; 67 68/* d10v register names. */ 69 70enum 71 { 72 R0_REGNUM = 0, 73 R3_REGNUM = 3, 74 D10V_FP_REGNUM = 11, 75 LR_REGNUM = 13, 76 D10V_SP_REGNUM = 15, 77 PSW_REGNUM = 16, 78 D10V_PC_REGNUM = 18, 79 NR_IMAP_REGS = 2, 80 NR_A_REGS = 2, 81 TS2_NUM_REGS = 37, 82 TS3_NUM_REGS = 42, 83 /* d10v calling convention. */ 84 ARG1_REGNUM = R0_REGNUM, 85 ARGN_REGNUM = R3_REGNUM 86 }; 87 88static int 89nr_dmap_regs (struct gdbarch *gdbarch) 90{ 91 return gdbarch_tdep (gdbarch)->nr_dmap_regs; 92} 93 94static int 95a0_regnum (struct gdbarch *gdbarch) 96{ 97 return gdbarch_tdep (gdbarch)->a0_regnum; 98} 99 100/* Local functions */ 101 102extern void _initialize_d10v_tdep (void); 103 104static void d10v_eva_prepare_to_trace (void); 105 106static void d10v_eva_get_trace_data (void); 107 108static CORE_ADDR 109d10v_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 110{ 111 /* Align to the size of an instruction (so that they can safely be 112 pushed onto the stack. */ 113 return sp & ~3; 114} 115 116static const unsigned char * 117d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) 118{ 119 static unsigned char breakpoint[] = 120 {0x2f, 0x90, 0x5e, 0x00}; 121 *lenptr = sizeof (breakpoint); 122 return breakpoint; 123} 124 125/* Map the REG_NR onto an ascii name. Return NULL or an empty string 126 when the reg_nr isn't valid. */ 127 128enum ts2_regnums 129 { 130 TS2_IMAP0_REGNUM = 32, 131 TS2_DMAP_REGNUM = 34, 132 TS2_NR_DMAP_REGS = 1, 133 TS2_A0_REGNUM = 35 134 }; 135 136static const char * 137d10v_ts2_register_name (int reg_nr) 138{ 139 static char *register_names[] = 140 { 141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 143 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", 144 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", 145 "imap0", "imap1", "dmap", "a0", "a1" 146 }; 147 if (reg_nr < 0) 148 return NULL; 149 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 150 return NULL; 151 return register_names[reg_nr]; 152} 153 154enum ts3_regnums 155 { 156 TS3_IMAP0_REGNUM = 36, 157 TS3_DMAP0_REGNUM = 38, 158 TS3_NR_DMAP_REGS = 4, 159 TS3_A0_REGNUM = 32 160 }; 161 162static const char * 163d10v_ts3_register_name (int reg_nr) 164{ 165 static char *register_names[] = 166 { 167 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 168 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 169 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", 170 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", 171 "a0", "a1", 172 "spi", "spu", 173 "imap0", "imap1", 174 "dmap0", "dmap1", "dmap2", "dmap3" 175 }; 176 if (reg_nr < 0) 177 return NULL; 178 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 179 return NULL; 180 return register_names[reg_nr]; 181} 182 183/* Access the DMAP/IMAP registers in a target independent way. 184 185 Divide the D10V's 64k data space into four 16k segments: 186 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and 187 0xc000 -- 0xffff. 188 189 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- 190 0x7fff) always map to the on-chip data RAM, and the fourth always 191 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into 192 unified memory or instruction memory, under the control of the 193 single DMAP register. 194 195 On the TS3, there are four DMAP registers, each of which controls 196 one of the segments. */ 197 198static unsigned long 199d10v_ts2_dmap_register (void *regcache, int reg_nr) 200{ 201 switch (reg_nr) 202 { 203 case 0: 204 case 1: 205 return 0x2000; 206 case 2: 207 { 208 ULONGEST reg; 209 regcache_cooked_read_unsigned (regcache, TS2_DMAP_REGNUM, ®); 210 return reg; 211 } 212 default: 213 return 0; 214 } 215} 216 217static unsigned long 218d10v_ts3_dmap_register (void *regcache, int reg_nr) 219{ 220 ULONGEST reg; 221 regcache_cooked_read_unsigned (regcache, TS3_DMAP0_REGNUM + reg_nr, ®); 222 return reg; 223} 224 225static unsigned long 226d10v_ts2_imap_register (void *regcache, int reg_nr) 227{ 228 ULONGEST reg; 229 regcache_cooked_read_unsigned (regcache, TS2_IMAP0_REGNUM + reg_nr, ®); 230 return reg; 231} 232 233static unsigned long 234d10v_ts3_imap_register (void *regcache, int reg_nr) 235{ 236 ULONGEST reg; 237 regcache_cooked_read_unsigned (regcache, TS3_IMAP0_REGNUM + reg_nr, ®); 238 return reg; 239} 240 241/* MAP GDB's internal register numbering (determined by the layout 242 from the DEPRECATED_REGISTER_BYTE array) onto the simulator's 243 register numbering. */ 244 245static int 246d10v_ts2_register_sim_regno (int nr) 247{ 248 /* Only makes sense to supply raw registers. */ 249 gdb_assert (nr >= 0 && nr < NUM_REGS); 250 if (nr >= TS2_IMAP0_REGNUM 251 && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) 252 return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; 253 if (nr == TS2_DMAP_REGNUM) 254 return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; 255 if (nr >= TS2_A0_REGNUM 256 && nr < TS2_A0_REGNUM + NR_A_REGS) 257 return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; 258 return nr; 259} 260 261static int 262d10v_ts3_register_sim_regno (int nr) 263{ 264 /* Only makes sense to supply raw registers. */ 265 gdb_assert (nr >= 0 && nr < NUM_REGS); 266 if (nr >= TS3_IMAP0_REGNUM 267 && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) 268 return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; 269 if (nr >= TS3_DMAP0_REGNUM 270 && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) 271 return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; 272 if (nr >= TS3_A0_REGNUM 273 && nr < TS3_A0_REGNUM + NR_A_REGS) 274 return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; 275 return nr; 276} 277 278/* Return the GDB type object for the "standard" data type 279 of data in register N. */ 280 281static struct type * 282d10v_register_type (struct gdbarch *gdbarch, int reg_nr) 283{ 284 if (reg_nr == D10V_PC_REGNUM) 285 return builtin_type (gdbarch)->builtin_func_ptr; 286 if (reg_nr == D10V_SP_REGNUM || reg_nr == D10V_FP_REGNUM) 287 return builtin_type (gdbarch)->builtin_data_ptr; 288 else if (reg_nr >= a0_regnum (gdbarch) 289 && reg_nr < (a0_regnum (gdbarch) + NR_A_REGS)) 290 return builtin_type_int64; 291 else 292 return builtin_type_int16; 293} 294 295static int 296d10v_iaddr_p (CORE_ADDR x) 297{ 298 return (((x) & 0x3000000) == IMEM_START); 299} 300 301static CORE_ADDR 302d10v_make_daddr (CORE_ADDR x) 303{ 304 return ((x) | DMEM_START); 305} 306 307static CORE_ADDR 308d10v_make_iaddr (CORE_ADDR x) 309{ 310 if (d10v_iaddr_p (x)) 311 return x; /* Idempotency -- x is already in the IMEM space. */ 312 else 313 return (((x) << 2) | IMEM_START); 314} 315 316static CORE_ADDR 317d10v_convert_iaddr_to_raw (CORE_ADDR x) 318{ 319 return (((x) >> 2) & 0xffff); 320} 321 322static CORE_ADDR 323d10v_convert_daddr_to_raw (CORE_ADDR x) 324{ 325 return ((x) & 0xffff); 326} 327 328static void 329d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) 330{ 331 /* Is it a code address? */ 332 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC 333 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) 334 { 335 store_unsigned_integer (buf, TYPE_LENGTH (type), 336 d10v_convert_iaddr_to_raw (addr)); 337 } 338 else 339 { 340 /* Strip off any upper segment bits. */ 341 store_unsigned_integer (buf, TYPE_LENGTH (type), 342 d10v_convert_daddr_to_raw (addr)); 343 } 344} 345 346static CORE_ADDR 347d10v_pointer_to_address (struct type *type, const void *buf) 348{ 349 CORE_ADDR addr = extract_unsigned_integer (buf, TYPE_LENGTH (type)); 350 /* Is it a code address? */ 351 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC 352 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD 353 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) 354 return d10v_make_iaddr (addr); 355 else 356 return d10v_make_daddr (addr); 357} 358 359/* Don't do anything if we have an integer, this way users can type 'x 360 <addr>' w/o having gdb outsmart them. The internal gdb conversions 361 to the correct space are taken care of in the pointer_to_address 362 function. If we don't do this, 'x $fp' wouldn't work. */ 363static CORE_ADDR 364d10v_integer_to_address (struct type *type, void *buf) 365{ 366 LONGEST val; 367 val = unpack_long (type, buf); 368 return val; 369} 370 371/* Handle the d10v's return_value convention. */ 372 373static enum return_value_convention 374d10v_return_value (struct gdbarch *gdbarch, struct type *valtype, 375 struct regcache *regcache, void *readbuf, 376 const void *writebuf) 377{ 378 if (TYPE_LENGTH (valtype) > 8) 379 /* Anything larger than 8 bytes (4 registers) goes on the stack. */ 380 return RETURN_VALUE_STRUCT_CONVENTION; 381 if (TYPE_LENGTH (valtype) == 5 382 || TYPE_LENGTH (valtype) == 6) 383 /* Anything 5 or 6 bytes in size goes in memory. Contents don't 384 appear to matter. Note that 7 and 8 byte objects do end up in 385 registers! */ 386 return RETURN_VALUE_STRUCT_CONVENTION; 387 if (TYPE_LENGTH (valtype) == 1) 388 { 389 /* All single byte values go in a register stored right-aligned. 390 Note: 2 byte integer values are handled further down. */ 391 if (readbuf) 392 { 393 /* Since TYPE is smaller than the register, there isn't a 394 sign extension problem. Let the extraction truncate the 395 register value. */ 396 ULONGEST regval; 397 regcache_cooked_read_unsigned (regcache, R0_REGNUM, 398 ®val); 399 store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval); 400 401 } 402 if (writebuf) 403 { 404 ULONGEST regval; 405 if (TYPE_CODE (valtype) == TYPE_CODE_INT) 406 /* Some sort of integer value stored in R0. Use 407 unpack_long since that should handle any required sign 408 extension. */ 409 regval = unpack_long (valtype, writebuf); 410 else 411 /* Some other type. Don't sign-extend the value when 412 storing it in the register. */ 413 regval = extract_unsigned_integer (writebuf, 1); 414 regcache_cooked_write_unsigned (regcache, R0_REGNUM, regval); 415 } 416 return RETURN_VALUE_REGISTER_CONVENTION; 417 } 418 if ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT 419 || TYPE_CODE (valtype) == TYPE_CODE_UNION) 420 && TYPE_NFIELDS (valtype) > 1 421 && TYPE_FIELD_BITPOS (valtype, 1) == 8) 422 /* If a composite is 8 bit aligned (determined by looking at the 423 start address of the second field), put it in memory. */ 424 return RETURN_VALUE_STRUCT_CONVENTION; 425 /* Assume it is in registers. */ 426 if (writebuf || readbuf) 427 { 428 int reg; 429 /* Per above, the value is never more than 8 bytes long. */ 430 gdb_assert (TYPE_LENGTH (valtype) <= 8); 431 /* Xfer 2 bytes at a time. */ 432 for (reg = 0; (reg * 2) + 1 < TYPE_LENGTH (valtype); reg++) 433 { 434 if (readbuf) 435 regcache_cooked_read (regcache, R0_REGNUM + reg, 436 (bfd_byte *) readbuf + reg * 2); 437 if (writebuf) 438 regcache_cooked_write (regcache, R0_REGNUM + reg, 439 (bfd_byte *) writebuf + reg * 2); 440 } 441 /* Any trailing byte ends up _left_ aligned. */ 442 if ((reg * 2) < TYPE_LENGTH (valtype)) 443 { 444 if (readbuf) 445 regcache_cooked_read_part (regcache, R0_REGNUM + reg, 446 0, 1, (bfd_byte *) readbuf + reg * 2); 447 if (writebuf) 448 regcache_cooked_write_part (regcache, R0_REGNUM + reg, 449 0, 1, (bfd_byte *) writebuf + reg * 2); 450 } 451 } 452 return RETURN_VALUE_REGISTER_CONVENTION; 453} 454 455static int 456check_prologue (unsigned short op) 457{ 458 /* st rn, @-sp */ 459 if ((op & 0x7E1F) == 0x6C1F) 460 return 1; 461 462 /* st2w rn, @-sp */ 463 if ((op & 0x7E3F) == 0x6E1F) 464 return 1; 465 466 /* subi sp, n */ 467 if ((op & 0x7FE1) == 0x01E1) 468 return 1; 469 470 /* mv r11, sp */ 471 if (op == 0x417E) 472 return 1; 473 474 /* nop */ 475 if (op == 0x5E00) 476 return 1; 477 478 /* st rn, @sp */ 479 if ((op & 0x7E1F) == 0x681E) 480 return 1; 481 482 /* st2w rn, @sp */ 483 if ((op & 0x7E3F) == 0x3A1E) 484 return 1; 485 486 return 0; 487} 488 489static CORE_ADDR 490d10v_skip_prologue (CORE_ADDR pc) 491{ 492 unsigned long op; 493 unsigned short op1, op2; 494 CORE_ADDR func_addr, func_end; 495 struct symtab_and_line sal; 496 497 /* If we have line debugging information, then the end of the prologue 498 should be the first assembly instruction of the first source line. */ 499 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 500 { 501 sal = find_pc_line (func_addr, 0); 502 if (sal.end && sal.end < func_end) 503 return sal.end; 504 } 505 506 if (target_read_memory (pc, (char *) &op, 4)) 507 return pc; /* Can't access it -- assume no prologue. */ 508 509 while (1) 510 { 511 op = (unsigned long) read_memory_integer (pc, 4); 512 if ((op & 0xC0000000) == 0xC0000000) 513 { 514 /* long instruction */ 515 if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ 516 ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ 517 ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ 518 break; 519 } 520 else 521 { 522 /* short instructions */ 523 if ((op & 0xC0000000) == 0x80000000) 524 { 525 op2 = (op & 0x3FFF8000) >> 15; 526 op1 = op & 0x7FFF; 527 } 528 else 529 { 530 op1 = (op & 0x3FFF8000) >> 15; 531 op2 = op & 0x7FFF; 532 } 533 if (check_prologue (op1)) 534 { 535 if (!check_prologue (op2)) 536 { 537 /* If the previous opcode was really part of the 538 prologue and not just a NOP, then we want to 539 break after both instructions. */ 540 if (op1 != 0x5E00) 541 pc += 4; 542 break; 543 } 544 } 545 else 546 break; 547 } 548 pc += 4; 549 } 550 return pc; 551} 552 553struct d10v_unwind_cache 554{ 555 /* The previous frame's inner most stack address. Used as this 556 frame ID's stack_addr. */ 557 CORE_ADDR prev_sp; 558 /* The frame's base, optionally used by the high-level debug info. */ 559 CORE_ADDR base; 560 int size; 561 /* How far the SP and r11 (FP) have been offset from the start of 562 the stack frame (as defined by the previous frame's stack 563 pointer). */ 564 LONGEST sp_offset; 565 LONGEST r11_offset; 566 int uses_frame; 567 /* Table indicating the location of each and every register. */ 568 struct trad_frame_saved_reg *saved_regs; 569}; 570 571static int 572prologue_find_regs (struct d10v_unwind_cache *info, unsigned short op, 573 CORE_ADDR addr) 574{ 575 int n; 576 577 /* st rn, @-sp */ 578 if ((op & 0x7E1F) == 0x6C1F) 579 { 580 n = (op & 0x1E0) >> 5; 581 info->sp_offset -= 2; 582 info->saved_regs[n].addr = info->sp_offset; 583 return 1; 584 } 585 586 /* st2w rn, @-sp */ 587 else if ((op & 0x7E3F) == 0x6E1F) 588 { 589 n = (op & 0x1E0) >> 5; 590 info->sp_offset -= 4; 591 info->saved_regs[n + 0].addr = info->sp_offset + 0; 592 info->saved_regs[n + 1].addr = info->sp_offset + 2; 593 return 1; 594 } 595 596 /* subi sp, n */ 597 if ((op & 0x7FE1) == 0x01E1) 598 { 599 n = (op & 0x1E) >> 1; 600 if (n == 0) 601 n = 16; 602 info->sp_offset -= n; 603 return 1; 604 } 605 606 /* mv r11, sp */ 607 if (op == 0x417E) 608 { 609 info->uses_frame = 1; 610 info->r11_offset = info->sp_offset; 611 return 1; 612 } 613 614 /* st rn, @r11 */ 615 if ((op & 0x7E1F) == 0x6816) 616 { 617 n = (op & 0x1E0) >> 5; 618 info->saved_regs[n].addr = info->r11_offset; 619 return 1; 620 } 621 622 /* nop */ 623 if (op == 0x5E00) 624 return 1; 625 626 /* st rn, @sp */ 627 if ((op & 0x7E1F) == 0x681E) 628 { 629 n = (op & 0x1E0) >> 5; 630 info->saved_regs[n].addr = info->sp_offset; 631 return 1; 632 } 633 634 /* st2w rn, @sp */ 635 if ((op & 0x7E3F) == 0x3A1E) 636 { 637 n = (op & 0x1E0) >> 5; 638 info->saved_regs[n + 0].addr = info->sp_offset + 0; 639 info->saved_regs[n + 1].addr = info->sp_offset + 2; 640 return 1; 641 } 642 643 return 0; 644} 645 646/* Put here the code to store, into fi->saved_regs, the addresses of 647 the saved registers of frame described by FRAME_INFO. This 648 includes special registers such as pc and fp saved in special ways 649 in the stack frame. sp is even more special: the address we return 650 for it IS the sp for the next frame. */ 651 652static struct d10v_unwind_cache * 653d10v_frame_unwind_cache (struct frame_info *next_frame, 654 void **this_prologue_cache) 655{ 656 struct gdbarch *gdbarch = get_frame_arch (next_frame); 657 CORE_ADDR pc; 658 ULONGEST prev_sp; 659 ULONGEST this_base; 660 unsigned long op; 661 unsigned short op1, op2; 662 int i; 663 struct d10v_unwind_cache *info; 664 665 if ((*this_prologue_cache)) 666 return (*this_prologue_cache); 667 668 info = FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache); 669 (*this_prologue_cache) = info; 670 info->saved_regs = trad_frame_alloc_saved_regs (next_frame); 671 672 info->size = 0; 673 info->sp_offset = 0; 674 675 info->uses_frame = 0; 676 for (pc = frame_func_unwind (next_frame); 677 pc > 0 && pc < frame_pc_unwind (next_frame); 678 pc += 4) 679 { 680 op = get_frame_memory_unsigned (next_frame, pc, 4); 681 if ((op & 0xC0000000) == 0xC0000000) 682 { 683 /* long instruction */ 684 if ((op & 0x3FFF0000) == 0x01FF0000) 685 { 686 /* add3 sp,sp,n */ 687 short n = op & 0xFFFF; 688 info->sp_offset += n; 689 } 690 else if ((op & 0x3F0F0000) == 0x340F0000) 691 { 692 /* st rn, @(offset,sp) */ 693 short offset = op & 0xFFFF; 694 short n = (op >> 20) & 0xF; 695 info->saved_regs[n].addr = info->sp_offset + offset; 696 } 697 else if ((op & 0x3F1F0000) == 0x350F0000) 698 { 699 /* st2w rn, @(offset,sp) */ 700 short offset = op & 0xFFFF; 701 short n = (op >> 20) & 0xF; 702 info->saved_regs[n + 0].addr = info->sp_offset + offset + 0; 703 info->saved_regs[n + 1].addr = info->sp_offset + offset + 2; 704 } 705 else 706 break; 707 } 708 else 709 { 710 /* short instructions */ 711 if ((op & 0xC0000000) == 0x80000000) 712 { 713 op2 = (op & 0x3FFF8000) >> 15; 714 op1 = op & 0x7FFF; 715 } 716 else 717 { 718 op1 = (op & 0x3FFF8000) >> 15; 719 op2 = op & 0x7FFF; 720 } 721 if (!prologue_find_regs (info, op1, pc) 722 || !prologue_find_regs (info, op2, pc)) 723 break; 724 } 725 } 726 727 info->size = -info->sp_offset; 728 729 /* Compute the previous frame's stack pointer (which is also the 730 frame's ID's stack address), and this frame's base pointer. */ 731 if (info->uses_frame) 732 { 733 /* The SP was moved to the FP. This indicates that a new frame 734 was created. Get THIS frame's FP value by unwinding it from 735 the next frame. */ 736 frame_unwind_unsigned_register (next_frame, D10V_FP_REGNUM, &this_base); 737 /* The FP points at the last saved register. Adjust the FP back 738 to before the first saved register giving the SP. */ 739 prev_sp = this_base + info->size; 740 } 741 else 742 { 743 /* Assume that the FP is this frame's SP but with that pushed 744 stack space added back. */ 745 frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &this_base); 746 prev_sp = this_base + info->size; 747 } 748 749 /* Convert that SP/BASE into real addresses. */ 750 info->prev_sp = d10v_make_daddr (prev_sp); 751 info->base = d10v_make_daddr (this_base); 752 753 /* Adjust all the saved registers so that they contain addresses and 754 not offsets. */ 755 for (i = 0; i < NUM_REGS - 1; i++) 756 if (trad_frame_addr_p (info->saved_regs, i)) 757 { 758 info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); 759 } 760 761 /* The call instruction moves the caller's PC in the callee's LR. 762 Since this is an unwind, do the reverse. Copy the location of LR 763 into PC (the address / regnum) so that a request for PC will be 764 converted into a request for the LR. */ 765 info->saved_regs[D10V_PC_REGNUM] = info->saved_regs[LR_REGNUM]; 766 767 /* The previous frame's SP needed to be computed. Save the computed 768 value. */ 769 trad_frame_set_value (info->saved_regs, D10V_SP_REGNUM, 770 d10v_make_daddr (prev_sp)); 771 772 return info; 773} 774 775static void 776d10v_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, 777 struct frame_info *frame, int regnum, int all) 778{ 779 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 780 if (regnum >= 0) 781 { 782 default_print_registers_info (gdbarch, file, frame, regnum, all); 783 return; 784 } 785 786 { 787 ULONGEST pc, psw, rpt_s, rpt_e, rpt_c; 788 pc = get_frame_register_unsigned (frame, D10V_PC_REGNUM); 789 psw = get_frame_register_unsigned (frame, PSW_REGNUM); 790 rpt_s = get_frame_register_unsigned (frame, frame_map_name_to_regnum (frame, "rpt_s", -1)); 791 rpt_e = get_frame_register_unsigned (frame, frame_map_name_to_regnum (frame, "rpt_e", -1)); 792 rpt_c = get_frame_register_unsigned (frame, frame_map_name_to_regnum (frame, "rpt_c", -1)); 793 fprintf_filtered (file, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", 794 (long) pc, (long) d10v_make_iaddr (pc), (long) psw, 795 (long) rpt_s, (long) rpt_e, (long) rpt_c); 796 } 797 798 { 799 int group; 800 for (group = 0; group < 16; group += 8) 801 { 802 int r; 803 fprintf_filtered (file, "R%d-R%-2d", group, group + 7); 804 for (r = group; r < group + 8; r++) 805 { 806 ULONGEST tmp; 807 tmp = get_frame_register_unsigned (frame, r); 808 fprintf_filtered (file, " %04lx", (long) tmp); 809 } 810 fprintf_filtered (file, "\n"); 811 } 812 } 813 814 /* Note: The IMAP/DMAP registers don't participate in function 815 calls. Don't bother trying to unwind them. */ 816 817 { 818 int a; 819 for (a = 0; a < NR_IMAP_REGS; a++) 820 { 821 if (a > 0) 822 fprintf_filtered (file, " "); 823 fprintf_filtered (file, "IMAP%d %04lx", a, 824 tdep->imap_register (current_regcache, a)); 825 } 826 if (nr_dmap_regs (gdbarch) == 1) 827 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */ 828 fprintf_filtered (file, " DMAP %04lx\n", 829 tdep->dmap_register (current_regcache, 2)); 830 else 831 { 832 for (a = 0; a < nr_dmap_regs (gdbarch); a++) 833 { 834 fprintf_filtered (file, " DMAP%d %04lx", a, 835 tdep->dmap_register (current_regcache, a)); 836 } 837 fprintf_filtered (file, "\n"); 838 } 839 } 840 841 { 842 char num[MAX_REGISTER_SIZE]; 843 int a; 844 fprintf_filtered (file, "A0-A%d", NR_A_REGS - 1); 845 for (a = a0_regnum (gdbarch); a < a0_regnum (gdbarch) + NR_A_REGS; a++) 846 { 847 int i; 848 fprintf_filtered (file, " "); 849 get_frame_register (frame, a, num); 850 for (i = 0; i < register_size (gdbarch, a); i++) 851 { 852 fprintf_filtered (file, "%02x", (num[i] & 0xff)); 853 } 854 } 855 } 856 fprintf_filtered (file, "\n"); 857} 858 859static void 860show_regs (char *args, int from_tty) 861{ 862 d10v_print_registers_info (current_gdbarch, gdb_stdout, 863 get_current_frame (), -1, 1); 864} 865 866static CORE_ADDR 867d10v_read_pc (ptid_t ptid) 868{ 869 ptid_t save_ptid; 870 CORE_ADDR pc; 871 CORE_ADDR retval; 872 873 save_ptid = inferior_ptid; 874 inferior_ptid = ptid; 875 pc = (int) read_register (D10V_PC_REGNUM); 876 inferior_ptid = save_ptid; 877 retval = d10v_make_iaddr (pc); 878 return retval; 879} 880 881static void 882d10v_write_pc (CORE_ADDR val, ptid_t ptid) 883{ 884 ptid_t save_ptid; 885 886 save_ptid = inferior_ptid; 887 inferior_ptid = ptid; 888 write_register (D10V_PC_REGNUM, d10v_convert_iaddr_to_raw (val)); 889 inferior_ptid = save_ptid; 890} 891 892static CORE_ADDR 893d10v_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 894{ 895 ULONGEST sp; 896 frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &sp); 897 return d10v_make_daddr (sp); 898} 899 900/* When arguments must be pushed onto the stack, they go on in reverse 901 order. The below implements a FILO (stack) to do this. */ 902 903struct stack_item 904{ 905 int len; 906 struct stack_item *prev; 907 void *data; 908}; 909 910static struct stack_item *push_stack_item (struct stack_item *prev, 911 void *contents, int len); 912static struct stack_item * 913push_stack_item (struct stack_item *prev, void *contents, int len) 914{ 915 struct stack_item *si; 916 si = xmalloc (sizeof (struct stack_item)); 917 si->data = xmalloc (len); 918 si->len = len; 919 si->prev = prev; 920 memcpy (si->data, contents, len); 921 return si; 922} 923 924static struct stack_item *pop_stack_item (struct stack_item *si); 925static struct stack_item * 926pop_stack_item (struct stack_item *si) 927{ 928 struct stack_item *dead = si; 929 si = si->prev; 930 xfree (dead->data); 931 xfree (dead); 932 return si; 933} 934 935 936static CORE_ADDR 937d10v_push_dummy_code (struct gdbarch *gdbarch, 938 CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, 939 struct value **args, int nargs, 940 struct type *value_type, 941 CORE_ADDR *real_pc, CORE_ADDR *bp_addr) 942{ 943 /* Allocate space sufficient for a breakpoint. */ 944 sp = (sp - 4) & ~3; 945 /* Store the address of that breakpoint taking care to first convert 946 it into a code (IADDR) address from a stack (DADDR) address. 947 This of course assumes that the two virtual addresses map onto 948 the same real address. */ 949 (*bp_addr) = d10v_make_iaddr (d10v_convert_iaddr_to_raw (sp)); 950 /* d10v always starts the call at the callee's entry point. */ 951 (*real_pc) = funaddr; 952 return sp; 953} 954 955static CORE_ADDR 956d10v_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 957 struct regcache *regcache, CORE_ADDR bp_addr, 958 int nargs, struct value **args, CORE_ADDR sp, 959 int struct_return, CORE_ADDR struct_addr) 960{ 961 int i; 962 int regnum = ARG1_REGNUM; 963 struct stack_item *si = NULL; 964 long val; 965 966 /* Set the return address. For the d10v, the return breakpoint is 967 always at BP_ADDR. */ 968 regcache_cooked_write_unsigned (regcache, LR_REGNUM, 969 d10v_convert_iaddr_to_raw (bp_addr)); 970 971 /* If STRUCT_RETURN is true, then the struct return address (in 972 STRUCT_ADDR) will consume the first argument-passing register. 973 Both adjust the register count and store that value. */ 974 if (struct_return) 975 { 976 regcache_cooked_write_unsigned (regcache, regnum, struct_addr); 977 regnum++; 978 } 979 980 /* Fill in registers and arg lists */ 981 for (i = 0; i < nargs; i++) 982 { 983 struct value *arg = args[i]; 984 struct type *type = check_typedef (VALUE_TYPE (arg)); 985 char *contents = VALUE_CONTENTS (arg); 986 int len = TYPE_LENGTH (type); 987 int aligned_regnum = (regnum + 1) & ~1; 988 989 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ 990 if (len <= 2 && regnum <= ARGN_REGNUM) 991 /* fits in a single register, do not align */ 992 { 993 val = extract_unsigned_integer (contents, len); 994 regcache_cooked_write_unsigned (regcache, regnum++, val); 995 } 996 else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) 997 /* value fits in remaining registers, store keeping left 998 aligned */ 999 { 1000 int b; 1001 regnum = aligned_regnum; 1002 for (b = 0; b < (len & ~1); b += 2) 1003 { 1004 val = extract_unsigned_integer (&contents[b], 2); 1005 regcache_cooked_write_unsigned (regcache, regnum++, val); 1006 } 1007 if (b < len) 1008 { 1009 val = extract_unsigned_integer (&contents[b], 1); 1010 regcache_cooked_write_unsigned (regcache, regnum++, (val << 8)); 1011 } 1012 } 1013 else 1014 { 1015 /* arg will go onto stack */ 1016 regnum = ARGN_REGNUM + 1; 1017 si = push_stack_item (si, contents, len); 1018 } 1019 } 1020 1021 while (si) 1022 { 1023 sp = (sp - si->len) & ~1; 1024 write_memory (sp, si->data, si->len); 1025 si = pop_stack_item (si); 1026 } 1027 1028 /* Finally, update the SP register. */ 1029 regcache_cooked_write_unsigned (regcache, D10V_SP_REGNUM, 1030 d10v_convert_daddr_to_raw (sp)); 1031 1032 return sp; 1033} 1034 1035/* Translate a GDB virtual ADDR/LEN into a format the remote target 1036 understands. Returns number of bytes that can be transfered 1037 starting at TARG_ADDR. Return ZERO if no bytes can be transfered 1038 (segmentation fault). Since the simulator knows all about how the 1039 VM system works, we just call that to do the translation. */ 1040 1041static void 1042remote_d10v_translate_xfer_address (struct gdbarch *gdbarch, 1043 struct regcache *regcache, 1044 CORE_ADDR memaddr, int nr_bytes, 1045 CORE_ADDR *targ_addr, int *targ_len) 1046{ 1047 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1048 long out_addr; 1049 long out_len; 1050 out_len = sim_d10v_translate_addr (memaddr, nr_bytes, &out_addr, regcache, 1051 tdep->dmap_register, tdep->imap_register); 1052 *targ_addr = out_addr; 1053 *targ_len = out_len; 1054} 1055 1056 1057/* The following code implements access to, and display of, the D10V's 1058 instruction trace buffer. The buffer consists of 64K or more 1059 4-byte words of data, of which each words includes an 8-bit count, 1060 an 8-bit segment number, and a 16-bit instruction address. 1061 1062 In theory, the trace buffer is continuously capturing instruction 1063 data that the CPU presents on its "debug bus", but in practice, the 1064 ROMified GDB stub only enables tracing when it continues or steps 1065 the program, and stops tracing when the program stops; so it 1066 actually works for GDB to read the buffer counter out of memory and 1067 then read each trace word. The counter records where the tracing 1068 stops, but there is no record of where it started, so we remember 1069 the PC when we resumed and then search backwards in the trace 1070 buffer for a word that includes that address. This is not perfect, 1071 because you will miss trace data if the resumption PC is the target 1072 of a branch. (The value of the buffer counter is semi-random, any 1073 trace data from a previous program stop is gone.) */ 1074 1075/* The address of the last word recorded in the trace buffer. */ 1076 1077#define DBBC_ADDR (0xd80000) 1078 1079/* The base of the trace buffer, at least for the "Board_0". */ 1080 1081#define TRACE_BUFFER_BASE (0xf40000) 1082 1083static void trace_command (char *, int); 1084 1085static void untrace_command (char *, int); 1086 1087static void trace_info (char *, int); 1088 1089static void tdisassemble_command (char *, int); 1090 1091static void display_trace (int, int); 1092 1093/* True when instruction traces are being collected. */ 1094 1095static int tracing; 1096 1097/* Remembered PC. */ 1098 1099static CORE_ADDR last_pc; 1100 1101/* True when trace output should be displayed whenever program stops. */ 1102 1103static int trace_display; 1104 1105/* True when trace listing should include source lines. */ 1106 1107static int default_trace_show_source = 1; 1108 1109struct trace_buffer 1110 { 1111 int size; 1112 short *counts; 1113 CORE_ADDR *addrs; 1114 } 1115trace_data; 1116 1117static void 1118trace_command (char *args, int from_tty) 1119{ 1120 /* Clear the host-side trace buffer, allocating space if needed. */ 1121 trace_data.size = 0; 1122 if (trace_data.counts == NULL) 1123 trace_data.counts = XCALLOC (65536, short); 1124 if (trace_data.addrs == NULL) 1125 trace_data.addrs = XCALLOC (65536, CORE_ADDR); 1126 1127 tracing = 1; 1128 1129 printf_filtered ("Tracing is now on.\n"); 1130} 1131 1132static void 1133untrace_command (char *args, int from_tty) 1134{ 1135 tracing = 0; 1136 1137 printf_filtered ("Tracing is now off.\n"); 1138} 1139 1140static void 1141trace_info (char *args, int from_tty) 1142{ 1143 int i; 1144 1145 if (trace_data.size) 1146 { 1147 printf_filtered ("%d entries in trace buffer:\n", trace_data.size); 1148 1149 for (i = 0; i < trace_data.size; ++i) 1150 { 1151 printf_filtered ("%d: %d instruction%s at 0x%s\n", 1152 i, 1153 trace_data.counts[i], 1154 (trace_data.counts[i] == 1 ? "" : "s"), 1155 paddr_nz (trace_data.addrs[i])); 1156 } 1157 } 1158 else 1159 printf_filtered ("No entries in trace buffer.\n"); 1160 1161 printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); 1162} 1163 1164static void 1165d10v_eva_prepare_to_trace (void) 1166{ 1167 if (!tracing) 1168 return; 1169 1170 last_pc = read_register (D10V_PC_REGNUM); 1171} 1172 1173/* Collect trace data from the target board and format it into a form 1174 more useful for display. */ 1175 1176static void 1177d10v_eva_get_trace_data (void) 1178{ 1179 int count, i, j, oldsize; 1180 int trace_addr, trace_seg, trace_cnt, next_cnt; 1181 unsigned int last_trace, trace_word, next_word; 1182 unsigned int *tmpspace; 1183 1184 if (!tracing) 1185 return; 1186 1187 tmpspace = xmalloc (65536 * sizeof (unsigned int)); 1188 1189 last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; 1190 1191 /* Collect buffer contents from the target, stopping when we reach 1192 the word recorded when execution resumed. */ 1193 1194 count = 0; 1195 while (last_trace > 0) 1196 { 1197 QUIT; 1198 trace_word = 1199 read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); 1200 trace_addr = trace_word & 0xffff; 1201 last_trace -= 4; 1202 /* Ignore an apparently nonsensical entry. */ 1203 if (trace_addr == 0xffd5) 1204 continue; 1205 tmpspace[count++] = trace_word; 1206 if (trace_addr == last_pc) 1207 break; 1208 if (count > 65535) 1209 break; 1210 } 1211 1212 /* Move the data to the host-side trace buffer, adjusting counts to 1213 include the last instruction executed and transforming the address 1214 into something that GDB likes. */ 1215 1216 for (i = 0; i < count; ++i) 1217 { 1218 trace_word = tmpspace[i]; 1219 next_word = ((i == 0) ? 0 : tmpspace[i - 1]); 1220 trace_addr = trace_word & 0xffff; 1221 next_cnt = (next_word >> 24) & 0xff; 1222 j = trace_data.size + count - i - 1; 1223 trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; 1224 trace_data.counts[j] = next_cnt + 1; 1225 } 1226 1227 oldsize = trace_data.size; 1228 trace_data.size += count; 1229 1230 xfree (tmpspace); 1231 1232 if (trace_display) 1233 display_trace (oldsize, trace_data.size); 1234} 1235 1236static void 1237tdisassemble_command (char *arg, int from_tty) 1238{ 1239 int i, count; 1240 CORE_ADDR low, high; 1241 1242 if (!arg) 1243 { 1244 low = 0; 1245 high = trace_data.size; 1246 } 1247 else 1248 { 1249 char *space_index = strchr (arg, ' '); 1250 if (space_index == NULL) 1251 { 1252 low = parse_and_eval_address (arg); 1253 high = low + 5; 1254 } 1255 else 1256 { 1257 /* Two arguments. */ 1258 *space_index = '\0'; 1259 low = parse_and_eval_address (arg); 1260 high = parse_and_eval_address (space_index + 1); 1261 if (high < low) 1262 high = low; 1263 } 1264 } 1265 1266 printf_filtered ("Dump of trace from %s to %s:\n", 1267 paddr_u (low), paddr_u (high)); 1268 1269 display_trace (low, high); 1270 1271 printf_filtered ("End of trace dump.\n"); 1272 gdb_flush (gdb_stdout); 1273} 1274 1275static void 1276display_trace (int low, int high) 1277{ 1278 int i, count, trace_show_source, first, suppress; 1279 CORE_ADDR next_address; 1280 1281 trace_show_source = default_trace_show_source; 1282 if (!have_full_symbols () && !have_partial_symbols ()) 1283 { 1284 trace_show_source = 0; 1285 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); 1286 printf_filtered ("Trace will not display any source.\n"); 1287 } 1288 1289 first = 1; 1290 suppress = 0; 1291 for (i = low; i < high; ++i) 1292 { 1293 next_address = trace_data.addrs[i]; 1294 count = trace_data.counts[i]; 1295 while (count-- > 0) 1296 { 1297 QUIT; 1298 if (trace_show_source) 1299 { 1300 struct symtab_and_line sal, sal_prev; 1301 1302 sal_prev = find_pc_line (next_address - 4, 0); 1303 sal = find_pc_line (next_address, 0); 1304 1305 if (sal.symtab) 1306 { 1307 if (first || sal.line != sal_prev.line) 1308 print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); 1309 suppress = 0; 1310 } 1311 else 1312 { 1313 if (!suppress) 1314 /* FIXME-32x64--assumes sal.pc fits in long. */ 1315 printf_filtered ("No source file for address %s.\n", 1316 hex_string ((unsigned long) sal.pc)); 1317 suppress = 1; 1318 } 1319 } 1320 first = 0; 1321 print_address (next_address, gdb_stdout); 1322 printf_filtered (":"); 1323 printf_filtered ("\t"); 1324 wrap_here (" "); 1325 next_address += gdb_print_insn (next_address, gdb_stdout); 1326 printf_filtered ("\n"); 1327 gdb_flush (gdb_stdout); 1328 } 1329 } 1330} 1331 1332static CORE_ADDR 1333d10v_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1334{ 1335 ULONGEST pc; 1336 frame_unwind_unsigned_register (next_frame, D10V_PC_REGNUM, &pc); 1337 return d10v_make_iaddr (pc); 1338} 1339 1340/* Given a GDB frame, determine the address of the calling function's 1341 frame. This will be used to create a new GDB frame struct. */ 1342 1343static void 1344d10v_frame_this_id (struct frame_info *next_frame, 1345 void **this_prologue_cache, 1346 struct frame_id *this_id) 1347{ 1348 struct d10v_unwind_cache *info 1349 = d10v_frame_unwind_cache (next_frame, this_prologue_cache); 1350 CORE_ADDR base; 1351 CORE_ADDR func; 1352 struct frame_id id; 1353 1354 /* The FUNC is easy. */ 1355 func = frame_func_unwind (next_frame); 1356 1357 /* Hopefully the prologue analysis either correctly determined the 1358 frame's base (which is the SP from the previous frame), or set 1359 that base to "NULL". */ 1360 base = info->prev_sp; 1361 if (base == STACK_START || base == 0) 1362 return; 1363 1364 id = frame_id_build (base, func); 1365 1366 (*this_id) = id; 1367} 1368 1369static void 1370d10v_frame_prev_register (struct frame_info *next_frame, 1371 void **this_prologue_cache, 1372 int regnum, int *optimizedp, 1373 enum lval_type *lvalp, CORE_ADDR *addrp, 1374 int *realnump, void *bufferp) 1375{ 1376 struct d10v_unwind_cache *info 1377 = d10v_frame_unwind_cache (next_frame, this_prologue_cache); 1378 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, 1379 optimizedp, lvalp, addrp, realnump, bufferp); 1380} 1381 1382static const struct frame_unwind d10v_frame_unwind = { 1383 NORMAL_FRAME, 1384 d10v_frame_this_id, 1385 d10v_frame_prev_register 1386}; 1387 1388static const struct frame_unwind * 1389d10v_frame_sniffer (struct frame_info *next_frame) 1390{ 1391 return &d10v_frame_unwind; 1392} 1393 1394static CORE_ADDR 1395d10v_frame_base_address (struct frame_info *next_frame, void **this_cache) 1396{ 1397 struct d10v_unwind_cache *info 1398 = d10v_frame_unwind_cache (next_frame, this_cache); 1399 return info->base; 1400} 1401 1402static const struct frame_base d10v_frame_base = { 1403 &d10v_frame_unwind, 1404 d10v_frame_base_address, 1405 d10v_frame_base_address, 1406 d10v_frame_base_address 1407}; 1408 1409/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that 1410 dummy frame. The frame ID's base needs to match the TOS value 1411 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 1412 breakpoint. */ 1413 1414static struct frame_id 1415d10v_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 1416{ 1417 return frame_id_build (d10v_unwind_sp (gdbarch, next_frame), 1418 frame_pc_unwind (next_frame)); 1419} 1420 1421static gdbarch_init_ftype d10v_gdbarch_init; 1422 1423static struct gdbarch * 1424d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1425{ 1426 struct gdbarch *gdbarch; 1427 int d10v_num_regs; 1428 struct gdbarch_tdep *tdep; 1429 gdbarch_register_name_ftype *d10v_register_name; 1430 gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; 1431 1432 /* Find a candidate among the list of pre-declared architectures. */ 1433 arches = gdbarch_list_lookup_by_info (arches, &info); 1434 if (arches != NULL) 1435 return arches->gdbarch; 1436 1437 /* None found, create a new architecture from the information 1438 provided. */ 1439 tdep = XMALLOC (struct gdbarch_tdep); 1440 gdbarch = gdbarch_alloc (&info, tdep); 1441 1442 switch (info.bfd_arch_info->mach) 1443 { 1444 case bfd_mach_d10v_ts2: 1445 d10v_num_regs = 37; 1446 d10v_register_name = d10v_ts2_register_name; 1447 d10v_register_sim_regno = d10v_ts2_register_sim_regno; 1448 tdep->a0_regnum = TS2_A0_REGNUM; 1449 tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; 1450 tdep->dmap_register = d10v_ts2_dmap_register; 1451 tdep->imap_register = d10v_ts2_imap_register; 1452 break; 1453 default: 1454 case bfd_mach_d10v_ts3: 1455 d10v_num_regs = 42; 1456 d10v_register_name = d10v_ts3_register_name; 1457 d10v_register_sim_regno = d10v_ts3_register_sim_regno; 1458 tdep->a0_regnum = TS3_A0_REGNUM; 1459 tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; 1460 tdep->dmap_register = d10v_ts3_dmap_register; 1461 tdep->imap_register = d10v_ts3_imap_register; 1462 break; 1463 } 1464 1465 set_gdbarch_read_pc (gdbarch, d10v_read_pc); 1466 set_gdbarch_write_pc (gdbarch, d10v_write_pc); 1467 set_gdbarch_unwind_sp (gdbarch, d10v_unwind_sp); 1468 1469 set_gdbarch_num_regs (gdbarch, d10v_num_regs); 1470 set_gdbarch_sp_regnum (gdbarch, D10V_SP_REGNUM); 1471 set_gdbarch_register_name (gdbarch, d10v_register_name); 1472 set_gdbarch_register_type (gdbarch, d10v_register_type); 1473 1474 set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); 1475 set_gdbarch_addr_bit (gdbarch, 32); 1476 set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); 1477 set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); 1478 set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); 1479 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 1480 set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); 1481 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); 1482 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 1483 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long 1484 double'' is 64 bits. */ 1485 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 1486 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); 1487 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 1488 switch (info.byte_order) 1489 { 1490 case BFD_ENDIAN_BIG: 1491 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); 1492 set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); 1493 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); 1494 break; 1495 case BFD_ENDIAN_LITTLE: 1496 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); 1497 set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); 1498 set_gdbarch_long_double_format (gdbarch, 1499 &floatformat_ieee_double_little); 1500 break; 1501 default: 1502 internal_error (__FILE__, __LINE__, 1503 "d10v_gdbarch_init: bad byte order for float format"); 1504 } 1505 1506 set_gdbarch_return_value (gdbarch, d10v_return_value); 1507 set_gdbarch_push_dummy_code (gdbarch, d10v_push_dummy_code); 1508 set_gdbarch_push_dummy_call (gdbarch, d10v_push_dummy_call); 1509 1510 set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); 1511 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1512 set_gdbarch_decr_pc_after_break (gdbarch, 4); 1513 set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); 1514 1515 set_gdbarch_remote_translate_xfer_address (gdbarch, 1516 remote_d10v_translate_xfer_address); 1517 1518 set_gdbarch_frame_align (gdbarch, d10v_frame_align); 1519 1520 set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); 1521 1522 set_gdbarch_print_registers_info (gdbarch, d10v_print_registers_info); 1523 1524 frame_unwind_append_sniffer (gdbarch, d10v_frame_sniffer); 1525 frame_base_set_default (gdbarch, &d10v_frame_base); 1526 1527 /* Methods for saving / extracting a dummy frame's ID. The ID's 1528 stack address must match the SP value returned by 1529 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ 1530 set_gdbarch_unwind_dummy_id (gdbarch, d10v_unwind_dummy_id); 1531 1532 /* Return the unwound PC value. */ 1533 set_gdbarch_unwind_pc (gdbarch, d10v_unwind_pc); 1534 1535 set_gdbarch_print_insn (gdbarch, print_insn_d10v); 1536 1537 return gdbarch; 1538} 1539 1540void 1541_initialize_d10v_tdep (void) 1542{ 1543 register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); 1544 1545 deprecated_target_resume_hook = d10v_eva_prepare_to_trace; 1546 deprecated_target_wait_loop_hook = d10v_eva_get_trace_data; 1547 1548 deprecate_cmd (add_com ("regs", class_vars, show_regs, 1549 "Print all registers"), 1550 "info registers"); 1551 1552 add_com ("itrace", class_support, trace_command, 1553 "Enable tracing of instruction execution."); 1554 1555 add_com ("iuntrace", class_support, untrace_command, 1556 "Disable tracing of instruction execution."); 1557 1558 add_com ("itdisassemble", class_vars, tdisassemble_command, 1559 "Disassemble the trace buffer.\n\ 1560Two optional arguments specify a range of trace buffer entries\n\ 1561as reported by info trace (NOT addresses!)."); 1562 1563 add_info ("itrace", trace_info, 1564 "Display info about the trace data buffer."); 1565 1566 add_setshow_boolean_cmd ("itracedisplay", no_class, &trace_display, "\ 1567Set automatic display of trace.", "\ 1568Show automatic display of trace.", "\ 1569Controls the display of d10v specific instruction trace information.", "\ 1570Automatic display of trace is %s.", 1571 NULL, NULL, &setlist, &showlist); 1572 add_setshow_boolean_cmd ("itracesource", no_class, 1573 &default_trace_show_source, "\ 1574Set display of source code with trace.", "\ 1575Show display of source code with trace.", "\ 1576When on source code is included in the d10v instruction trace display.", "\ 1577Display of source code with trace is %s.", 1578 NULL, NULL, &setlist, &showlist); 1579} 1580