1/*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD$"); 22 23/*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54 55#include <net80211/ieee80211_var.h> 56#include <net80211/ieee80211_radiotap.h> 57#include <net80211/ieee80211_regdomain.h> 58#include <net80211/ieee80211_ratectl.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/ip.h> 64#include <netinet/if_ether.h> 65 66#include <dev/ral/rt2860reg.h> 67#include <dev/ral/rt2860var.h> 68 69#define RAL_DEBUG 70#ifdef RAL_DEBUG 71#define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 72#define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 73#else 74#define DPRINTF(x) 75#define DPRINTFN(n, x) 76#endif 77 78static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 79 const char [IFNAMSIZ], int, enum ieee80211_opmode, 80 int, const uint8_t [IEEE80211_ADDR_LEN], 81 const uint8_t [IEEE80211_ADDR_LEN]); 82static void rt2860_vap_delete(struct ieee80211vap *); 83static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 84static int rt2860_alloc_tx_ring(struct rt2860_softc *, 85 struct rt2860_tx_ring *); 86static void rt2860_reset_tx_ring(struct rt2860_softc *, 87 struct rt2860_tx_ring *); 88static void rt2860_free_tx_ring(struct rt2860_softc *, 89 struct rt2860_tx_ring *); 90static int rt2860_alloc_tx_pool(struct rt2860_softc *); 91static void rt2860_free_tx_pool(struct rt2860_softc *); 92static int rt2860_alloc_rx_ring(struct rt2860_softc *, 93 struct rt2860_rx_ring *); 94static void rt2860_reset_rx_ring(struct rt2860_softc *, 95 struct rt2860_rx_ring *); 96static void rt2860_free_rx_ring(struct rt2860_softc *, 97 struct rt2860_rx_ring *); 98static void rt2860_updatestats(struct rt2860_softc *); 99static void rt2860_newassoc(struct ieee80211_node *, int); 100static void rt2860_node_free(struct ieee80211_node *); 101#ifdef IEEE80211_HT 102static int rt2860_ampdu_rx_start(struct ieee80211com *, 103 struct ieee80211_node *, uint8_t); 104static void rt2860_ampdu_rx_stop(struct ieee80211com *, 105 struct ieee80211_node *, uint8_t); 106#endif 107static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 108 int); 109static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 110static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 111static void rt2860_intr_coherent(struct rt2860_softc *); 112static void rt2860_drain_stats_fifo(struct rt2860_softc *); 113static void rt2860_tx_intr(struct rt2860_softc *, int); 114static void rt2860_rx_intr(struct rt2860_softc *); 115static void rt2860_tbtt_intr(struct rt2860_softc *); 116static void rt2860_gp_intr(struct rt2860_softc *); 117static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 118 struct ieee80211_node *); 119static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 120 const struct ieee80211_bpf_params *); 121static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 122 struct ieee80211_node *, 123 const struct ieee80211_bpf_params *params); 124static void rt2860_start(struct ifnet *); 125static void rt2860_start_locked(struct ifnet *); 126static void rt2860_watchdog(void *); 127static int rt2860_ioctl(struct ifnet *, u_long, caddr_t); 128static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 129static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 130static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 131static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 132static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 133static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 134static void rt2860_enable_mrr(struct rt2860_softc *); 135static void rt2860_set_txpreamble(struct rt2860_softc *); 136static void rt2860_set_basicrates(struct rt2860_softc *, 137 const struct ieee80211_rateset *); 138static void rt2860_scan_start(struct ieee80211com *); 139static void rt2860_scan_end(struct ieee80211com *); 140static void rt2860_set_channel(struct ieee80211com *); 141static void rt2860_select_chan_group(struct rt2860_softc *, int); 142static void rt2860_set_chan(struct rt2860_softc *, u_int); 143static void rt3090_set_chan(struct rt2860_softc *, u_int); 144static int rt3090_rf_init(struct rt2860_softc *); 145static void rt3090_rf_wakeup(struct rt2860_softc *); 146static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 147 uint8_t *); 148static void rt3090_rf_setup(struct rt2860_softc *); 149static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 150static void rt2860_set_gp_timer(struct rt2860_softc *, int); 151static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 152static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 153static void rt2860_update_promisc(struct ifnet *); 154static void rt2860_updateslot(struct ifnet *); 155static void rt2860_updateprot(struct ifnet *); 156static int rt2860_updateedca(struct ieee80211com *); 157#ifdef HW_CRYPTO 158static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 159 struct ieee80211_key *); 160static void rt2860_delete_key(struct ieee80211com *, 161 struct ieee80211_node *, struct ieee80211_key *); 162#endif 163static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 164static const char *rt2860_get_rf(uint8_t); 165static int rt2860_read_eeprom(struct rt2860_softc *, 166 uint8_t macaddr[IEEE80211_ADDR_LEN]); 167static int rt2860_bbp_init(struct rt2860_softc *); 168static int rt2860_txrx_enable(struct rt2860_softc *); 169static void rt2860_init(void *); 170static void rt2860_init_locked(struct rt2860_softc *); 171static void rt2860_stop(void *); 172static void rt2860_stop_locked(struct rt2860_softc *); 173static int rt2860_load_microcode(struct rt2860_softc *); 174#ifdef NOT_YET 175static void rt2860_calib(struct rt2860_softc *); 176#endif 177static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 178static void rt2860_switch_chan(struct rt2860_softc *, 179 struct ieee80211_channel *); 180static int rt2860_setup_beacon(struct rt2860_softc *, 181 struct ieee80211vap *); 182static void rt2860_enable_tsf_sync(struct rt2860_softc *); 183 184static const struct { 185 uint32_t reg; 186 uint32_t val; 187} rt2860_def_mac[] = { 188 RT2860_DEF_MAC 189}; 190 191static const struct { 192 uint8_t reg; 193 uint8_t val; 194} rt2860_def_bbp[] = { 195 RT2860_DEF_BBP 196}; 197 198static const struct rfprog { 199 uint8_t chan; 200 uint32_t r1, r2, r3, r4; 201} rt2860_rf2850[] = { 202 RT2860_RF2850 203}; 204 205struct { 206 uint8_t n, r, k; 207} rt3090_freqs[] = { 208 RT3070_RF3052 209}; 210 211static const struct { 212 uint8_t reg; 213 uint8_t val; 214} rt3090_def_rf[] = { 215 RT3070_DEF_RF 216}; 217 218int 219rt2860_attach(device_t dev, int id) 220{ 221 struct rt2860_softc *sc = device_get_softc(dev); 222 struct ieee80211com *ic; 223 struct ifnet *ifp; 224 uint32_t tmp; 225 int error, ntries, qid; 226 uint8_t bands; 227 uint8_t macaddr[IEEE80211_ADDR_LEN]; 228 229 sc->sc_dev = dev; 230 sc->sc_debug = 0; 231 232 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 233 if (ifp == NULL) { 234 device_printf(sc->sc_dev, "can not if_alloc()\n"); 235 return ENOMEM; 236 } 237 ic = ifp->if_l2com; 238 239 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 240 MTX_DEF | MTX_RECURSE); 241 242 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 243 244 /* wait for NIC to initialize */ 245 for (ntries = 0; ntries < 100; ntries++) { 246 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 247 if (tmp != 0 && tmp != 0xffffffff) 248 break; 249 DELAY(10); 250 } 251 if (ntries == 100) { 252 device_printf(sc->sc_dev, 253 "timeout waiting for NIC to initialize\n"); 254 error = EIO; 255 goto fail1; 256 } 257 sc->mac_ver = tmp >> 16; 258 sc->mac_rev = tmp & 0xffff; 259 260 if (sc->mac_ver != 0x2860 && 261 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 262 sc->sc_flags |= RT2860_ADVANCED_PS; 263 264 /* retrieve RF rev. no and various other things from EEPROM */ 265 rt2860_read_eeprom(sc, macaddr); 266 if (bootverbose) { 267 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 268 "RF %s (MIMO %dT%dR), address %6D\n", 269 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 270 sc->ntxchains, sc->nrxchains, macaddr, ":"); 271 } 272 273 /* 274 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 275 */ 276 for (qid = 0; qid < 6; qid++) { 277 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 278 device_printf(sc->sc_dev, 279 "could not allocate Tx ring %d\n", qid); 280 goto fail2; 281 } 282 } 283 284 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 285 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 286 goto fail2; 287 } 288 289 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 290 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 291 goto fail3; 292 } 293 294 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 295 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 296 WME_AC_VO : 5; 297 298 ifp->if_softc = sc; 299 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 300 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 301 ifp->if_init = rt2860_init; 302 ifp->if_ioctl = rt2860_ioctl; 303 ifp->if_start = rt2860_start; 304 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 305 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 306 IFQ_SET_READY(&ifp->if_snd); 307 308 ic->ic_ifp = ifp; 309 ic->ic_opmode = IEEE80211_M_STA; 310 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 311 312 /* set device capabilities */ 313 ic->ic_caps = 314 IEEE80211_C_STA /* station mode */ 315 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 316 | IEEE80211_C_HOSTAP /* hostap mode */ 317 | IEEE80211_C_MONITOR /* monitor mode */ 318 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 319 | IEEE80211_C_WDS /* 4-address traffic works */ 320 | IEEE80211_C_MBSS /* mesh point link mode */ 321 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 322 | IEEE80211_C_SHSLOT /* short slot time supported */ 323 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 324#if 0 325 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 326#endif 327 | IEEE80211_C_WME /* 802.11e */ 328 ; 329 330 bands = 0; 331 setbit(&bands, IEEE80211_MODE_11B); 332 setbit(&bands, IEEE80211_MODE_11G); 333 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) 334 setbit(&bands, IEEE80211_MODE_11A); 335 ieee80211_init_channels(ic, NULL, &bands); 336 337 ieee80211_ifattach(ic, macaddr); 338 339 ic->ic_wme.wme_update = rt2860_updateedca; 340 ic->ic_scan_start = rt2860_scan_start; 341 ic->ic_scan_end = rt2860_scan_end; 342 ic->ic_set_channel = rt2860_set_channel; 343 ic->ic_updateslot = rt2860_updateslot; 344 ic->ic_update_promisc = rt2860_update_promisc; 345 ic->ic_raw_xmit = rt2860_raw_xmit; 346 sc->sc_node_free = ic->ic_node_free; 347 ic->ic_node_free = rt2860_node_free; 348 ic->ic_newassoc = rt2860_newassoc; 349 350 ic->ic_vap_create = rt2860_vap_create; 351 ic->ic_vap_delete = rt2860_vap_delete; 352 353 ieee80211_radiotap_attach(ic, 354 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 355 RT2860_TX_RADIOTAP_PRESENT, 356 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 357 RT2860_RX_RADIOTAP_PRESENT); 358 359#ifdef RAL_DEBUG 360 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 361 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 362 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 363#endif 364 if (bootverbose) 365 ieee80211_announce(ic); 366 367 return 0; 368 369fail3: rt2860_free_rx_ring(sc, &sc->rxq); 370fail2: while (--qid >= 0) 371 rt2860_free_tx_ring(sc, &sc->txq[qid]); 372fail1: mtx_destroy(&sc->sc_mtx); 373 if_free(ifp); 374 return error; 375} 376 377int 378rt2860_detach(void *xsc) 379{ 380 struct rt2860_softc *sc = xsc; 381 struct ifnet *ifp = sc->sc_ifp; 382 struct ieee80211com *ic = ifp->if_l2com; 383 int qid; 384 385 RAL_LOCK(sc); 386 rt2860_stop_locked(sc); 387 RAL_UNLOCK(sc); 388 389 ieee80211_ifdetach(ic); 390 391 for (qid = 0; qid < 6; qid++) 392 rt2860_free_tx_ring(sc, &sc->txq[qid]); 393 rt2860_free_rx_ring(sc, &sc->rxq); 394 rt2860_free_tx_pool(sc); 395 396 if_free(ifp); 397 398 mtx_destroy(&sc->sc_mtx); 399 400 return 0; 401} 402 403void 404rt2860_shutdown(void *xsc) 405{ 406 struct rt2860_softc *sc = xsc; 407 408 rt2860_stop(sc); 409} 410 411void 412rt2860_suspend(void *xsc) 413{ 414 struct rt2860_softc *sc = xsc; 415 416 rt2860_stop(sc); 417} 418 419void 420rt2860_resume(void *xsc) 421{ 422 struct rt2860_softc *sc = xsc; 423 struct ifnet *ifp = sc->sc_ifp; 424 425 if (ifp->if_flags & IFF_UP) 426 rt2860_init(sc); 427} 428 429static struct ieee80211vap * 430rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 431 enum ieee80211_opmode opmode, int flags, 432 const uint8_t bssid[IEEE80211_ADDR_LEN], 433 const uint8_t mac[IEEE80211_ADDR_LEN]) 434{ 435 struct ifnet *ifp = ic->ic_ifp; 436 struct rt2860_vap *rvp; 437 struct ieee80211vap *vap; 438 439 switch (opmode) { 440 case IEEE80211_M_STA: 441 case IEEE80211_M_IBSS: 442 case IEEE80211_M_AHDEMO: 443 case IEEE80211_M_MONITOR: 444 case IEEE80211_M_HOSTAP: 445 case IEEE80211_M_MBSS: 446 /* XXXRP: TBD */ 447 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 448 if_printf(ifp, "only 1 vap supported\n"); 449 return NULL; 450 } 451 if (opmode == IEEE80211_M_STA) 452 flags |= IEEE80211_CLONE_NOBEACONS; 453 break; 454 case IEEE80211_M_WDS: 455 if (TAILQ_EMPTY(&ic->ic_vaps) || 456 ic->ic_opmode != IEEE80211_M_HOSTAP) { 457 if_printf(ifp, "wds only supported in ap mode\n"); 458 return NULL; 459 } 460 /* 461 * Silently remove any request for a unique 462 * bssid; WDS vap's always share the local 463 * mac address. 464 */ 465 flags &= ~IEEE80211_CLONE_BSSID; 466 break; 467 default: 468 if_printf(ifp, "unknown opmode %d\n", opmode); 469 return NULL; 470 } 471 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_NOWAIT | M_ZERO); 472 if (rvp == NULL) 473 return NULL; 474 vap = &rvp->ral_vap; 475 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 476 477 /* override state transition machine */ 478 rvp->ral_newstate = vap->iv_newstate; 479 vap->iv_newstate = rt2860_newstate; 480#if 0 481 vap->iv_update_beacon = rt2860_beacon_update; 482#endif 483 484 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 485 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 486 487 ieee80211_ratectl_init(vap); 488 /* complete setup */ 489 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 490 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 491 ic->ic_opmode = opmode; 492 return vap; 493} 494 495static void 496rt2860_vap_delete(struct ieee80211vap *vap) 497{ 498 struct rt2860_vap *rvp = RT2860_VAP(vap); 499 500 ieee80211_ratectl_deinit(vap); 501 ieee80211_vap_detach(vap); 502 free(rvp, M_80211_VAP); 503} 504 505static void 506rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 507{ 508 if (error != 0) 509 return; 510 511 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 512 513 *(bus_addr_t *)arg = segs[0].ds_addr; 514} 515 516 517static int 518rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 519{ 520 int size, error; 521 522 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 523 524 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 525 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 526 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 527 if (error != 0) { 528 device_printf(sc->sc_dev, "could not create desc DMA map\n"); 529 goto fail; 530 } 531 532 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 533 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 534 if (error != 0) { 535 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 536 goto fail; 537 } 538 539 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 540 size, rt2860_dma_map_addr, &ring->paddr, 0); 541 if (error != 0) { 542 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 543 goto fail; 544 } 545 546 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 547 548 return 0; 549 550fail: rt2860_free_tx_ring(sc, ring); 551 return error; 552} 553 554void 555rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 556{ 557 struct rt2860_tx_data *data; 558 int i; 559 560 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 561 if ((data = ring->data[i]) == NULL) 562 continue; /* nothing mapped in this slot */ 563 564 if (data->m != NULL) { 565 bus_dmamap_sync(sc->txwi_dmat, data->map, 566 BUS_DMASYNC_POSTWRITE); 567 bus_dmamap_unload(sc->txwi_dmat, data->map); 568 m_freem(data->m); 569 data->m = NULL; 570 } 571 if (data->ni != NULL) { 572 ieee80211_free_node(data->ni); 573 data->ni = NULL; 574 } 575 576 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 577 ring->data[i] = NULL; 578 } 579 580 ring->queued = 0; 581 ring->cur = ring->next = 0; 582} 583 584void 585rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 586{ 587 struct rt2860_tx_data *data; 588 int i; 589 590 if (ring->txd != NULL) { 591 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 592 BUS_DMASYNC_POSTWRITE); 593 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 594 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 595 } 596 if (ring->desc_dmat != NULL) 597 bus_dma_tag_destroy(ring->desc_dmat); 598 599 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 600 if ((data = ring->data[i]) == NULL) 601 continue; /* nothing mapped in this slot */ 602 603 if (data->m != NULL) { 604 bus_dmamap_sync(sc->txwi_dmat, data->map, 605 BUS_DMASYNC_POSTWRITE); 606 bus_dmamap_unload(sc->txwi_dmat, data->map); 607 m_freem(data->m); 608 } 609 if (data->ni != NULL) 610 ieee80211_free_node(data->ni); 611 612 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 613 } 614} 615 616/* 617 * Allocate a pool of TX Wireless Information blocks. 618 */ 619int 620rt2860_alloc_tx_pool(struct rt2860_softc *sc) 621{ 622 caddr_t vaddr; 623 bus_addr_t paddr; 624 int i, size, error; 625 626 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 627 628 /* init data_pool early in case of failure.. */ 629 SLIST_INIT(&sc->data_pool); 630 631 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 632 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 633 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 634 if (error != 0) { 635 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 636 goto fail; 637 } 638 639 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 640 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 641 if (error != 0) { 642 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 643 goto fail; 644 } 645 646 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 647 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 648 if (error != 0) { 649 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 650 goto fail; 651 } 652 653 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 654 655 vaddr = sc->txwi_vaddr; 656 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 657 struct rt2860_tx_data *data = &sc->data[i]; 658 659 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 660 if (error != 0) { 661 device_printf(sc->sc_dev, "could not create DMA map\n"); 662 goto fail; 663 } 664 data->txwi = (struct rt2860_txwi *)vaddr; 665 data->paddr = paddr; 666 vaddr += RT2860_TXWI_DMASZ; 667 paddr += RT2860_TXWI_DMASZ; 668 669 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 670 } 671 672 return 0; 673 674fail: rt2860_free_tx_pool(sc); 675 return error; 676} 677 678void 679rt2860_free_tx_pool(struct rt2860_softc *sc) 680{ 681 if (sc->txwi_vaddr != NULL) { 682 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 683 BUS_DMASYNC_POSTWRITE); 684 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 685 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 686 } 687 if (sc->txwi_dmat != NULL) 688 bus_dma_tag_destroy(sc->txwi_dmat); 689 690 while (!SLIST_EMPTY(&sc->data_pool)) { 691 struct rt2860_tx_data *data; 692 data = SLIST_FIRST(&sc->data_pool); 693 bus_dmamap_destroy(sc->txwi_dmat, data->map); 694 SLIST_REMOVE_HEAD(&sc->data_pool, next); 695 } 696} 697 698int 699rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 700{ 701 bus_addr_t physaddr; 702 int i, size, error; 703 704 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 705 706 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 707 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 708 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 709 if (error != 0) { 710 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 711 goto fail; 712 } 713 714 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 715 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 716 if (error != 0) { 717 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 718 goto fail; 719 } 720 721 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 722 size, rt2860_dma_map_addr, &ring->paddr, 0); 723 if (error != 0) { 724 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 725 goto fail; 726 } 727 728 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 729 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 730 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 731 if (error != 0) { 732 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 733 goto fail; 734 } 735 736 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 737 struct rt2860_rx_data *data = &ring->data[i]; 738 struct rt2860_rxd *rxd = &ring->rxd[i]; 739 740 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 741 if (error != 0) { 742 device_printf(sc->sc_dev, "could not create DMA map\n"); 743 goto fail; 744 } 745 746 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 747 if (data->m == NULL) { 748 device_printf(sc->sc_dev, 749 "could not allocate rx mbuf\n"); 750 error = ENOMEM; 751 goto fail; 752 } 753 754 error = bus_dmamap_load(ring->data_dmat, data->map, 755 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 756 &physaddr, 0); 757 if (error != 0) { 758 device_printf(sc->sc_dev, 759 "could not load rx buf DMA map"); 760 goto fail; 761 } 762 763 rxd->sdp0 = htole32(physaddr); 764 rxd->sdl0 = htole16(MCLBYTES); 765 } 766 767 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 768 769 return 0; 770 771fail: rt2860_free_rx_ring(sc, ring); 772 return error; 773} 774 775void 776rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 777{ 778 int i; 779 780 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 781 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 782 783 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 784 785 ring->cur = 0; 786} 787 788void 789rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 790{ 791 int i; 792 793 if (ring->rxd != NULL) { 794 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 795 BUS_DMASYNC_POSTWRITE); 796 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 797 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 798 } 799 if (ring->desc_dmat != NULL) 800 bus_dma_tag_destroy(ring->desc_dmat); 801 802 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 803 struct rt2860_rx_data *data = &ring->data[i]; 804 805 if (data->m != NULL) { 806 bus_dmamap_sync(ring->data_dmat, data->map, 807 BUS_DMASYNC_POSTREAD); 808 bus_dmamap_unload(ring->data_dmat, data->map); 809 m_freem(data->m); 810 } 811 if (data->map != NULL) 812 bus_dmamap_destroy(ring->data_dmat, data->map); 813 } 814 if (ring->data_dmat != NULL) 815 bus_dma_tag_destroy(ring->data_dmat); 816} 817 818static void 819rt2860_updatestats(struct rt2860_softc *sc) 820{ 821 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 822 823 /* 824 * In IBSS or HostAP modes (when the hardware sends beacons), the 825 * MAC can run into a livelock and start sending CTS-to-self frames 826 * like crazy if protection is enabled. Fortunately, we can detect 827 * when such a situation occurs and reset the MAC. 828 */ 829 if (ic->ic_curmode != IEEE80211_M_STA) { 830 /* check if we're in a livelock situation.. */ 831 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 832 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 833 /* ..and reset MAC/BBP for a while.. */ 834 DPRINTF(("CTS-to-self livelock detected\n")); 835 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 836 RAL_BARRIER_WRITE(sc); 837 DELAY(1); 838 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 839 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 840 } 841 } 842} 843 844static void 845rt2860_newassoc(struct ieee80211_node *ni, int isnew) 846{ 847 struct ieee80211com *ic = ni->ni_ic; 848 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 849 uint8_t wcid; 850 851 wcid = IEEE80211_AID(ni->ni_associd); 852 if (isnew && ni->ni_associd != 0) { 853 sc->wcid2ni[wcid] = ni; 854 855 /* init WCID table entry */ 856 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 857 ni->ni_macaddr, IEEE80211_ADDR_LEN); 858 } 859 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 860 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 861} 862 863static void 864rt2860_node_free(struct ieee80211_node *ni) 865{ 866 struct ieee80211com *ic = ni->ni_ic; 867 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 868 uint8_t wcid; 869 870 if (ni->ni_associd != 0) { 871 wcid = IEEE80211_AID(ni->ni_associd); 872 873 /* clear Rx WCID search table entry */ 874 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 875 } 876 sc->sc_node_free(ni); 877} 878 879#ifdef IEEE80211_HT 880static int 881rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 882 uint8_t tid) 883{ 884 struct rt2860_softc *sc = ic->ic_softc; 885 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 886 uint32_t tmp; 887 888 /* update BA session mask */ 889 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 890 tmp |= (1 << tid) << 16; 891 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 892 return 0; 893} 894 895static void 896rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 897 uint8_t tid) 898{ 899 struct rt2860_softc *sc = ic->ic_softc; 900 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 901 uint32_t tmp; 902 903 /* update BA session mask */ 904 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 905 tmp &= ~((1 << tid) << 16); 906 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 907} 908#endif 909 910int 911rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 912{ 913 struct rt2860_vap *rvp = RT2860_VAP(vap); 914 struct ieee80211com *ic = vap->iv_ic; 915 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 916 uint32_t tmp; 917 int error; 918 919 if (vap->iv_state == IEEE80211_S_RUN) { 920 /* turn link LED off */ 921 rt2860_set_leds(sc, RT2860_LED_RADIO); 922 } 923 924 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 925 /* abort TSF synchronization */ 926 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 927 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 928 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 929 RT2860_TBTT_TIMER_EN)); 930 } 931 932 rt2860_set_gp_timer(sc, 0); 933 934 error = rvp->ral_newstate(vap, nstate, arg); 935 if (error != 0) 936 return (error); 937 938 if (nstate == IEEE80211_S_RUN) { 939 struct ieee80211_node *ni = vap->iv_bss; 940 941 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 942 rt2860_enable_mrr(sc); 943 rt2860_set_txpreamble(sc); 944 rt2860_set_basicrates(sc, &ni->ni_rates); 945 rt2860_set_bssid(sc, ni->ni_bssid); 946 } 947 948 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 949 vap->iv_opmode == IEEE80211_M_IBSS || 950 vap->iv_opmode == IEEE80211_M_MBSS) { 951 error = rt2860_setup_beacon(sc, vap); 952 if (error != 0) 953 return error; 954 } 955 956 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 957 rt2860_enable_tsf_sync(sc); 958 rt2860_set_gp_timer(sc, 500); 959 } 960 961 /* turn link LED on */ 962 rt2860_set_leds(sc, RT2860_LED_RADIO | 963 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 964 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 965 } 966 return error; 967} 968 969/* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 970static uint16_t 971rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 972{ 973 uint32_t tmp; 974 uint16_t reg; 975 int ntries; 976 977 addr *= 2; 978 /*- 979 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 980 * DATA0: F E D C 981 * DATA1: B A 9 8 982 * DATA2: 7 6 5 4 983 * DATA3: 3 2 1 0 984 */ 985 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 986 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 987 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 988 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 989 for (ntries = 0; ntries < 500; ntries++) { 990 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 991 if (!(tmp & RT3070_EFSROM_KICK)) 992 break; 993 DELAY(2); 994 } 995 if (ntries == 500) 996 return 0xffff; 997 998 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 999 return 0xffff; /* address not found */ 1000 1001 /* determine to which 32-bit register our 16-bit word belongs */ 1002 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1003 tmp = RAL_READ(sc, reg); 1004 1005 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1006} 1007 1008/* 1009 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1010 * 93C66 or 93C86). 1011 */ 1012static uint16_t 1013rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1014{ 1015 uint32_t tmp; 1016 uint16_t val; 1017 int n; 1018 1019 /* clock C once before the first command */ 1020 RT2860_EEPROM_CTL(sc, 0); 1021 1022 RT2860_EEPROM_CTL(sc, RT2860_S); 1023 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1024 RT2860_EEPROM_CTL(sc, RT2860_S); 1025 1026 /* write start bit (1) */ 1027 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1028 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1029 1030 /* write READ opcode (10) */ 1031 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1032 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1033 RT2860_EEPROM_CTL(sc, RT2860_S); 1034 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1035 1036 /* write address (A5-A0 or A7-A0) */ 1037 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1038 for (; n >= 0; n--) { 1039 RT2860_EEPROM_CTL(sc, RT2860_S | 1040 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1041 RT2860_EEPROM_CTL(sc, RT2860_S | 1042 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1043 } 1044 1045 RT2860_EEPROM_CTL(sc, RT2860_S); 1046 1047 /* read data Q15-Q0 */ 1048 val = 0; 1049 for (n = 15; n >= 0; n--) { 1050 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1051 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1052 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1053 RT2860_EEPROM_CTL(sc, RT2860_S); 1054 } 1055 1056 RT2860_EEPROM_CTL(sc, 0); 1057 1058 /* clear Chip Select and clock C */ 1059 RT2860_EEPROM_CTL(sc, RT2860_S); 1060 RT2860_EEPROM_CTL(sc, 0); 1061 RT2860_EEPROM_CTL(sc, RT2860_C); 1062 1063 return val; 1064} 1065 1066static __inline uint16_t 1067rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1068{ 1069 /* either eFUSE ROM or EEPROM */ 1070 return sc->sc_srom_read(sc, addr); 1071} 1072 1073static void 1074rt2860_intr_coherent(struct rt2860_softc *sc) 1075{ 1076 uint32_t tmp; 1077 1078 /* DMA finds data coherent event when checking the DDONE bit */ 1079 1080 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1081 1082 /* restart DMA engine */ 1083 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1084 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1085 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1086 1087 (void)rt2860_txrx_enable(sc); 1088} 1089 1090static void 1091rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1092{ 1093 struct ifnet *ifp = sc->sc_ifp; 1094 struct ieee80211_node *ni; 1095 uint32_t stat; 1096 int retrycnt; 1097 uint8_t wcid, mcs, pid; 1098 1099 /* drain Tx status FIFO (maxsize = 16) */ 1100 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1101 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1102 1103 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1104 ni = sc->wcid2ni[wcid]; 1105 1106 /* if no ACK was requested, no feedback is available */ 1107 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL) 1108 continue; 1109 1110 /* update per-STA AMRR stats */ 1111 if (stat & RT2860_TXQ_OK) { 1112 /* 1113 * Check if there were retries, ie if the Tx success 1114 * rate is different from the requested rate. Note 1115 * that it works only because we do not allow rate 1116 * fallback from OFDM to CCK. 1117 */ 1118 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1119 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1120 if (mcs + 1 != pid) 1121 retrycnt = 1; 1122 else 1123 retrycnt = 0; 1124 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1125 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL); 1126 } else { 1127 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1128 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL); 1129 ifp->if_oerrors++; 1130 } 1131 } 1132} 1133 1134static void 1135rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1136{ 1137 struct ifnet *ifp = sc->sc_ifp; 1138 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1139 uint32_t hw; 1140 1141 rt2860_drain_stats_fifo(sc); 1142 1143 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1144 while (ring->next != hw) { 1145 struct rt2860_tx_data *data = ring->data[ring->next]; 1146 1147 if (data != NULL) { 1148 bus_dmamap_sync(sc->txwi_dmat, data->map, 1149 BUS_DMASYNC_POSTWRITE); 1150 bus_dmamap_unload(sc->txwi_dmat, data->map); 1151 if (data->m->m_flags & M_TXCB) { 1152 ieee80211_process_callback(data->ni, data->m, 1153 0); 1154 } 1155 m_freem(data->m); 1156 ieee80211_free_node(data->ni); 1157 data->m = NULL; 1158 data->ni = NULL; 1159 1160 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1161 ring->data[ring->next] = NULL; 1162 1163 ifp->if_opackets++; 1164 } 1165 ring->queued--; 1166 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1167 } 1168 1169 sc->sc_tx_timer = 0; 1170 if (ring->queued < RT2860_TX_RING_COUNT) 1171 sc->qfullmsk &= ~(1 << qid); 1172 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1173 rt2860_start_locked(ifp); 1174} 1175 1176/* 1177 * Return the Rx chain with the highest RSSI for a given frame. 1178 */ 1179static __inline uint8_t 1180rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1181{ 1182 uint8_t rxchain = 0; 1183 1184 if (sc->nrxchains > 1) { 1185 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1186 rxchain = 1; 1187 if (sc->nrxchains > 2) 1188 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1189 rxchain = 2; 1190 } 1191 return rxchain; 1192} 1193 1194static void 1195rt2860_rx_intr(struct rt2860_softc *sc) 1196{ 1197 struct rt2860_rx_radiotap_header *tap; 1198 struct ifnet *ifp = sc->sc_ifp; 1199 struct ieee80211com *ic = ifp->if_l2com; 1200 struct ieee80211_frame *wh; 1201 struct ieee80211_node *ni; 1202 struct mbuf *m, *m1; 1203 bus_addr_t physaddr; 1204 uint32_t hw; 1205 uint16_t phy; 1206 uint8_t ant; 1207 int8_t rssi, nf; 1208 int error; 1209 1210 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1211 while (sc->rxq.cur != hw) { 1212 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1213 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1214 struct rt2860_rxwi *rxwi; 1215 1216 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1217 BUS_DMASYNC_POSTREAD); 1218 1219 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1220 DPRINTF(("RXD DDONE bit not set!\n")); 1221 break; /* should not happen */ 1222 } 1223 1224 if (__predict_false(rxd->flags & 1225 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1226 ifp->if_ierrors++; 1227 goto skip; 1228 } 1229 1230#ifdef HW_CRYPTO 1231 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1232 /* report MIC failures to net80211 for TKIP */ 1233 ic->ic_stats.is_rx_locmicfail++; 1234 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1235 ifp->if_ierrors++; 1236 goto skip; 1237 } 1238#endif 1239 1240 m1 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1241 if (__predict_false(m1 == NULL)) { 1242 ifp->if_ierrors++; 1243 goto skip; 1244 } 1245 1246 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1247 BUS_DMASYNC_POSTREAD); 1248 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1249 1250 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1251 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1252 &physaddr, 0); 1253 if (__predict_false(error != 0)) { 1254 m_freem(m1); 1255 1256 /* try to reload the old mbuf */ 1257 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1258 mtod(data->m, void *), MCLBYTES, 1259 rt2860_dma_map_addr, &physaddr, 0); 1260 if (__predict_false(error != 0)) { 1261 panic("%s: could not load old rx mbuf", 1262 device_get_name(sc->sc_dev)); 1263 } 1264 /* physical address may have changed */ 1265 rxd->sdp0 = htole32(physaddr); 1266 ifp->if_ierrors++; 1267 goto skip; 1268 } 1269 1270 /* 1271 * New mbuf successfully loaded, update Rx ring and continue 1272 * processing. 1273 */ 1274 m = data->m; 1275 data->m = m1; 1276 rxd->sdp0 = htole32(physaddr); 1277 1278 rxwi = mtod(m, struct rt2860_rxwi *); 1279 1280 /* finalize mbuf */ 1281 m->m_pkthdr.rcvif = ifp; 1282 m->m_data = (caddr_t)(rxwi + 1); 1283 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1284 1285 wh = mtod(m, struct ieee80211_frame *); 1286#ifdef HW_CRYPTO 1287 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1288 /* frame is decrypted by hardware */ 1289 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 1290 } 1291#endif 1292 1293 /* HW may insert 2 padding bytes after 802.11 header */ 1294 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1295 u_int hdrlen = ieee80211_hdrsize(wh); 1296 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1297 m->m_data += 2; 1298 wh = mtod(m, struct ieee80211_frame *); 1299 } 1300 1301 ant = rt2860_maxrssi_chain(sc, rxwi); 1302 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1303 nf = RT2860_NOISE_FLOOR; 1304 1305 if (ieee80211_radiotap_active(ic)) { 1306 tap = &sc->sc_rxtap; 1307 tap->wr_flags = 0; 1308 tap->wr_antenna = ant; 1309 tap->wr_antsignal = nf + rssi; 1310 tap->wr_antnoise = nf; 1311 /* in case it can't be found below */ 1312 tap->wr_rate = 2; 1313 phy = le16toh(rxwi->phy); 1314 switch (phy & RT2860_PHY_MODE) { 1315 case RT2860_PHY_CCK: 1316 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1317 case 0: tap->wr_rate = 2; break; 1318 case 1: tap->wr_rate = 4; break; 1319 case 2: tap->wr_rate = 11; break; 1320 case 3: tap->wr_rate = 22; break; 1321 } 1322 if (phy & RT2860_PHY_SHPRE) 1323 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1324 break; 1325 case RT2860_PHY_OFDM: 1326 switch (phy & RT2860_PHY_MCS) { 1327 case 0: tap->wr_rate = 12; break; 1328 case 1: tap->wr_rate = 18; break; 1329 case 2: tap->wr_rate = 24; break; 1330 case 3: tap->wr_rate = 36; break; 1331 case 4: tap->wr_rate = 48; break; 1332 case 5: tap->wr_rate = 72; break; 1333 case 6: tap->wr_rate = 96; break; 1334 case 7: tap->wr_rate = 108; break; 1335 } 1336 break; 1337 } 1338 } 1339 1340 RAL_UNLOCK(sc); 1341 wh = mtod(m, struct ieee80211_frame *); 1342 1343 /* send the frame to the 802.11 layer */ 1344 ni = ieee80211_find_rxnode(ic, 1345 (struct ieee80211_frame_min *)wh); 1346 if (ni != NULL) { 1347 (void)ieee80211_input(ni, m, rssi - nf, nf); 1348 ieee80211_free_node(ni); 1349 } else 1350 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1351 1352 RAL_LOCK(sc); 1353 1354skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1355 1356 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1357 BUS_DMASYNC_PREWRITE); 1358 1359 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1360 } 1361 1362 /* tell HW what we have processed */ 1363 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1364 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1365} 1366 1367static void 1368rt2860_tbtt_intr(struct rt2860_softc *sc) 1369{ 1370#if 0 1371 struct ieee80211com *ic = &sc->sc_ic; 1372 1373#ifndef IEEE80211_STA_ONLY 1374 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1375 /* one less beacon until next DTIM */ 1376 if (ic->ic_dtim_count == 0) 1377 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1378 else 1379 ic->ic_dtim_count--; 1380 1381 /* update dynamic parts of beacon */ 1382 rt2860_setup_beacon(sc); 1383 1384 /* flush buffered multicast frames */ 1385 if (ic->ic_dtim_count == 0) 1386 ieee80211_notify_dtim(ic); 1387 } 1388#endif 1389 /* check if protection mode has changed */ 1390 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1391 rt2860_updateprot(ic); 1392 sc->sc_ic_flags = ic->ic_flags; 1393 } 1394#endif 1395} 1396 1397static void 1398rt2860_gp_intr(struct rt2860_softc *sc) 1399{ 1400 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1401 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1402 1403 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1404 1405 if (vap->iv_state == IEEE80211_S_RUN) 1406 rt2860_updatestats(sc); 1407} 1408 1409void 1410rt2860_intr(void *arg) 1411{ 1412 struct rt2860_softc *sc = arg; 1413 uint32_t r; 1414 1415 RAL_LOCK(sc); 1416 1417#ifndef __HAIKU__ 1418 r = RAL_READ(sc, RT2860_INT_STATUS); 1419 if (__predict_false(r == 0xffffffff)) { 1420 RAL_UNLOCK(sc); 1421 return; /* device likely went away */ 1422 } 1423 if (r == 0) { 1424 RAL_UNLOCK(sc); 1425 return; /* not for us */ 1426 } 1427#else 1428 r = atomic_get((int32 *)&sc->sc_intr_status); 1429#endif 1430 1431 /* acknowledge interrupts */ 1432 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1433 1434 if (r & RT2860_TX_RX_COHERENT) 1435 rt2860_intr_coherent(sc); 1436 1437 if (r & RT2860_MAC_INT_2) /* TX status */ 1438 rt2860_drain_stats_fifo(sc); 1439 1440 if (r & RT2860_TX_DONE_INT5) 1441 rt2860_tx_intr(sc, 5); 1442 1443 if (r & RT2860_RX_DONE_INT) 1444 rt2860_rx_intr(sc); 1445 1446 if (r & RT2860_TX_DONE_INT4) 1447 rt2860_tx_intr(sc, 4); 1448 1449 if (r & RT2860_TX_DONE_INT3) 1450 rt2860_tx_intr(sc, 3); 1451 1452 if (r & RT2860_TX_DONE_INT2) 1453 rt2860_tx_intr(sc, 2); 1454 1455 if (r & RT2860_TX_DONE_INT1) 1456 rt2860_tx_intr(sc, 1); 1457 1458 if (r & RT2860_TX_DONE_INT0) 1459 rt2860_tx_intr(sc, 0); 1460 1461 if (r & RT2860_MAC_INT_0) /* TBTT */ 1462 rt2860_tbtt_intr(sc); 1463 1464 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1465 /* TBD wakeup */; 1466 1467 if (r & RT2860_MAC_INT_4) /* GP timer */ 1468 rt2860_gp_intr(sc); 1469 1470 RAL_UNLOCK(sc); 1471} 1472 1473static int 1474rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1475{ 1476 struct ifnet *ifp = sc->sc_ifp; 1477 struct ieee80211com *ic = ifp->if_l2com; 1478 struct ieee80211vap *vap = ni->ni_vap; 1479 struct rt2860_tx_ring *ring; 1480 struct rt2860_tx_data *data; 1481 struct rt2860_txd *txd; 1482 struct rt2860_txwi *txwi; 1483 struct ieee80211_frame *wh; 1484 const struct ieee80211_txparam *tp; 1485 struct ieee80211_key *k; 1486 struct mbuf *m1; 1487 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1488 bus_dma_segment_t *seg; 1489 u_int hdrlen; 1490 uint16_t qos, dur; 1491 uint8_t type, qsel, mcs, pid, tid, qid; 1492 int i, nsegs, ntxds, pad, rate, ridx, error; 1493 1494 /* the data pool contains at least one element, pick the first */ 1495 data = SLIST_FIRST(&sc->data_pool); 1496 1497 wh = mtod(m, struct ieee80211_frame *); 1498 1499 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1500 k = ieee80211_crypto_encap(ni, m); 1501 if (k == NULL) { 1502 m_freem(m); 1503 return ENOBUFS; 1504 } 1505 1506 /* packet header may have moved, reset our local pointer */ 1507 wh = mtod(m, struct ieee80211_frame *); 1508 } 1509 1510 hdrlen = ieee80211_anyhdrsize(wh); 1511 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1512 1513 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1514 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1515 rate = tp->mcastrate; 1516 } else if (m->m_flags & M_EAPOL) { 1517 rate = tp->mgmtrate; 1518 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1519 rate = tp->ucastrate; 1520 } else { 1521 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1522 rate = ni->ni_txrate; 1523 } 1524 rate &= IEEE80211_RATE_VAL; 1525 1526 qid = M_WME_GETAC(m); 1527 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1528 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1529 tid = qos & IEEE80211_QOS_TID; 1530 } else { 1531 qos = 0; 1532 tid = 0; 1533 } 1534 ring = &sc->txq[qid]; 1535 ridx = ic->ic_rt->rateCodeToIndex[rate]; 1536 1537 /* get MCS code from rate index */ 1538 mcs = rt2860_rates[ridx].mcs; 1539 1540 /* setup TX Wireless Information */ 1541 txwi = data->txwi; 1542 txwi->flags = 0; 1543 /* let HW generate seq numbers for non-QoS frames */ 1544 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1545 if (type == IEEE80211_FC0_TYPE_DATA) 1546 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1547 else 1548 txwi->wcid = 0xff; 1549 txwi->len = htole16(m->m_pkthdr.len); 1550 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1551 txwi->phy = htole16(RT2860_PHY_CCK); 1552 if (ridx != RT2860_RIDX_CCK1 && 1553 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1554 mcs |= RT2860_PHY_SHPRE; 1555 } else 1556 txwi->phy = htole16(RT2860_PHY_OFDM); 1557 txwi->phy |= htole16(mcs); 1558 1559 /* 1560 * We store the MCS code into the driver-private PacketID field. 1561 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1562 * that we know at which initial rate the frame was transmitted. 1563 * We add 1 to the MCS code because setting the PacketID field to 1564 * 0 means that we don't want feedback in TX_STAT_FIFO. 1565 */ 1566 pid = (mcs + 1) & 0xf; 1567 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1568 1569 /* check if RTS/CTS or CTS-to-self protection is required */ 1570 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1571 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1572 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1573 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1574 txwi->txop = RT2860_TX_TXOP_HT; 1575 else 1576 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1577 1578 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1579 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1580 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1581 txwi->xflags |= RT2860_TX_ACK; 1582 1583 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1584 dur = rt2860_rates[ridx].sp_ack_dur; 1585 else 1586 dur = rt2860_rates[ridx].lp_ack_dur; 1587 *(uint16_t *)wh->i_dur = htole16(dur); 1588 } 1589 /* ask MAC to insert timestamp into probe responses */ 1590 if ((wh->i_fc[0] & 1591 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1592 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1593 /* NOTE: beacons do not pass through tx_data() */ 1594 txwi->flags |= RT2860_TX_TS; 1595 1596 if (ieee80211_radiotap_active_vap(vap)) { 1597 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1598 1599 tap->wt_flags = 0; 1600 tap->wt_rate = rate; 1601 if (mcs & RT2860_PHY_SHPRE) 1602 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1603 1604 ieee80211_radiotap_tx(vap, m); 1605 } 1606 1607 pad = (hdrlen + 3) & ~3; 1608 1609 /* copy and trim 802.11 header */ 1610 memcpy(txwi + 1, wh, hdrlen); 1611 m_adj(m, hdrlen); 1612 1613 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1614 &nsegs, 0); 1615 if (__predict_false(error != 0 && error != EFBIG)) { 1616 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1617 error); 1618 m_freem(m); 1619 return error; 1620 } 1621 if (__predict_true(error == 0)) { 1622 /* determine how many TXDs are required */ 1623 ntxds = 1 + (nsegs / 2); 1624 1625 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1626 /* not enough free TXDs, force mbuf defrag */ 1627 bus_dmamap_unload(sc->txwi_dmat, data->map); 1628 error = EFBIG; 1629 } 1630 } 1631 if (__predict_false(error != 0)) { 1632 m1 = m_defrag(m, M_DONTWAIT); 1633 if (m1 == NULL) { 1634 device_printf(sc->sc_dev, 1635 "could not defragment mbuf\n"); 1636 m_freem(m); 1637 return ENOBUFS; 1638 } 1639 m = m1; 1640 1641 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1642 segs, &nsegs, 0); 1643 if (__predict_false(error != 0)) { 1644 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1645 error); 1646 m_freem(m); 1647 return error; 1648 } 1649 1650 /* determine how many TXDs are now required */ 1651 ntxds = 1 + (nsegs / 2); 1652 1653 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1654 /* this is a hopeless case, drop the mbuf! */ 1655 bus_dmamap_unload(sc->txwi_dmat, data->map); 1656 m_freem(m); 1657 return ENOBUFS; 1658 } 1659 } 1660 1661 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1662 1663 /* first segment is TXWI + 802.11 header */ 1664 txd = &ring->txd[ring->cur]; 1665 txd->sdp0 = htole32(data->paddr); 1666 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1667 txd->flags = qsel; 1668 1669 /* setup payload segments */ 1670 seg = &segs[0]; 1671 for (i = nsegs; i >= 2; i -= 2) { 1672 txd->sdp1 = htole32(seg->ds_addr); 1673 txd->sdl1 = htole16(seg->ds_len); 1674 seg++; 1675 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1676 /* grab a new Tx descriptor */ 1677 txd = &ring->txd[ring->cur]; 1678 txd->sdp0 = htole32(seg->ds_addr); 1679 txd->sdl0 = htole16(seg->ds_len); 1680 txd->flags = qsel; 1681 seg++; 1682 } 1683 /* finalize last segment */ 1684 if (i > 0) { 1685 txd->sdp1 = htole32(seg->ds_addr); 1686 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1687 } else { 1688 txd->sdl0 |= htole16(RT2860_TX_LS0); 1689 txd->sdl1 = 0; 1690 } 1691 1692 /* remove from the free pool and link it into the SW Tx slot */ 1693 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1694 data->m = m; 1695 data->ni = ni; 1696 ring->data[ring->cur] = data; 1697 1698 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1699 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1700 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1701 1702 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1703 qid, txwi->wcid, nsegs, ridx)); 1704 1705 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1706 ring->queued += ntxds; 1707 if (ring->queued >= RT2860_TX_RING_COUNT) 1708 sc->qfullmsk |= 1 << qid; 1709 1710 /* kick Tx */ 1711 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1712 1713 return 0; 1714} 1715 1716static int 1717rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1718 const struct ieee80211_bpf_params *params) 1719{ 1720 struct ieee80211com *ic = ni->ni_ic; 1721 struct ifnet *ifp = ic->ic_ifp; 1722 struct rt2860_softc *sc = ifp->if_softc; 1723 int error; 1724 1725 RAL_LOCK(sc); 1726 1727 /* prevent management frames from being sent if we're not ready */ 1728 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1729 RAL_UNLOCK(sc); 1730 m_freem(m); 1731 ieee80211_free_node(ni); 1732 return ENETDOWN; 1733 } 1734 if (params == NULL) { 1735 /* 1736 * Legacy path; interpret frame contents to decide 1737 * precisely how to send the frame. 1738 */ 1739 error = rt2860_tx(sc, m, ni); 1740 } else { 1741 /* 1742 * Caller supplied explicit parameters to use in 1743 * sending the frame. 1744 */ 1745 error = rt2860_tx_raw(sc, m, ni, params); 1746 } 1747 if (error != 0) { 1748 /* NB: m is reclaimed on tx failure */ 1749 ieee80211_free_node(ni); 1750 ifp->if_oerrors++; 1751 } 1752 sc->sc_tx_timer = 5; 1753 RAL_UNLOCK(sc); 1754 return error; 1755} 1756 1757static int 1758rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1759 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1760{ 1761 struct ifnet *ifp = sc->sc_ifp; 1762 struct ieee80211com *ic = ifp->if_l2com; 1763 struct ieee80211vap *vap = ni->ni_vap; 1764 struct rt2860_tx_ring *ring; 1765 struct rt2860_tx_data *data; 1766 struct rt2860_txd *txd; 1767 struct rt2860_txwi *txwi; 1768 struct ieee80211_frame *wh; 1769 struct mbuf *m1; 1770 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1771 bus_dma_segment_t *seg; 1772 u_int hdrlen; 1773 uint16_t dur; 1774 uint8_t type, qsel, mcs, pid, tid, qid; 1775 int i, nsegs, ntxds, pad, rate, ridx, error; 1776 1777 /* the data pool contains at least one element, pick the first */ 1778 data = SLIST_FIRST(&sc->data_pool); 1779 1780 wh = mtod(m, struct ieee80211_frame *); 1781 hdrlen = ieee80211_hdrsize(wh); 1782 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1783 1784 /* Choose a TX rate index. */ 1785 rate = params->ibp_rate0; 1786 ridx = ic->ic_rt->rateCodeToIndex[rate]; 1787 if (ridx == (uint8_t)-1) { 1788 /* XXX fall back to mcast/mgmt rate? */ 1789 m_freem(m); 1790 return EINVAL; 1791 } 1792 1793 qid = params->ibp_pri & 3; 1794 tid = 0; 1795 ring = &sc->txq[qid]; 1796 1797 /* get MCS code from rate index */ 1798 mcs = rt2860_rates[ridx].mcs; 1799 1800 /* setup TX Wireless Information */ 1801 txwi = data->txwi; 1802 txwi->flags = 0; 1803 /* let HW generate seq numbers for non-QoS frames */ 1804 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1805 txwi->wcid = 0xff; 1806 txwi->len = htole16(m->m_pkthdr.len); 1807 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1808 txwi->phy = htole16(RT2860_PHY_CCK); 1809 if (ridx != RT2860_RIDX_CCK1 && 1810 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1811 mcs |= RT2860_PHY_SHPRE; 1812 } else 1813 txwi->phy = htole16(RT2860_PHY_OFDM); 1814 txwi->phy |= htole16(mcs); 1815 1816 /* 1817 * We store the MCS code into the driver-private PacketID field. 1818 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1819 * that we know at which initial rate the frame was transmitted. 1820 * We add 1 to the MCS code because setting the PacketID field to 1821 * 0 means that we don't want feedback in TX_STAT_FIFO. 1822 */ 1823 pid = (mcs + 1) & 0xf; 1824 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1825 1826 /* check if RTS/CTS or CTS-to-self protection is required */ 1827 if (params->ibp_flags & IEEE80211_BPF_RTS || 1828 params->ibp_flags & IEEE80211_BPF_CTS) 1829 txwi->txop = RT2860_TX_TXOP_HT; 1830 else 1831 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1832 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1833 txwi->xflags |= RT2860_TX_ACK; 1834 1835 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1836 dur = rt2860_rates[ridx].sp_ack_dur; 1837 else 1838 dur = rt2860_rates[ridx].lp_ack_dur; 1839 *(uint16_t *)wh->i_dur = htole16(dur); 1840 } 1841 /* ask MAC to insert timestamp into probe responses */ 1842 if ((wh->i_fc[0] & 1843 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1844 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1845 /* NOTE: beacons do not pass through tx_data() */ 1846 txwi->flags |= RT2860_TX_TS; 1847 1848 if (ieee80211_radiotap_active_vap(vap)) { 1849 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1850 1851 tap->wt_flags = 0; 1852 tap->wt_rate = rate; 1853 if (mcs & RT2860_PHY_SHPRE) 1854 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1855 1856 ieee80211_radiotap_tx(vap, m); 1857 } 1858 1859 pad = (hdrlen + 3) & ~3; 1860 1861 /* copy and trim 802.11 header */ 1862 memcpy(txwi + 1, wh, hdrlen); 1863 m_adj(m, hdrlen); 1864 1865 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1866 &nsegs, 0); 1867 if (__predict_false(error != 0 && error != EFBIG)) { 1868 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1869 error); 1870 m_freem(m); 1871 return error; 1872 } 1873 if (__predict_true(error == 0)) { 1874 /* determine how many TXDs are required */ 1875 ntxds = 1 + (nsegs / 2); 1876 1877 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1878 /* not enough free TXDs, force mbuf defrag */ 1879 bus_dmamap_unload(sc->txwi_dmat, data->map); 1880 error = EFBIG; 1881 } 1882 } 1883 if (__predict_false(error != 0)) { 1884 m1 = m_defrag(m, M_DONTWAIT); 1885 if (m1 == NULL) { 1886 device_printf(sc->sc_dev, 1887 "could not defragment mbuf\n"); 1888 m_freem(m); 1889 return ENOBUFS; 1890 } 1891 m = m1; 1892 1893 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1894 segs, &nsegs, 0); 1895 if (__predict_false(error != 0)) { 1896 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1897 error); 1898 m_freem(m); 1899 return error; 1900 } 1901 1902 /* determine how many TXDs are now required */ 1903 ntxds = 1 + (nsegs / 2); 1904 1905 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1906 /* this is a hopeless case, drop the mbuf! */ 1907 bus_dmamap_unload(sc->txwi_dmat, data->map); 1908 m_freem(m); 1909 return ENOBUFS; 1910 } 1911 } 1912 1913 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1914 1915 /* first segment is TXWI + 802.11 header */ 1916 txd = &ring->txd[ring->cur]; 1917 txd->sdp0 = htole32(data->paddr); 1918 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1919 txd->flags = qsel; 1920 1921 /* setup payload segments */ 1922 seg = &segs[0]; 1923 for (i = nsegs; i >= 2; i -= 2) { 1924 txd->sdp1 = htole32(seg->ds_addr); 1925 txd->sdl1 = htole16(seg->ds_len); 1926 seg++; 1927 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1928 /* grab a new Tx descriptor */ 1929 txd = &ring->txd[ring->cur]; 1930 txd->sdp0 = htole32(seg->ds_addr); 1931 txd->sdl0 = htole16(seg->ds_len); 1932 txd->flags = qsel; 1933 seg++; 1934 } 1935 /* finalize last segment */ 1936 if (i > 0) { 1937 txd->sdp1 = htole32(seg->ds_addr); 1938 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1939 } else { 1940 txd->sdl0 |= htole16(RT2860_TX_LS0); 1941 txd->sdl1 = 0; 1942 } 1943 1944 /* remove from the free pool and link it into the SW Tx slot */ 1945 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1946 data->m = m; 1947 data->ni = ni; 1948 ring->data[ring->cur] = data; 1949 1950 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1951 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1952 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1953 1954 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1955 qid, txwi->wcid, nsegs, ridx)); 1956 1957 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1958 ring->queued += ntxds; 1959 if (ring->queued >= RT2860_TX_RING_COUNT) 1960 sc->qfullmsk |= 1 << qid; 1961 1962 /* kick Tx */ 1963 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1964 1965 return 0; 1966} 1967 1968static void 1969rt2860_start(struct ifnet *ifp) 1970{ 1971 struct rt2860_softc *sc = ifp->if_softc; 1972 1973 RAL_LOCK(sc); 1974 rt2860_start_locked(ifp); 1975 RAL_UNLOCK(sc); 1976} 1977 1978static void 1979rt2860_start_locked(struct ifnet *ifp) 1980{ 1981 struct rt2860_softc *sc = ifp->if_softc; 1982 struct ieee80211_node *ni; 1983 struct mbuf *m; 1984 1985 RAL_LOCK_ASSERT(sc); 1986 1987 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1988 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) 1989 return; 1990 1991 for (;;) { 1992 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1993 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1994 break; 1995 } 1996 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1997 if (m == NULL) 1998 break; 1999 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2000 if (rt2860_tx(sc, m, ni) != 0) { 2001 ieee80211_free_node(ni); 2002 ifp->if_oerrors++; 2003 continue; 2004 } 2005 sc->sc_tx_timer = 5; 2006 } 2007} 2008 2009static void 2010rt2860_watchdog(void *arg) 2011{ 2012 struct rt2860_softc *sc = arg; 2013 struct ifnet *ifp = sc->sc_ifp; 2014 2015 RAL_LOCK_ASSERT(sc); 2016 2017 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 2018 2019 if (sc->sc_invalid) /* card ejected */ 2020 return; 2021 2022 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 2023 if_printf(ifp, "device timeout\n"); 2024 rt2860_stop_locked(sc); 2025 rt2860_init_locked(sc); 2026 ifp->if_oerrors++; 2027 return; 2028 } 2029 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2030} 2031 2032static int 2033rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2034{ 2035 struct rt2860_softc *sc = ifp->if_softc; 2036 struct ieee80211com *ic = ifp->if_l2com; 2037 struct ifreq *ifr = (struct ifreq *)data; 2038 int error = 0, startall = 0; 2039 2040 switch (cmd) { 2041 case SIOCSIFFLAGS: 2042 RAL_LOCK(sc); 2043 if (ifp->if_flags & IFF_UP) { 2044 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2045 rt2860_init_locked(sc); 2046 startall = 1; 2047 } else 2048 rt2860_update_promisc(ifp); 2049 } else { 2050 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2051 rt2860_stop_locked(sc); 2052 } 2053 RAL_UNLOCK(sc); 2054 if (startall) 2055 ieee80211_start_all(ic); 2056 break; 2057 case SIOCGIFMEDIA: 2058 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 2059 break; 2060 case SIOCSIFADDR: 2061 error = ether_ioctl(ifp, cmd, data); 2062 break; 2063 default: 2064 error = EINVAL; 2065 break; 2066 } 2067 return error; 2068} 2069 2070/* 2071 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2072 * We access the BBP through the 8051 microcontroller unit which means that 2073 * the microcode must be loaded first. 2074 */ 2075void 2076rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2077{ 2078 int ntries; 2079 2080 for (ntries = 0; ntries < 100; ntries++) { 2081 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2082 break; 2083 DELAY(1); 2084 } 2085 if (ntries == 100) { 2086 device_printf(sc->sc_dev, 2087 "could not write to BBP through MCU\n"); 2088 return; 2089 } 2090 2091 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2092 RT2860_BBP_CSR_KICK | reg << 8 | val); 2093 RAL_BARRIER_WRITE(sc); 2094 2095 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2096 DELAY(1000); 2097} 2098 2099uint8_t 2100rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2101{ 2102 uint32_t val; 2103 int ntries; 2104 2105 for (ntries = 0; ntries < 100; ntries++) { 2106 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2107 break; 2108 DELAY(1); 2109 } 2110 if (ntries == 100) { 2111 device_printf(sc->sc_dev, 2112 "could not read from BBP through MCU\n"); 2113 return 0; 2114 } 2115 2116 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2117 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2118 RAL_BARRIER_WRITE(sc); 2119 2120 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2121 DELAY(1000); 2122 2123 for (ntries = 0; ntries < 100; ntries++) { 2124 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2125 if (!(val & RT2860_BBP_CSR_KICK)) 2126 return val & 0xff; 2127 DELAY(1); 2128 } 2129 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2130 2131 return 0; 2132} 2133 2134/* 2135 * Write to one of the 4 programmable 24-bit RF registers. 2136 */ 2137static void 2138rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2139{ 2140 uint32_t tmp; 2141 int ntries; 2142 2143 for (ntries = 0; ntries < 100; ntries++) { 2144 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2145 break; 2146 DELAY(1); 2147 } 2148 if (ntries == 100) { 2149 device_printf(sc->sc_dev, "could not write to RF\n"); 2150 return; 2151 } 2152 2153 /* RF registers are 24-bit on the RT2860 */ 2154 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2155 (val & 0x3fffff) << 2 | (reg & 3); 2156 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2157} 2158 2159static uint8_t 2160rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2161{ 2162 uint32_t tmp; 2163 int ntries; 2164 2165 for (ntries = 0; ntries < 100; ntries++) { 2166 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2167 break; 2168 DELAY(1); 2169 } 2170 if (ntries == 100) { 2171 device_printf(sc->sc_dev, "could not read RF register\n"); 2172 return 0xff; 2173 } 2174 tmp = RT3070_RF_KICK | reg << 8; 2175 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2176 2177 for (ntries = 0; ntries < 100; ntries++) { 2178 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2179 if (!(tmp & RT3070_RF_KICK)) 2180 break; 2181 DELAY(1); 2182 } 2183 if (ntries == 100) { 2184 device_printf(sc->sc_dev, "could not read RF register\n"); 2185 return 0xff; 2186 } 2187 return tmp & 0xff; 2188} 2189 2190void 2191rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2192{ 2193 uint32_t tmp; 2194 int ntries; 2195 2196 for (ntries = 0; ntries < 10; ntries++) { 2197 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2198 break; 2199 DELAY(10); 2200 } 2201 if (ntries == 10) { 2202 device_printf(sc->sc_dev, "could not write to RF\n"); 2203 return; 2204 } 2205 2206 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2207 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2208} 2209 2210/* 2211 * Send a command to the 8051 microcontroller unit. 2212 */ 2213int 2214rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2215{ 2216 int slot, ntries; 2217 uint32_t tmp; 2218 uint8_t cid; 2219 2220 for (ntries = 0; ntries < 100; ntries++) { 2221 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2222 break; 2223 DELAY(2); 2224 } 2225 if (ntries == 100) 2226 return EIO; 2227 2228 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2229 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2230 RAL_BARRIER_WRITE(sc); 2231 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2232 2233 if (!wait) 2234 return 0; 2235 /* wait for the command to complete */ 2236 for (ntries = 0; ntries < 200; ntries++) { 2237 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2238 /* find the command slot */ 2239 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2240 if ((tmp & 0xff) == cid) 2241 break; 2242 if (slot < 4) 2243 break; 2244 DELAY(100); 2245 } 2246 if (ntries == 200) { 2247 /* clear command and status */ 2248 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2249 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2250 return ETIMEDOUT; 2251 } 2252 /* get command status (1 means success) */ 2253 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2254 tmp = (tmp >> (slot * 8)) & 0xff; 2255 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2256 cmd, slot, tmp)); 2257 /* clear command and status */ 2258 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2259 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2260 return (tmp == 1) ? 0 : EIO; 2261} 2262 2263static void 2264rt2860_enable_mrr(struct rt2860_softc *sc) 2265{ 2266#define CCK(mcs) (mcs) 2267#define OFDM(mcs) (1 << 3 | (mcs)) 2268 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2269 OFDM(6) << 28 | /* 54->48 */ 2270 OFDM(5) << 24 | /* 48->36 */ 2271 OFDM(4) << 20 | /* 36->24 */ 2272 OFDM(3) << 16 | /* 24->18 */ 2273 OFDM(2) << 12 | /* 18->12 */ 2274 OFDM(1) << 8 | /* 12-> 9 */ 2275 OFDM(0) << 4 | /* 9-> 6 */ 2276 OFDM(0)); /* 6-> 6 */ 2277 2278 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2279 CCK(2) << 12 | /* 11->5.5 */ 2280 CCK(1) << 8 | /* 5.5-> 2 */ 2281 CCK(0) << 4 | /* 2-> 1 */ 2282 CCK(0)); /* 1-> 1 */ 2283#undef OFDM 2284#undef CCK 2285} 2286 2287static void 2288rt2860_set_txpreamble(struct rt2860_softc *sc) 2289{ 2290 struct ifnet *ifp = sc->sc_ifp; 2291 struct ieee80211com *ic = ifp->if_l2com; 2292 uint32_t tmp; 2293 2294 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2295 tmp &= ~RT2860_CCK_SHORT_EN; 2296 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2297 tmp |= RT2860_CCK_SHORT_EN; 2298 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2299} 2300 2301void 2302rt2860_set_basicrates(struct rt2860_softc *sc, 2303 const struct ieee80211_rateset *rs) 2304{ 2305#define RV(r) ((r) & IEEE80211_RATE_VAL) 2306 struct ifnet *ifp = sc->sc_ifp; 2307 struct ieee80211com *ic = ifp->if_l2com; 2308 uint32_t mask = 0; 2309 uint8_t rate; 2310 int i; 2311 2312 for (i = 0; i < rs->rs_nrates; i++) { 2313 rate = rs->rs_rates[i]; 2314 2315 if (!(rate & IEEE80211_RATE_BASIC)) 2316 continue; 2317 2318 mask |= 1 << ic->ic_rt->rateCodeToIndex[RV(rate)]; 2319 } 2320 2321 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2322#undef RV 2323} 2324 2325static void 2326rt2860_scan_start(struct ieee80211com *ic) 2327{ 2328 struct ifnet *ifp = ic->ic_ifp; 2329 struct rt2860_softc *sc = ifp->if_softc; 2330 uint32_t tmp; 2331 2332 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2333 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2334 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2335 RT2860_TBTT_TIMER_EN)); 2336 rt2860_set_gp_timer(sc, 0); 2337} 2338 2339static void 2340rt2860_scan_end(struct ieee80211com *ic) 2341{ 2342 struct ifnet *ifp = ic->ic_ifp; 2343 struct rt2860_softc *sc = ifp->if_softc; 2344 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2345 2346 if (vap->iv_state == IEEE80211_S_RUN) { 2347 rt2860_enable_tsf_sync(sc); 2348 rt2860_set_gp_timer(sc, 500); 2349 } 2350} 2351 2352static void 2353rt2860_set_channel(struct ieee80211com *ic) 2354{ 2355 struct ifnet *ifp = ic->ic_ifp; 2356 struct rt2860_softc *sc = ifp->if_softc; 2357 2358 RAL_LOCK(sc); 2359 rt2860_switch_chan(sc, ic->ic_curchan); 2360 RAL_UNLOCK(sc); 2361} 2362 2363static void 2364rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2365{ 2366 uint32_t tmp; 2367 uint8_t agc; 2368 2369 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2370 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2371 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2372 rt2860_mcu_bbp_write(sc, 86, 0x00); 2373 2374 if (group == 0) { 2375 if (sc->ext_2ghz_lna) { 2376 rt2860_mcu_bbp_write(sc, 82, 0x62); 2377 rt2860_mcu_bbp_write(sc, 75, 0x46); 2378 } else { 2379 rt2860_mcu_bbp_write(sc, 82, 0x84); 2380 rt2860_mcu_bbp_write(sc, 75, 0x50); 2381 } 2382 } else { 2383 if (sc->ext_5ghz_lna) { 2384 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2385 rt2860_mcu_bbp_write(sc, 75, 0x46); 2386 } else { 2387 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2388 rt2860_mcu_bbp_write(sc, 75, 0x50); 2389 } 2390 } 2391 2392 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2393 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2394 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2395 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2396 2397 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2398 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2399 if (sc->nrxchains > 1) 2400 tmp |= RT2860_LNA_PE1_EN; 2401 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2402 tmp |= RT3593_LNA_PE2_EN; 2403 if (group == 0) { /* 2GHz */ 2404 tmp |= RT2860_PA_PE_G0_EN; 2405 if (sc->ntxchains > 1) 2406 tmp |= RT2860_PA_PE_G1_EN; 2407 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2408 tmp |= RT3593_PA_PE_G2_EN; 2409 } else { /* 5GHz */ 2410 tmp |= RT2860_PA_PE_A0_EN; 2411 if (sc->ntxchains > 1) 2412 tmp |= RT2860_PA_PE_A1_EN; 2413 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2414 tmp |= RT3593_PA_PE_A2_EN; 2415 } 2416 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2417 2418 if (sc->mac_ver == 0x3593) { 2419 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2420 if (sc->sc_flags & RT2860_PCIE) { 2421 tmp &= ~0x01010000; 2422 if (group == 0) 2423 tmp |= 0x00010000; 2424 } else { 2425 tmp &= ~0x00008080; 2426 if (group == 0) 2427 tmp |= 0x00000080; 2428 } 2429 tmp = (tmp & ~0x00001000) | 0x00000010; 2430 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2431 } 2432 2433 /* set initial AGC value */ 2434 if (group == 0) { /* 2GHz band */ 2435 if (sc->mac_ver >= 0x3071) 2436 agc = 0x1c + sc->lna[0] * 2; 2437 else 2438 agc = 0x2e + sc->lna[0]; 2439 } else { /* 5GHz band */ 2440 agc = 0x32 + (sc->lna[group] * 5) / 3; 2441 } 2442 rt2860_mcu_bbp_write(sc, 66, agc); 2443 2444 DELAY(1000); 2445} 2446 2447static void 2448rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2449{ 2450 const struct rfprog *rfprog = rt2860_rf2850; 2451 uint32_t r2, r3, r4; 2452 int8_t txpow1, txpow2; 2453 u_int i; 2454 2455 /* find the settings for this channel (we know it exists) */ 2456 for (i = 0; rfprog[i].chan != chan; i++); 2457 2458 r2 = rfprog[i].r2; 2459 if (sc->ntxchains == 1) 2460 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2461 if (sc->nrxchains == 1) 2462 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2463 else if (sc->nrxchains == 2) 2464 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2465 2466 /* use Tx power values from EEPROM */ 2467 txpow1 = sc->txpow1[i]; 2468 txpow2 = sc->txpow2[i]; 2469 if (chan > 14) { 2470 if (txpow1 >= 0) 2471 txpow1 = txpow1 << 1 | 1; 2472 else 2473 txpow1 = (7 + txpow1) << 1; 2474 if (txpow2 >= 0) 2475 txpow2 = txpow2 << 1 | 1; 2476 else 2477 txpow2 = (7 + txpow2) << 1; 2478 } 2479 r3 = rfprog[i].r3 | txpow1 << 7; 2480 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2481 2482 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2483 rt2860_rf_write(sc, RT2860_RF2, r2); 2484 rt2860_rf_write(sc, RT2860_RF3, r3); 2485 rt2860_rf_write(sc, RT2860_RF4, r4); 2486 2487 DELAY(200); 2488 2489 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2490 rt2860_rf_write(sc, RT2860_RF2, r2); 2491 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2492 rt2860_rf_write(sc, RT2860_RF4, r4); 2493 2494 DELAY(200); 2495 2496 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2497 rt2860_rf_write(sc, RT2860_RF2, r2); 2498 rt2860_rf_write(sc, RT2860_RF3, r3); 2499 rt2860_rf_write(sc, RT2860_RF4, r4); 2500} 2501 2502static void 2503rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2504{ 2505 int8_t txpow1, txpow2; 2506 uint8_t rf; 2507 int i; 2508 2509 /* RT3090 is 2GHz only */ 2510 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2511 2512 /* find the settings for this channel (we know it exists) */ 2513 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2514 2515 /* use Tx power values from EEPROM */ 2516 txpow1 = sc->txpow1[i]; 2517 txpow2 = sc->txpow2[i]; 2518 2519 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2520 rf = rt3090_rf_read(sc, 3); 2521 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2522 rt3090_rf_write(sc, 3, rf); 2523 rf = rt3090_rf_read(sc, 6); 2524 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2525 rt3090_rf_write(sc, 6, rf); 2526 2527 /* set Tx0 power */ 2528 rf = rt3090_rf_read(sc, 12); 2529 rf = (rf & ~0x1f) | txpow1; 2530 rt3090_rf_write(sc, 12, rf); 2531 2532 /* set Tx1 power */ 2533 rf = rt3090_rf_read(sc, 13); 2534 rf = (rf & ~0x1f) | txpow2; 2535 rt3090_rf_write(sc, 13, rf); 2536 2537 rf = rt3090_rf_read(sc, 1); 2538 rf &= ~0xfc; 2539 if (sc->ntxchains == 1) 2540 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2541 else if (sc->ntxchains == 2) 2542 rf |= RT3070_TX2_PD; 2543 if (sc->nrxchains == 1) 2544 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2545 else if (sc->nrxchains == 2) 2546 rf |= RT3070_RX2_PD; 2547 rt3090_rf_write(sc, 1, rf); 2548 2549 /* set RF offset */ 2550 rf = rt3090_rf_read(sc, 23); 2551 rf = (rf & ~0x7f) | sc->freq; 2552 rt3090_rf_write(sc, 23, rf); 2553 2554 /* program RF filter */ 2555 rf = rt3090_rf_read(sc, 24); /* Tx */ 2556 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2557 rt3090_rf_write(sc, 24, rf); 2558 rf = rt3090_rf_read(sc, 31); /* Rx */ 2559 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2560 rt3090_rf_write(sc, 31, rf); 2561 2562 /* enable RF tuning */ 2563 rf = rt3090_rf_read(sc, 7); 2564 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2565} 2566 2567static int 2568rt3090_rf_init(struct rt2860_softc *sc) 2569{ 2570#define N(a) (sizeof (a) / sizeof ((a)[0])) 2571 uint32_t tmp; 2572 uint8_t rf, bbp; 2573 int i; 2574 2575 rf = rt3090_rf_read(sc, 30); 2576 /* toggle RF R30 bit 7 */ 2577 rt3090_rf_write(sc, 30, rf | 0x80); 2578 DELAY(1000); 2579 rt3090_rf_write(sc, 30, rf & ~0x80); 2580 2581 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2582 tmp &= ~0x1f000000; 2583 if (sc->patch_dac && sc->mac_rev < 0x0211) 2584 tmp |= 0x0d000000; /* 1.35V */ 2585 else 2586 tmp |= 0x01000000; /* 1.2V */ 2587 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2588 2589 /* patch LNA_PE_G1 */ 2590 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2591 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2592 2593 /* initialize RF registers to default value */ 2594 for (i = 0; i < N(rt3090_def_rf); i++) { 2595 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2596 rt3090_def_rf[i].val); 2597 } 2598 2599 /* select 20MHz bandwidth */ 2600 rt3090_rf_write(sc, 31, 0x14); 2601 2602 rf = rt3090_rf_read(sc, 6); 2603 rt3090_rf_write(sc, 6, rf | 0x40); 2604 2605 if (sc->mac_ver != 0x3593) { 2606 /* calibrate filter for 20MHz bandwidth */ 2607 sc->rf24_20mhz = 0x1f; /* default value */ 2608 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2609 2610 /* select 40MHz bandwidth */ 2611 bbp = rt2860_mcu_bbp_read(sc, 4); 2612 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2613 rf = rt3090_rf_read(sc, 31); 2614 rt3090_rf_write(sc, 31, rf | 0x20); 2615 2616 /* calibrate filter for 40MHz bandwidth */ 2617 sc->rf24_40mhz = 0x2f; /* default value */ 2618 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2619 2620 /* go back to 20MHz bandwidth */ 2621 bbp = rt2860_mcu_bbp_read(sc, 4); 2622 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2623 } 2624 if (sc->mac_rev < 0x0211) 2625 rt3090_rf_write(sc, 27, 0x03); 2626 2627 tmp = RAL_READ(sc, RT3070_OPT_14); 2628 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2629 2630 if (sc->rf_rev == RT3070_RF_3020) 2631 rt3090_set_rx_antenna(sc, 0); 2632 2633 bbp = rt2860_mcu_bbp_read(sc, 138); 2634 if (sc->mac_ver == 0x3593) { 2635 if (sc->ntxchains == 1) 2636 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2637 else if (sc->ntxchains == 2) 2638 bbp |= 0x40; /* turn off DAC2 */ 2639 if (sc->nrxchains == 1) 2640 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2641 else if (sc->nrxchains == 2) 2642 bbp &= ~0x04; /* turn off ADC2 */ 2643 } else { 2644 if (sc->ntxchains == 1) 2645 bbp |= 0x20; /* turn off DAC1 */ 2646 if (sc->nrxchains == 1) 2647 bbp &= ~0x02; /* turn off ADC1 */ 2648 } 2649 rt2860_mcu_bbp_write(sc, 138, bbp); 2650 2651 rf = rt3090_rf_read(sc, 1); 2652 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2653 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2654 rt3090_rf_write(sc, 1, rf); 2655 2656 rf = rt3090_rf_read(sc, 15); 2657 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2658 2659 rf = rt3090_rf_read(sc, 17); 2660 rf &= ~RT3070_TX_LO1; 2661 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2662 rf |= 0x20; /* fix for long range Rx issue */ 2663 if (sc->txmixgain_2ghz >= 2) 2664 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2665 rt3090_rf_write(sc, 17, rf); 2666 2667 rf = rt3090_rf_read(sc, 20); 2668 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2669 2670 rf = rt3090_rf_read(sc, 21); 2671 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2672 2673 return 0; 2674#undef N 2675} 2676 2677void 2678rt3090_rf_wakeup(struct rt2860_softc *sc) 2679{ 2680 uint32_t tmp; 2681 uint8_t rf; 2682 2683 if (sc->mac_ver == 0x3593) { 2684 /* enable VCO */ 2685 rf = rt3090_rf_read(sc, 1); 2686 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2687 2688 /* initiate VCO calibration */ 2689 rf = rt3090_rf_read(sc, 3); 2690 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2691 2692 /* enable VCO bias current control */ 2693 rf = rt3090_rf_read(sc, 6); 2694 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2695 2696 /* initiate res calibration */ 2697 rf = rt3090_rf_read(sc, 2); 2698 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2699 2700 /* set reference current control to 0.33 mA */ 2701 rf = rt3090_rf_read(sc, 22); 2702 rf &= ~RT3593_CP_IC_MASK; 2703 rf |= 1 << RT3593_CP_IC_SHIFT; 2704 rt3090_rf_write(sc, 22, rf); 2705 2706 /* enable RX CTB */ 2707 rf = rt3090_rf_read(sc, 46); 2708 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2709 2710 rf = rt3090_rf_read(sc, 20); 2711 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2712 rt3090_rf_write(sc, 20, rf); 2713 } else { 2714 /* enable RF block */ 2715 rf = rt3090_rf_read(sc, 1); 2716 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2717 2718 /* enable VCO bias current control */ 2719 rf = rt3090_rf_read(sc, 7); 2720 rt3090_rf_write(sc, 7, rf | 0x30); 2721 2722 rf = rt3090_rf_read(sc, 9); 2723 rt3090_rf_write(sc, 9, rf | 0x0e); 2724 2725 /* enable RX CTB */ 2726 rf = rt3090_rf_read(sc, 21); 2727 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2728 2729 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2730 rf = rt3090_rf_read(sc, 27); 2731 rf &= ~0x77; 2732 if (sc->mac_rev < 0x0211) 2733 rf |= 0x03; 2734 rt3090_rf_write(sc, 27, rf); 2735 } 2736 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2737 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2738 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2739 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2740 } 2741} 2742 2743int 2744rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2745 uint8_t *val) 2746{ 2747 uint8_t rf22, rf24; 2748 uint8_t bbp55_pb, bbp55_sb, delta; 2749 int ntries; 2750 2751 /* program filter */ 2752 rf24 = rt3090_rf_read(sc, 24); 2753 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2754 rt3090_rf_write(sc, 24, rf24); 2755 2756 /* enable baseband loopback mode */ 2757 rf22 = rt3090_rf_read(sc, 22); 2758 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2759 2760 /* set power and frequency of passband test tone */ 2761 rt2860_mcu_bbp_write(sc, 24, 0x00); 2762 for (ntries = 0; ntries < 100; ntries++) { 2763 /* transmit test tone */ 2764 rt2860_mcu_bbp_write(sc, 25, 0x90); 2765 DELAY(1000); 2766 /* read received power */ 2767 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2768 if (bbp55_pb != 0) 2769 break; 2770 } 2771 if (ntries == 100) 2772 return ETIMEDOUT; 2773 2774 /* set power and frequency of stopband test tone */ 2775 rt2860_mcu_bbp_write(sc, 24, 0x06); 2776 for (ntries = 0; ntries < 100; ntries++) { 2777 /* transmit test tone */ 2778 rt2860_mcu_bbp_write(sc, 25, 0x90); 2779 DELAY(1000); 2780 /* read received power */ 2781 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2782 2783 delta = bbp55_pb - bbp55_sb; 2784 if (delta > target) 2785 break; 2786 2787 /* reprogram filter */ 2788 rf24++; 2789 rt3090_rf_write(sc, 24, rf24); 2790 } 2791 if (ntries < 100) { 2792 if (rf24 != init) 2793 rf24--; /* backtrack */ 2794 *val = rf24; 2795 rt3090_rf_write(sc, 24, rf24); 2796 } 2797 2798 /* restore initial state */ 2799 rt2860_mcu_bbp_write(sc, 24, 0x00); 2800 2801 /* disable baseband loopback mode */ 2802 rf22 = rt3090_rf_read(sc, 22); 2803 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2804 2805 return 0; 2806} 2807 2808static void 2809rt3090_rf_setup(struct rt2860_softc *sc) 2810{ 2811 uint8_t bbp; 2812 int i; 2813 2814 if (sc->mac_rev >= 0x0211) { 2815 /* enable DC filter */ 2816 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2817 2818 /* improve power consumption */ 2819 bbp = rt2860_mcu_bbp_read(sc, 31); 2820 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2821 } 2822 2823 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2824 if (sc->mac_rev < 0x0211) { 2825 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2826 sc->patch_dac ? 0x2c : 0x0f); 2827 } else 2828 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2829 2830 /* initialize RF registers from ROM */ 2831 for (i = 0; i < 10; i++) { 2832 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2833 continue; 2834 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2835 } 2836} 2837 2838static void 2839rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2840{ 2841 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2842 which | (sc->leds & 0x7f), 0); 2843} 2844 2845/* 2846 * Hardware has a general-purpose programmable timer interrupt that can 2847 * periodically raise MAC_INT_4. 2848 */ 2849static void 2850rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2851{ 2852 uint32_t tmp; 2853 2854 /* disable GP timer before reprogramming it */ 2855 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2856 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2857 2858 if (ms == 0) 2859 return; 2860 2861 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2862 ms *= 16; /* Unit: 64us */ 2863 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2864 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2865 2866 /* enable GP timer */ 2867 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2868 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2869} 2870 2871static void 2872rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2873{ 2874 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2875 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2876 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2877 bssid[4] | bssid[5] << 8); 2878} 2879 2880static void 2881rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2882{ 2883 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2884 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2885 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2886 addr[4] | addr[5] << 8 | 0xff << 16); 2887} 2888 2889static void 2890rt2860_updateslot(struct ifnet *ifp) 2891{ 2892 struct rt2860_softc *sc = ifp->if_softc; 2893 struct ieee80211com *ic = ifp->if_l2com; 2894 uint32_t tmp; 2895 2896 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 2897 tmp &= ~0xff; 2898 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2899 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 2900} 2901 2902static void 2903rt2860_updateprot(struct ifnet *ifp) 2904{ 2905 struct rt2860_softc *sc = ifp->if_softc; 2906 struct ieee80211com *ic = ifp->if_l2com; 2907 uint32_t tmp; 2908 2909 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 2910 /* setup protection frame rate (MCS code) */ 2911 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 2912 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 2913 rt2860_rates[RT2860_RIDX_CCK11].mcs; 2914 2915 /* CCK frames don't require protection */ 2916 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 2917 2918 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2919 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2920 tmp |= RT2860_PROT_CTRL_RTS_CTS; 2921 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2922 tmp |= RT2860_PROT_CTRL_CTS; 2923 } 2924 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 2925} 2926 2927static void 2928rt2860_update_promisc(struct ifnet *ifp) 2929{ 2930 struct rt2860_softc *sc = ifp->if_softc; 2931 uint32_t tmp; 2932 2933 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 2934 tmp &= ~RT2860_DROP_NOT_MYBSS; 2935 if (!(ifp->if_flags & IFF_PROMISC)) 2936 tmp |= RT2860_DROP_NOT_MYBSS; 2937 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 2938} 2939 2940static int 2941rt2860_updateedca(struct ieee80211com *ic) 2942{ 2943 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 2944 const struct wmeParams *wmep; 2945 int aci; 2946 2947 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2948 2949 /* update MAC TX configuration registers */ 2950 for (aci = 0; aci < WME_NUM_AC; aci++) { 2951 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 2952 wmep[aci].wmep_logcwmax << 16 | 2953 wmep[aci].wmep_logcwmin << 12 | 2954 wmep[aci].wmep_aifsn << 8 | 2955 wmep[aci].wmep_txopLimit); 2956 } 2957 2958 /* update SCH/DMA registers too */ 2959 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 2960 wmep[WME_AC_VO].wmep_aifsn << 12 | 2961 wmep[WME_AC_VI].wmep_aifsn << 8 | 2962 wmep[WME_AC_BK].wmep_aifsn << 4 | 2963 wmep[WME_AC_BE].wmep_aifsn); 2964 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 2965 wmep[WME_AC_VO].wmep_logcwmin << 12 | 2966 wmep[WME_AC_VI].wmep_logcwmin << 8 | 2967 wmep[WME_AC_BK].wmep_logcwmin << 4 | 2968 wmep[WME_AC_BE].wmep_logcwmin); 2969 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 2970 wmep[WME_AC_VO].wmep_logcwmax << 12 | 2971 wmep[WME_AC_VI].wmep_logcwmax << 8 | 2972 wmep[WME_AC_BK].wmep_logcwmax << 4 | 2973 wmep[WME_AC_BE].wmep_logcwmax); 2974 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 2975 wmep[WME_AC_BK].wmep_txopLimit << 16 | 2976 wmep[WME_AC_BE].wmep_txopLimit); 2977 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 2978 wmep[WME_AC_VO].wmep_txopLimit << 16 | 2979 wmep[WME_AC_VI].wmep_txopLimit); 2980 2981 return 0; 2982} 2983 2984#ifdef HW_CRYPTO 2985static int 2986rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2987 struct ieee80211_key *k) 2988{ 2989 struct rt2860_softc *sc = ic->ic_softc; 2990 bus_size_t base; 2991 uint32_t attr; 2992 uint8_t mode, wcid, iv[8]; 2993 2994 /* defer setting of WEP keys until interface is brought up */ 2995 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2996 (IFF_UP | IFF_RUNNING)) 2997 return 0; 2998 2999 /* map net80211 cipher to RT2860 security mode */ 3000 switch (k->k_cipher) { 3001 case IEEE80211_CIPHER_WEP40: 3002 mode = RT2860_MODE_WEP40; 3003 break; 3004 case IEEE80211_CIPHER_WEP104: 3005 mode = RT2860_MODE_WEP104; 3006 break; 3007 case IEEE80211_CIPHER_TKIP: 3008 mode = RT2860_MODE_TKIP; 3009 break; 3010 case IEEE80211_CIPHER_CCMP: 3011 mode = RT2860_MODE_AES_CCMP; 3012 break; 3013 default: 3014 return EINVAL; 3015 } 3016 3017 if (k->k_flags & IEEE80211_KEY_GROUP) { 3018 wcid = 0; /* NB: update WCID0 for group keys */ 3019 base = RT2860_SKEY(0, k->k_id); 3020 } else { 3021 wcid = ((struct rt2860_node *)ni)->wcid; 3022 base = RT2860_PKEY(wcid); 3023 } 3024 3025 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3026 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3027#ifndef IEEE80211_STA_ONLY 3028 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3029 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3030 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3031 } else 3032#endif 3033 { 3034 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3035 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3036 } 3037 } else 3038 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3039 3040 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3041 (k->k_flags & IEEE80211_KEY_TX)) { 3042 /* set initial packet number in IV+EIV */ 3043 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3044 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3045 uint32_t val = arc4random(); 3046 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3047 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3048 val += 0x000100; 3049 iv[0] = val; 3050 iv[1] = val >> 8; 3051 iv[2] = val >> 16; 3052 iv[3] = k->k_id << 6; 3053 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3054 } else { 3055 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3056 iv[0] = k->k_tsc >> 8; 3057 iv[1] = (iv[0] | 0x20) & 0x7f; 3058 iv[2] = k->k_tsc; 3059 } else /* CCMP */ { 3060 iv[0] = k->k_tsc; 3061 iv[1] = k->k_tsc >> 8; 3062 iv[2] = 0; 3063 } 3064 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3065 iv[4] = k->k_tsc >> 16; 3066 iv[5] = k->k_tsc >> 24; 3067 iv[6] = k->k_tsc >> 32; 3068 iv[7] = k->k_tsc >> 40; 3069 } 3070 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3071 } 3072 3073 if (k->k_flags & IEEE80211_KEY_GROUP) { 3074 /* install group key */ 3075 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3076 attr &= ~(0xf << (k->k_id * 4)); 3077 attr |= mode << (k->k_id * 4); 3078 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3079 } else { 3080 /* install pairwise key */ 3081 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3082 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3083 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3084 } 3085 return 0; 3086} 3087 3088static void 3089rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3090 struct ieee80211_key *k) 3091{ 3092 struct rt2860_softc *sc = ic->ic_softc; 3093 uint32_t attr; 3094 uint8_t wcid; 3095 3096 if (k->k_flags & IEEE80211_KEY_GROUP) { 3097 /* remove group key */ 3098 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3099 attr &= ~(0xf << (k->k_id * 4)); 3100 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3101 3102 } else { 3103 /* remove pairwise key */ 3104 wcid = ((struct rt2860_node *)ni)->wcid; 3105 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3106 attr &= ~0xf; 3107 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3108 } 3109} 3110#endif 3111 3112static int8_t 3113rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3114{ 3115 struct ifnet *ifp = sc->sc_ifp; 3116 struct ieee80211com *ic = ifp->if_l2com; 3117 struct ieee80211_channel *c = ic->ic_curchan; 3118 int delta; 3119 3120 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3121 u_int chan = ieee80211_chan2ieee(ic, c); 3122 delta = sc->rssi_5ghz[rxchain]; 3123 3124 /* determine channel group */ 3125 if (chan <= 64) 3126 delta -= sc->lna[1]; 3127 else if (chan <= 128) 3128 delta -= sc->lna[2]; 3129 else 3130 delta -= sc->lna[3]; 3131 } else 3132 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3133 3134 return -12 - delta - rssi; 3135} 3136 3137/* 3138 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3139 * Used to adjust per-rate Tx power registers. 3140 */ 3141static __inline uint32_t 3142b4inc(uint32_t b32, int8_t delta) 3143{ 3144 int8_t i, b4; 3145 3146 for (i = 0; i < 8; i++) { 3147 b4 = b32 & 0xf; 3148 b4 += delta; 3149 if (b4 < 0) 3150 b4 = 0; 3151 else if (b4 > 0xf) 3152 b4 = 0xf; 3153 b32 = b32 >> 4 | b4 << 28; 3154 } 3155 return b32; 3156} 3157 3158static const char * 3159rt2860_get_rf(uint8_t rev) 3160{ 3161 switch (rev) { 3162 case RT2860_RF_2820: return "RT2820"; 3163 case RT2860_RF_2850: return "RT2850"; 3164 case RT2860_RF_2720: return "RT2720"; 3165 case RT2860_RF_2750: return "RT2750"; 3166 case RT3070_RF_3020: return "RT3020"; 3167 case RT3070_RF_2020: return "RT2020"; 3168 case RT3070_RF_3021: return "RT3021"; 3169 case RT3070_RF_3022: return "RT3022"; 3170 case RT3070_RF_3052: return "RT3052"; 3171 case RT3070_RF_3320: return "RT3320"; 3172 case RT3070_RF_3053: return "RT3053"; 3173 default: return "unknown"; 3174 } 3175} 3176 3177static int 3178rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3179{ 3180 int8_t delta_2ghz, delta_5ghz; 3181 uint32_t tmp; 3182 uint16_t val; 3183 int ridx, ant, i; 3184 3185 /* check whether the ROM is eFUSE ROM or EEPROM */ 3186 sc->sc_srom_read = rt2860_eeprom_read_2; 3187 if (sc->mac_ver >= 0x3071) { 3188 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3189 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3190 if (tmp & RT3070_SEL_EFUSE) 3191 sc->sc_srom_read = rt3090_efuse_read_2; 3192 } 3193 3194 /* read EEPROM version */ 3195 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3196 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 3197 3198 /* read MAC address */ 3199 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3200 macaddr[0] = val & 0xff; 3201 macaddr[1] = val >> 8; 3202 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3203 macaddr[2] = val & 0xff; 3204 macaddr[3] = val >> 8; 3205 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3206 macaddr[4] = val & 0xff; 3207 macaddr[5] = val >> 8; 3208 3209 /* read country code */ 3210 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3211 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3212 3213 /* read vendor BBP settings */ 3214 for (i = 0; i < 8; i++) { 3215 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3216 sc->bbp[i].val = val & 0xff; 3217 sc->bbp[i].reg = val >> 8; 3218 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3219 } 3220 if (sc->mac_ver >= 0x3071) { 3221 /* read vendor RF settings */ 3222 for (i = 0; i < 10; i++) { 3223 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3224 sc->rf[i].val = val & 0xff; 3225 sc->rf[i].reg = val >> 8; 3226 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3227 sc->rf[i].val)); 3228 } 3229 } 3230 3231 /* read RF frequency offset from EEPROM */ 3232 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3233 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3234 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3235 if ((val >> 8) != 0xff) { 3236 /* read LEDs operating mode */ 3237 sc->leds = val >> 8; 3238 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3239 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3240 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3241 } else { 3242 /* broken EEPROM, use default settings */ 3243 sc->leds = 0x01; 3244 sc->led[0] = 0x5555; 3245 sc->led[1] = 0x2221; 3246 sc->led[2] = 0xa9f8; 3247 } 3248 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3249 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3250 3251 /* read RF information */ 3252 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3253 if (val == 0xffff) { 3254 DPRINTF(("invalid EEPROM antenna info, using default\n")); 3255 if (sc->mac_ver == 0x3593) { 3256 /* default to RF3053 3T3R */ 3257 sc->rf_rev = RT3070_RF_3053; 3258 sc->ntxchains = 3; 3259 sc->nrxchains = 3; 3260 } else if (sc->mac_ver >= 0x3071) { 3261 /* default to RF3020 1T1R */ 3262 sc->rf_rev = RT3070_RF_3020; 3263 sc->ntxchains = 1; 3264 sc->nrxchains = 1; 3265 } else { 3266 /* default to RF2820 1T2R */ 3267 sc->rf_rev = RT2860_RF_2820; 3268 sc->ntxchains = 1; 3269 sc->nrxchains = 2; 3270 } 3271 } else { 3272 sc->rf_rev = (val >> 8) & 0xf; 3273 sc->ntxchains = (val >> 4) & 0xf; 3274 sc->nrxchains = val & 0xf; 3275 } 3276 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3277 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3278 3279 /* check if RF supports automatic Tx access gain control */ 3280 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3281 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3282 /* check if driver should patch the DAC issue */ 3283 if ((val >> 8) != 0xff) 3284 sc->patch_dac = (val >> 15) & 1; 3285 if ((val & 0xff) != 0xff) { 3286 sc->ext_5ghz_lna = (val >> 3) & 1; 3287 sc->ext_2ghz_lna = (val >> 2) & 1; 3288 /* check if RF supports automatic Tx access gain control */ 3289 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3290 /* check if we have a hardware radio switch */ 3291 sc->rfswitch = val & 1; 3292 } 3293 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3294 /* read PCIe power save level */ 3295 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3296 if ((val & 0xff) != 0xff) { 3297 sc->pslevel = val & 0x3; 3298 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3299 if ((val & 0xff80) != 0x9280) 3300 sc->pslevel = MIN(sc->pslevel, 1); 3301 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3302 } 3303 } 3304 3305 /* read power settings for 2GHz channels */ 3306 for (i = 0; i < 14; i += 2) { 3307 val = rt2860_srom_read(sc, 3308 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3309 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3310 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3311 3312 val = rt2860_srom_read(sc, 3313 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3314 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3315 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3316 } 3317 /* fix broken Tx power entries */ 3318 for (i = 0; i < 14; i++) { 3319 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 3320 sc->txpow1[i] = 5; 3321 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 3322 sc->txpow2[i] = 5; 3323 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3324 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3325 } 3326 /* read power settings for 5GHz channels */ 3327 for (i = 0; i < 40; i += 2) { 3328 val = rt2860_srom_read(sc, 3329 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3330 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3331 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3332 3333 val = rt2860_srom_read(sc, 3334 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3335 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3336 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3337 } 3338 /* fix broken Tx power entries */ 3339 for (i = 0; i < 40; i++) { 3340 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3341 sc->txpow1[14 + i] = 5; 3342 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3343 sc->txpow2[14 + i] = 5; 3344 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3345 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3346 sc->txpow2[14 + i])); 3347 } 3348 3349 /* read Tx power compensation for each Tx rate */ 3350 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3351 delta_2ghz = delta_5ghz = 0; 3352 if ((val & 0xff) != 0xff && (val & 0x80)) { 3353 delta_2ghz = val & 0xf; 3354 if (!(val & 0x40)) /* negative number */ 3355 delta_2ghz = -delta_2ghz; 3356 } 3357 val >>= 8; 3358 if ((val & 0xff) != 0xff && (val & 0x80)) { 3359 delta_5ghz = val & 0xf; 3360 if (!(val & 0x40)) /* negative number */ 3361 delta_5ghz = -delta_5ghz; 3362 } 3363 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3364 delta_2ghz, delta_5ghz)); 3365 3366 for (ridx = 0; ridx < 5; ridx++) { 3367 uint32_t reg; 3368 3369 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3370 reg = val; 3371 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3372 reg |= (uint32_t)val << 16; 3373 3374 sc->txpow20mhz[ridx] = reg; 3375 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3376 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3377 3378 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3379 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3380 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3381 } 3382 3383 /* read factory-calibrated samples for temperature compensation */ 3384 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3385 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3386 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3387 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3388 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3389 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3390 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3391 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3392 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3393 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3394 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3395 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3396 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3397 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3398 sc->step_2ghz = val >> 8; 3399 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3400 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3401 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3402 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3403 sc->tssi_2ghz[8], sc->step_2ghz)); 3404 /* check that ref value is correct, otherwise disable calibration */ 3405 if (sc->tssi_2ghz[4] == 0xff) 3406 sc->calib_2ghz = 0; 3407 3408 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3409 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3410 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3411 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3412 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3413 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3414 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3415 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3416 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3417 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3418 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3419 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3420 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3421 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3422 sc->step_5ghz = val >> 8; 3423 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3424 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3425 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3426 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3427 sc->tssi_5ghz[8], sc->step_5ghz)); 3428 /* check that ref value is correct, otherwise disable calibration */ 3429 if (sc->tssi_5ghz[4] == 0xff) 3430 sc->calib_5ghz = 0; 3431 3432 /* read RSSI offsets and LNA gains from EEPROM */ 3433 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3434 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3435 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3436 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3437 if (sc->mac_ver >= 0x3071) { 3438 /* 3439 * On RT3090 chips (limited to 2 Rx chains), this ROM 3440 * field contains the Tx mixer gain for the 2GHz band. 3441 */ 3442 if ((val & 0xff) != 0xff) 3443 sc->txmixgain_2ghz = val & 0x7; 3444 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3445 } else 3446 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3447 sc->lna[2] = val >> 8; /* channel group 2 */ 3448 3449 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3450 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3451 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3452 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3453 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3454 sc->lna[3] = val >> 8; /* channel group 3 */ 3455 3456 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3457 if (sc->mac_ver >= 0x3071) 3458 sc->lna[0] = RT3090_DEF_LNA; 3459 else /* channel group 0 */ 3460 sc->lna[0] = val & 0xff; 3461 sc->lna[1] = val >> 8; /* channel group 1 */ 3462 3463 /* fix broken 5GHz LNA entries */ 3464 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3465 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3466 sc->lna[2] = sc->lna[1]; 3467 } 3468 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3469 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3470 sc->lna[3] = sc->lna[1]; 3471 } 3472 3473 /* fix broken RSSI offset entries */ 3474 for (ant = 0; ant < 3; ant++) { 3475 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3476 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3477 ant + 1, sc->rssi_2ghz[ant])); 3478 sc->rssi_2ghz[ant] = 0; 3479 } 3480 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3481 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3482 ant + 1, sc->rssi_5ghz[ant])); 3483 sc->rssi_5ghz[ant] = 0; 3484 } 3485 } 3486 3487 return 0; 3488} 3489 3490int 3491rt2860_bbp_init(struct rt2860_softc *sc) 3492{ 3493#define N(a) (sizeof (a) / sizeof ((a)[0])) 3494 int i, ntries; 3495 3496 /* wait for BBP to wake up */ 3497 for (ntries = 0; ntries < 20; ntries++) { 3498 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3499 if (bbp0 != 0 && bbp0 != 0xff) 3500 break; 3501 } 3502 if (ntries == 20) { 3503 device_printf(sc->sc_dev, 3504 "timeout waiting for BBP to wake up\n"); 3505 return ETIMEDOUT; 3506 } 3507 3508 /* initialize BBP registers to default values */ 3509 for (i = 0; i < N(rt2860_def_bbp); i++) { 3510 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3511 rt2860_def_bbp[i].val); 3512 } 3513 3514 /* fix BBP84 for RT2860E */ 3515 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3516 rt2860_mcu_bbp_write(sc, 84, 0x19); 3517 3518 if (sc->mac_ver >= 0x3071) { 3519 rt2860_mcu_bbp_write(sc, 79, 0x13); 3520 rt2860_mcu_bbp_write(sc, 80, 0x05); 3521 rt2860_mcu_bbp_write(sc, 81, 0x33); 3522 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3523 rt2860_mcu_bbp_write(sc, 69, 0x16); 3524 rt2860_mcu_bbp_write(sc, 73, 0x12); 3525 } 3526 3527 return 0; 3528#undef N 3529} 3530 3531static int 3532rt2860_txrx_enable(struct rt2860_softc *sc) 3533{ 3534 struct ifnet *ifp = sc->sc_ifp; 3535 struct ieee80211com *ic = ifp->if_l2com; 3536 uint32_t tmp; 3537 int ntries; 3538 3539 /* enable Tx/Rx DMA engine */ 3540 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3541 RAL_BARRIER_READ_WRITE(sc); 3542 for (ntries = 0; ntries < 200; ntries++) { 3543 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3544 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3545 break; 3546 DELAY(1000); 3547 } 3548 if (ntries == 200) { 3549 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3550 return ETIMEDOUT; 3551 } 3552 3553 DELAY(50); 3554 3555 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3556 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3557 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3558 3559 /* set Rx filter */ 3560 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3561 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3562 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3563 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3564 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3565 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3566 if (ic->ic_opmode == IEEE80211_M_STA) 3567 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3568 } 3569 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3570 3571 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3572 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3573 3574 return 0; 3575} 3576 3577static void 3578rt2860_init(void *arg) 3579{ 3580 struct rt2860_softc *sc = arg; 3581 struct ifnet *ifp = sc->sc_ifp; 3582 struct ieee80211com *ic = ifp->if_l2com; 3583 3584 RAL_LOCK(sc); 3585 rt2860_init_locked(sc); 3586 RAL_UNLOCK(sc); 3587 3588 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3589 ieee80211_start_all(ic); 3590} 3591 3592static void 3593rt2860_init_locked(struct rt2860_softc *sc) 3594{ 3595#define N(a) (sizeof (a) / sizeof ((a)[0])) 3596 struct ifnet *ifp = sc->sc_ifp; 3597 struct ieee80211com *ic = ifp->if_l2com; 3598 uint32_t tmp; 3599 uint8_t bbp1, bbp3; 3600 int i, qid, ridx, ntries, error; 3601 3602 RAL_LOCK_ASSERT(sc); 3603 3604 if (sc->rfswitch) { 3605 /* hardware has a radio switch on GPIO pin 2 */ 3606 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3607 device_printf(sc->sc_dev, 3608 "radio is disabled by hardware switch\n"); 3609#ifdef notyet 3610 rt2860_stop_locked(sc); 3611 return; 3612#endif 3613 } 3614 } 3615 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3616 3617 /* disable DMA */ 3618 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3619 tmp &= 0xff0; 3620 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3621 3622 /* PBF hardware reset */ 3623 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3624 RAL_BARRIER_WRITE(sc); 3625 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3626 3627 if ((error = rt2860_load_microcode(sc)) != 0) { 3628 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3629 rt2860_stop_locked(sc); 3630 return; 3631 } 3632 3633 rt2860_set_macaddr(sc, IF_LLADDR(ifp)); 3634 3635 /* init Tx power for all Tx rates (from EEPROM) */ 3636 for (ridx = 0; ridx < 5; ridx++) { 3637 if (sc->txpow20mhz[ridx] == 0xffffffff) 3638 continue; 3639 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3640 } 3641 3642 for (ntries = 0; ntries < 100; ntries++) { 3643 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3644 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3645 break; 3646 DELAY(1000); 3647 } 3648 if (ntries == 100) { 3649 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3650 rt2860_stop_locked(sc); 3651 return; 3652 } 3653 tmp &= 0xff0; 3654 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3655 3656 /* reset Rx ring and all 6 Tx rings */ 3657 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3658 3659 /* PBF hardware reset */ 3660 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3661 RAL_BARRIER_WRITE(sc); 3662 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3663 3664 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3665 3666 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3667 RAL_BARRIER_WRITE(sc); 3668 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3669 3670 for (i = 0; i < N(rt2860_def_mac); i++) 3671 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3672 if (sc->mac_ver >= 0x3071) { 3673 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3674 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3675 4 << RT2860_DLY_PAPE_EN_SHIFT); 3676 } 3677 3678 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3679 sc->sc_flags |= RT2860_PCIE; 3680 /* PCIe has different clock cycle count than PCI */ 3681 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3682 tmp = (tmp & ~0xff) | 0x7d; 3683 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3684 } 3685 3686 /* wait while MAC is busy */ 3687 for (ntries = 0; ntries < 100; ntries++) { 3688 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3689 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3690 break; 3691 DELAY(1000); 3692 } 3693 if (ntries == 100) { 3694 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3695 rt2860_stop_locked(sc); 3696 return; 3697 } 3698 3699 /* clear Host to MCU mailbox */ 3700 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3701 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3702 3703 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3704 DELAY(1000); 3705 3706 if ((error = rt2860_bbp_init(sc)) != 0) { 3707 rt2860_stop_locked(sc); 3708 return; 3709 } 3710 3711 /* clear RX WCID search table */ 3712 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3713 /* clear pairwise key table */ 3714 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3715 /* clear IV/EIV table */ 3716 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3717 /* clear WCID attribute table */ 3718 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3719 /* clear shared key table */ 3720 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3721 /* clear shared key mode */ 3722 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3723 3724 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3725 for (qid = 0; qid < 6; qid++) { 3726 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3727 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3728 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3729 } 3730 3731 /* init Rx ring */ 3732 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3733 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3734 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3735 3736 /* setup maximum buffer sizes */ 3737 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3738 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3739 3740 for (ntries = 0; ntries < 100; ntries++) { 3741 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3742 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3743 break; 3744 DELAY(1000); 3745 } 3746 if (ntries == 100) { 3747 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3748 rt2860_stop_locked(sc); 3749 return; 3750 } 3751 tmp &= 0xff0; 3752 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3753 3754 /* disable interrupts mitigation */ 3755 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3756 3757 /* write vendor-specific BBP values (from EEPROM) */ 3758 for (i = 0; i < 8; i++) { 3759 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3760 continue; 3761 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3762 } 3763 3764 /* select Main antenna for 1T1R devices */ 3765 if (sc->rf_rev == RT3070_RF_2020 || 3766 sc->rf_rev == RT3070_RF_3020 || 3767 sc->rf_rev == RT3070_RF_3320) 3768 rt3090_set_rx_antenna(sc, 0); 3769 3770 /* send LEDs operating mode to microcontroller */ 3771 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3772 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3773 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3774 3775 if (sc->mac_ver >= 0x3071) 3776 rt3090_rf_init(sc); 3777 3778 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3779 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3780 3781 if (sc->mac_ver >= 0x3071) 3782 rt3090_rf_wakeup(sc); 3783 3784 /* disable non-existing Rx chains */ 3785 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3786 bbp3 &= ~(1 << 3 | 1 << 4); 3787 if (sc->nrxchains == 2) 3788 bbp3 |= 1 << 3; 3789 else if (sc->nrxchains == 3) 3790 bbp3 |= 1 << 4; 3791 rt2860_mcu_bbp_write(sc, 3, bbp3); 3792 3793 /* disable non-existing Tx chains */ 3794 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3795 if (sc->ntxchains == 1) 3796 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3797 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3798 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3799 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3800 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3801 rt2860_mcu_bbp_write(sc, 1, bbp1); 3802 3803 if (sc->mac_ver >= 0x3071) 3804 rt3090_rf_setup(sc); 3805 3806 /* select default channel */ 3807 rt2860_switch_chan(sc, ic->ic_curchan); 3808 3809 /* reset RF from MCU */ 3810 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3811 3812 /* set RTS threshold */ 3813 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 3814 tmp &= ~0xffff00; 3815 tmp |= IEEE80211_RTS_DEFAULT << 8; 3816 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 3817 3818 /* setup initial protection mode */ 3819 rt2860_updateprot(ifp); 3820 3821 /* turn radio LED on */ 3822 rt2860_set_leds(sc, RT2860_LED_RADIO); 3823 3824 /* enable Tx/Rx DMA engine */ 3825 if ((error = rt2860_txrx_enable(sc)) != 0) { 3826 rt2860_stop_locked(sc); 3827 return; 3828 } 3829 3830 /* clear pending interrupts */ 3831 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 3832 /* enable interrupts */ 3833 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 3834 3835 if (sc->sc_flags & RT2860_ADVANCED_PS) 3836 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 3837 3838 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3839 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3840 3841 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 3842#undef N 3843} 3844 3845static void 3846rt2860_stop(void *arg) 3847{ 3848 struct rt2860_softc *sc = arg; 3849 3850 RAL_LOCK(sc); 3851 rt2860_stop_locked(sc); 3852 RAL_UNLOCK(sc); 3853} 3854 3855static void 3856rt2860_stop_locked(struct rt2860_softc *sc) 3857{ 3858 struct ifnet *ifp = sc->sc_ifp; 3859 uint32_t tmp; 3860 int qid; 3861 3862 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3863 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 3864 3865 callout_stop(&sc->watchdog_ch); 3866 sc->sc_tx_timer = 0; 3867 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3868 3869 /* disable interrupts */ 3870 RAL_WRITE(sc, RT2860_INT_MASK, 0); 3871 3872 /* disable GP timer */ 3873 rt2860_set_gp_timer(sc, 0); 3874 3875 /* disable Rx */ 3876 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 3877 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3878 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 3879 3880 /* reset adapter */ 3881 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3882 RAL_BARRIER_WRITE(sc); 3883 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3884 3885 /* reset Tx and Rx rings (and reclaim TXWIs) */ 3886 sc->qfullmsk = 0; 3887 for (qid = 0; qid < 6; qid++) 3888 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 3889 rt2860_reset_rx_ring(sc, &sc->rxq); 3890} 3891 3892int 3893rt2860_load_microcode(struct rt2860_softc *sc) 3894{ 3895 const struct firmware *fp; 3896 int ntries, error; 3897 3898 RAL_LOCK_ASSERT(sc); 3899 3900 RAL_UNLOCK(sc); 3901 fp = firmware_get("rt2860fw"); 3902 RAL_LOCK(sc); 3903 if (fp == NULL) { 3904 device_printf(sc->sc_dev, 3905 "unable to receive rt2860fw firmware image\n"); 3906 return EINVAL; 3907 } 3908 3909 /* set "host program ram write selection" bit */ 3910 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 3911 /* write microcode image */ 3912 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 3913 /* kick microcontroller unit */ 3914 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 3915 RAL_BARRIER_WRITE(sc); 3916 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 3917 3918 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3919 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3920 3921 /* wait until microcontroller is ready */ 3922 RAL_BARRIER_READ_WRITE(sc); 3923 for (ntries = 0; ntries < 1000; ntries++) { 3924 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 3925 break; 3926 DELAY(1000); 3927 } 3928 if (ntries == 1000) { 3929 device_printf(sc->sc_dev, 3930 "timeout waiting for MCU to initialize\n"); 3931 error = ETIMEDOUT; 3932 } else 3933 error = 0; 3934 3935 firmware_put(fp, FIRMWARE_UNLOAD); 3936 return error; 3937} 3938 3939/* 3940 * This function is called periodically to adjust Tx power based on 3941 * temperature variation. 3942 */ 3943#ifdef NOT_YET 3944static void 3945rt2860_calib(struct rt2860_softc *sc) 3946{ 3947 struct ieee80211com *ic = &sc->sc_ic; 3948 const uint8_t *tssi; 3949 uint8_t step, bbp49; 3950 int8_t ridx, d; 3951 3952 /* read current temperature */ 3953 bbp49 = rt2860_mcu_bbp_read(sc, 49); 3954 3955 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 3956 tssi = &sc->tssi_2ghz[4]; 3957 step = sc->step_2ghz; 3958 } else { 3959 tssi = &sc->tssi_5ghz[4]; 3960 step = sc->step_5ghz; 3961 } 3962 3963 if (bbp49 < tssi[0]) { /* lower than reference */ 3964 /* use higher Tx power than default */ 3965 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 3966 } else if (bbp49 > tssi[0]) { /* greater than reference */ 3967 /* use lower Tx power than default */ 3968 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 3969 } else { 3970 /* use default Tx power */ 3971 d = 0; 3972 } 3973 d *= step; 3974 3975 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 3976 3977 /* write adjusted Tx power values for each Tx rate */ 3978 for (ridx = 0; ridx < 5; ridx++) { 3979 if (sc->txpow20mhz[ridx] == 0xffffffff) 3980 continue; 3981 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 3982 b4inc(sc->txpow20mhz[ridx], d)); 3983 } 3984} 3985#endif 3986 3987static void 3988rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 3989{ 3990 uint32_t tmp; 3991 3992 if (aux) { 3993 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3994 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 3995 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 3996 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 3997 } else { 3998 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3999 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4000 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4001 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4002 } 4003} 4004 4005static void 4006rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4007{ 4008 struct ifnet *ifp = sc->sc_ifp; 4009 struct ieee80211com *ic = ifp->if_l2com; 4010 u_int chan, group; 4011 4012 chan = ieee80211_chan2ieee(ic, c); 4013 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4014 return; 4015 4016 if (sc->mac_ver >= 0x3071) 4017 rt3090_set_chan(sc, chan); 4018 else 4019 rt2860_set_chan(sc, chan); 4020 4021 /* determine channel group */ 4022 if (chan <= 14) 4023 group = 0; 4024 else if (chan <= 64) 4025 group = 1; 4026 else if (chan <= 128) 4027 group = 2; 4028 else 4029 group = 3; 4030 4031 /* XXX necessary only when group has changed! */ 4032 rt2860_select_chan_group(sc, group); 4033 4034 DELAY(1000); 4035} 4036 4037static int 4038rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4039{ 4040 struct ieee80211com *ic = vap->iv_ic; 4041 struct ieee80211_beacon_offsets bo; 4042 struct rt2860_txwi txwi; 4043 struct mbuf *m; 4044 int ridx; 4045 4046 if ((m = ieee80211_beacon_alloc(vap->iv_bss, &bo)) == NULL) 4047 return ENOBUFS; 4048 4049 memset(&txwi, 0, sizeof txwi); 4050 txwi.wcid = 0xff; 4051 txwi.len = htole16(m->m_pkthdr.len); 4052 /* send beacons at the lowest available rate */ 4053 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4054 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4055 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4056 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4057 txwi.phy |= htole16(RT2860_PHY_OFDM); 4058 txwi.txop = RT2860_TX_TXOP_HT; 4059 txwi.flags = RT2860_TX_TS; 4060 txwi.xflags = RT2860_TX_NSEQ; 4061 4062 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4063 (uint8_t *)&txwi, sizeof txwi); 4064 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4065 mtod(m, uint8_t *), m->m_pkthdr.len); 4066 4067 m_freem(m); 4068 4069 return 0; 4070} 4071 4072static void 4073rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4074{ 4075 struct ifnet *ifp = sc->sc_ifp; 4076 struct ieee80211com *ic = ifp->if_l2com; 4077 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4078 uint32_t tmp; 4079 4080 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4081 4082 tmp &= ~0x1fffff; 4083 tmp |= vap->iv_bss->ni_intval * 16; 4084 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4085 if (vap->iv_opmode == IEEE80211_M_STA) { 4086 /* 4087 * Local TSF is always updated with remote TSF on beacon 4088 * reception. 4089 */ 4090 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4091 } 4092 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4093 vap->iv_opmode == IEEE80211_M_MBSS) { 4094 tmp |= RT2860_BCN_TX_EN; 4095 /* 4096 * Local TSF is updated with remote TSF on beacon reception 4097 * only if the remote TSF is greater than local TSF. 4098 */ 4099 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4100 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4101 tmp |= RT2860_BCN_TX_EN; 4102 /* SYNC with nobody */ 4103 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4104 } 4105 4106 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4107} 4108