1/* 2 Driver for Intel(R) PRO/Wireless 2100 devices. 3 Copyright (C) 2006 Michael Lotz <mmlr@mlotz.ch> 4 Released under the terms of the MIT license. 5*/ 6 7#ifndef _IPW2100_HW_H_ 8#define _IPW2100_HW_H_ 9 10// buffer descriptor 11struct ipw_bd { 12 uint32 physical_address; 13 uint32 length; 14 uint8 flags; 15 uint8 fragment_count; 16 uint8 reserved[6]; 17} _PACKED; 18 19#define IPW_BD_FLAG_TYPE_802_3 0x00 20#define IPW_BD_FLAG_NOT_LAST_FRAGMENT 0x01 21#define IPW_BD_FLAG_COMMAND 0x02 22#define IPW_BD_FLAG_TYPE_802_11 0x04 23#define IPW_BD_FLAG_INTERRUPT 0x08 24 25// status descriptor 26struct ipw_status { 27 uint32 length; 28 uint16 code; 29 uint8 flags; 30 uint8 rssi; // received signal strength indicator 31} _PACKED; 32 33#define IPW_STATUS_CODE_COMMAND 0 34#define IPW_STATUS_CODE_STATUS 1 35#define IPW_STATUS_CODE_DATA_802_11 2 36#define IPW_STATUS_CODE_DATA_802_3 3 37#define IPW_STATUS_CODE_NOTIFICATION 4 38#define IPW_STATUS_CODE_MASK 0x0f 39 40#define IPW_STATUS_FLAG_DECRYPTED 0x01 41#define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 42 43// adapter states 44#define IPW_STATE_INITIALIZED 0x00000001 45#define IPW_STATE_COUNTRY_FOUND 0x00000002 46#define IPW_STATE_ASSOCIATED 0x00000004 47#define IPW_STATE_ASSOCIATION_LOST 0x00000008 48#define IPW_STATE_ASSOCIATION_CHANGED 0x00000010 49#define IPW_STATE_SCAN_COMPLETE 0x00000020 50#define IPW_STATE_PSP_ENTERED 0x00000040 51#define IPW_STATE_PSP_LEFT 0x00000080 52#define IPW_STATE_RF_KILL 0x00000100 53#define IPW_STATE_DISABLED 0x00000200 54#define IPW_STATE_POWER_DOWN 0x00000400 55#define IPW_STATE_SCANNING 0x00000800 56 57// data descriptor 58struct ipw_data { 59 uint32 command; 60 uint32 unused; 61 uint8 encrypted; 62 uint8 needs_encryption; 63 uint8 key_index; 64 uint8 key_size; 65 uint8 key[16]; 66 uint8 reserved[10]; 67 uint8 source_address[6]; 68 uint8 dest_address[6]; 69 uint16 fragment_size; 70} _PACKED; 71 72// data holders 73struct ipw_tx { 74 uint8 data[2500]; 75} _PACKED; 76 77struct ipw_rx { 78 uint8 data[2500]; 79} _PACKED; 80 81// command descriptor 82struct ipw_command { 83 uint32 command; 84 uint64 unused; 85 uint32 length; 86 uint8 data[400]; 87 uint32 status; 88 uint8 reserved[68]; 89} _PACKED; 90 91#define IPW_COMMAND_ENABLE 2 92#define IPW_COMMAND_SET_CONFIGURATION 6 93#define IPW_COMMAND_SET_ESSID 8 94#define IPW_COMMAND_SET_MANDATORY_BSSID 9 95#define IPW_COMMAND_SET_MAC_ADDRESS 11 96#define IPW_COMMAND_SET_MODE 12 97#define IPW_COMMAND_SET_CHANNEL 14 98#define IPW_COMMAND_SET_RTS_THRESHOLD 15 99#define IPW_COMMAND_SET_FRAG_THRESHOLD 16 100#define IPW_COMMAND_SET_POWER_MODE 17 101#define IPW_COMMAND_SET_TX_RATES 18 102#define IPW_COMMAND_SET_BASIC_TX_RATES 19 103#define IPW_COMMAND_SET_WEP_KEY 20 104#define IPW_COMMAND_SET_WEP_KEY_INDEX 25 105#define IPW_COMMAND_SET_WEP_FLAGS 26 106#define IPW_COMMAND_ADD_MULTICAST 27 107#define IPW_COMMAND_SET_BEACON_INTERVAL 29 108#define IPW_COMMAND_SEND_DATA 33 109#define IPW_COMMAND_SET_TX_POWER_INDEX 36 110#define IPW_COMMAND_BROADCAST_SCAN 43 111#define IPW_COMMAND_DISABLE 44 112#define IPW_COMMAND_SET_DESIRED_BSSID 45 113#define IPW_COMMAND_SET_SCAN_OPTIONS 46 114#define IPW_COMMAND_PREPARE_POWER_DOWN 58 115#define IPW_COMMAND_DISABLE_PHY 61 116#define IPW_COMMAND_SET_MSDU_TX_RATES 62 117#define IPW_COMMAND_SET_SECURITY_INFO 67 118#define IPW_COMMAND_SET_WPA_IE 69 119 120// values for IPW_COMMAND_SET_POWER_MODE 121#define IPW_POWER_MODE_CAM 0 122#define IPW_POWER_MODE_AUTOMATIC 6 123 124// values for IPW_COMMAND_SET_MODE 125#define IPW_MODE_BSS 1 126#define IPW_MODE_MONITOR 2 127#define IPW_MODE_IBSS 3 128 129// values for IPW_COMMAND_SET_WEP_FLAGS 130#define IPW_WEP_FLAGS_HW_DECRYPT 0x00000001 131#define IPW_WEP_FLAGS_HW_ENCRYPT 0x00000008 132 133// structure for IPW_COMMAND_SET_WEP_KEY 134struct ipw_wep_key { 135 uint8 index; 136 uint8 length; 137 uint8 key[13]; 138} _PACKED; 139 140// structure for IPW_COMMAND_SET_SECURITY_INFO 141struct ipw_security { 142 uint32 ciphers; 143 uint16 reserved1; 144 uint8 auth_mode; 145 uint16 reserved2; 146} _PACKED; 147 148#define IPW_CIPHER_NONE 0x00000001 149#define IPW_CIPHER_WEP40 0x00000002 150#define IPW_CIPHER_TKIP 0x00000004 151#define IPW_CIPHER_CCMP 0x00000010 152#define IPW_CIPHER_WEP104 0x00000020 153#define IPW_CIPHER_CKIP 0x00000040 154 155#define IPW_AUTH_MODE_OPEN 0 156#define IPW_AUTH_MODE_SHARED 1 157 158// structure for IPW_COMMAND_SET_SCAN_OPTIONS 159struct ipw_scan_options { 160 uint32 flags; 161 uint32 channels; 162} _PACKED; 163 164#define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 165#define IPW_SCAN_MIXED_CELL 0x00000002 166#define IPW_SCAN_PASSIVE 0x00000008 167 168// structure for IPW_COMMAND_SET_CONFIGURATION 169struct ipw_configuration { 170 uint32 flags; 171 uint32 bss_channel_mask; 172 uint32 ibss_channel_mask; 173} _PACKED; 174 175#define IPW_CONFIG_PROMISCUOUS 0x00000004 176#define IPW_CONFIG_PREAMBLE_AUTO 0x00000010 177#define IPW_CONFIG_IBSS_AUTO_START 0x00000020 178#define IPW_CONFIG_802_1X_ENABLE 0x00004000 179#define IPW_CONFIG_BSS_MASK 0x00008000 180#define IPW_CONFIG_IBSS_MASK 0x00010000 181 182// default values 183#define IPW_BSS_CHANNEL_MASK 0x000003fff 184#define IPW_IBSS_CHANNEL_MASK 0x0000087ff 185#define IPW_DEFAULT_BEACON_INTERVAL 100 186#define IPW_DEFAULT_TX_POWER 32 187 188// structure for IPW_COMMAND_SET_WPA_IE 189struct wpa_ie { 190 uint8 id; 191 uint8 length; 192 uint8 oui[3]; 193 uint8 oui_type; 194 uint16 version; 195 uint32 multicast_cipher; 196 uint16 unicast_cipher_count; 197 uint32 unicast_ciphers[8]; 198 uint16 auth_selector_count; 199 uint32 auth_selectors[8]; 200 uint16 capabilities; 201 uint16 pmkid_count; 202 uint16 pmkids[8]; 203} _PACKED; 204 205struct ipw_wpa_ie { 206 uint16 mask; 207 uint16 capability_info; 208 uint16 lintval; 209 uint8 bssid[6]; 210 uint32 length; 211 wpa_ie wpa; 212} _PACKED; 213 214// bitmask for IPW_COMMAND_SET_[BASIC|MSDU]_TX_RATES 215#define IPW_TX_RATE_1_MBIT 0x00000001 216#define IPW_TX_RATE_2_MBIT 0x00000002 217#define IPW_TX_RATE_5_5_MBIT 0x00000004 218#define IPW_TX_RATE_11_MBIT 0x00000008 219#define IPW_TX_RATE_ALL 0x0000000f 220 221// values for IPW_COMMAND_SET_RTS_THRESHOLD 222#define IPW_RTS_THRESHOLD_MIN 1 223#define IPW_RTS_THRESHOLD_MAX 2304 224#define IPW_RTS_THRESHOLD_DEFAULT 1000 225 226// buffers 227#define IPW_TX_BUFFER_COUNT 128 228#define IPW_TX_BUFFER_SIZE (IPW_TX_BUFFER_COUNT * sizeof(ipw_bd)) 229#define IPW_TX_PACKET_SIZE (IPW_TX_BUFFER_COUNT * sizeof(ipw_tx)) 230#define IPW_RX_BUFFER_COUNT 128 231#define IPW_RX_BUFFER_SIZE (IPW_RX_BUFFER_COUNT * sizeof(ipw_bd)) 232#define IPW_RX_PACKET_SIZE (IPW_RX_BUFFER_COUNT * sizeof(ipw_rx)) 233#define IPW_STATUS_BUFFER_COUNT IPW_RX_BUFFER_COUNT 234#define IPW_STATUS_BUFFER_SIZE (IPW_STATUS_BUFFER_COUNT * sizeof(ipw_status)) 235 236// registers 237#define IPW_REG_INTERRUPT 0x0008 238#define IPW_REG_INTERRUPT_MASK 0x000c 239#define IPW_REG_INDIRECT_ADDRESS 0x0010 240#define IPW_REG_INDIRECT_DATA 0x0014 241#define IPW_REG_RESET 0x0020 242#define IPW_REG_CONTROL 0x0024 243#define IPW_REG_IO 0x0030 244#define IPW_REG_DEBUG 0x0090 245#define IPW_REG_TX_BASE 0x0200 246#define IPW_REG_TX_SIZE 0x0204 247#define IPW_REG_TX_READ 0x0280 248#define IPW_REG_TX_WRITE 0x0f80 249#define IPW_REG_RX_BASE 0x0240 250#define IPW_REG_RX_SIZE 0x0248 251#define IPW_REG_RX_READ 0x02a0 252#define IPW_REG_RX_WRITE 0x0fa0 253#define IPW_REG_STATUS_BASE 0x0244 254 255#define IPW_INDIRECT_ADDRESS_MASK 0x00fffffc 256 257// flags for IPW_REG_INTERRUPT(_MASK) 258#define IPW_INTERRUPT_TX_TRANSFER 0x00000001 259#define IPW_INTERRUPT_RX_TRANSFER 0x00000002 260#define IPW_INTERRUPT_STATUS_CHANGE 0x00000010 261#define IPW_INTERRUPT_COMMAND_DONE 0x00010000 262#define IPW_INTERRUPT_FW_INIT_DONE 0x01000000 263#define IPW_INTERRUPT_FATAL_ERROR 0x40000000 264#define IPW_INTERRUPT_PARITY_ERROR 0x80000000 265 266// flags for IPW_REG_RESET 267#define IPW_RESET_PRINCETON_RESET 0x00000001 268#define IPW_RESET_SW_RESET 0x00000080 269#define IPW_RESET_MASTER_DISABLED 0x00000100 270#define IPW_RESET_STOP_MASTER 0x00000200 271 272// flags for IPW_REG_CONTROL 273#define IPW_CONTROL_CLOCK_READY 0x00000001 274#define IPW_CONTROL_ALLOW_STANDBY 0x00000002 275#define IPW_CONTROL_INIT_COMPLETE 0x00000004 276 277// flags for IPW_REG_IO 278#define IPW_IO_GPIO1_ENABLE 0x00000008 279#define IPW_IO_GPIO1_MASK 0x0000000c 280#define IPW_IO_GPIO3_MASK 0x000000c0 281#define IPW_IO_LED_OFF 0x00002000 282#define IPW_IO_RADIO_DISABLED 0x00010000 283 284// the value at the debug register base is always 285// the magic data value. used to verify register access. 286#define IPW_DEBUG_DATA 0xd55555d5 287 288// shared memory 289#define IPW_SHARED_MEMORY_BASE_0 0x0002f200 290#define IPW_SHARED_MEMORY_LENGTH_0 784 291#define IPW_SHARED_MEMORY_BASE_1 0x0002f610 292#define IPW_SHARED_MEMORY_LENGTH_1 32 293#define IPW_SHARED_MEMORY_BASE_2 0x0002fa00 294#define IPW_SHARED_MEMORY_LENGTH_2 32 295#define IPW_SHARED_MEMORY_BASE_3 0x0002fc00 296#define IPW_SHARED_MEMORY_LENGTH_3 16 297#define IPW_INTERRUPT_MEMORY_BASE 0x0002ff80 298#define IPW_INTERRUPT_MEMORY_LENGTH 128 299 300// ordinal tables 301#define IPW_ORDINAL_TABLE_1_ADDRESS 0x00000380 302#define IPW_ORDINAL_TABLE_2_ADDRESS 0x00000384 303#define IPW_ORDINAL_TABLE_1_START 1 304#define IPW_ORDINAL_TABLE_2_START 1000 305 306enum ipw_ordinal_table_1 { 307 IPW_ORD_FIRMWARE_DB_LOCK = 120, 308 IPW_ORD_CARD_DISABLED = 157, 309 IPW_ORD_GET_AP_BSSID = 1014, 310}; 311 312// firmware db lock 313#define IPW_FIRMWARE_LOCK_NONE 0 314#define IPW_FIRMWARE_LOCK_DRIVER 1 315#define IPW_FIRMWARE_LOCK_FIRMWARE 2 316 317// firmware binary image header 318struct ipw_firmware_header { 319 uint16 version; 320 uint16 mode; 321 uint32 main_size; 322 uint32 ucode_size; 323} _PACKED; 324 325// symbol alive response to check microcode 326struct symbol_alive_response { 327 uint8 command_id; 328 uint8 sequence_number; 329 uint8 microcode_revision; 330 uint8 eeprom_valid; 331 uint16 valid_flags; 332 uint8 ieee_address[6]; 333 uint16 flags; 334 uint16 pcb_revision; 335 uint16 clock_settle_time; 336 uint16 powerup_settle_time; 337 uint16 hop_settle_time; 338 uint8 date[3]; 339 uint8 time[2]; 340 uint8 microcode_valid; 341} _PACKED; 342 343#endif // _IPW2100_HW_H_ 344