1/*- 2 * Copyright (c) 2007-2009 3 * Damien Bergamini <damien.bergamini@free.fr> 4 * Copyright (c) 2008 5 * Benjamin Close <benjsc@FreeBSD.org> 6 * Copyright (c) 2008 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21/* 22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 23 * adapters. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD$"); 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/mbuf.h> 33#include <sys/kernel.h> 34#include <sys/socket.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/bus.h> 38#include <sys/rman.h> 39#include <sys/endian.h> 40#include <sys/firmware.h> 41#include <sys/limits.h> 42#include <sys/module.h> 43#include <sys/queue.h> 44#include <sys/taskqueue.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <machine/clock.h> 49 50#include <dev/pci/pcireg.h> 51#include <dev/pci/pcivar.h> 52 53#include <net/bpf.h> 54#include <net/if.h> 55#include <net/if_arp.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59#include <net/if_types.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/if_ether.h> 65#include <netinet/ip.h> 66 67#include <net80211/ieee80211_var.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_regdomain.h> 70#include <net80211/ieee80211_ratectl.h> 71 72#include <dev/iwn/if_iwnreg.h> 73#include <dev/iwn/if_iwnvar.h> 74 75struct iwn_ident { 76 uint16_t vendor; 77 uint16_t device; 78 const char *name; 79}; 80 81static const struct iwn_ident iwn_ident_table[] = { 82 { 0x8086, 0x0082, "Intel Centrino Advanced-N 6205" }, 83 { 0x8086, 0x0083, "Intel Centrino Wireless-N 1000" }, 84 { 0x8086, 0x0084, "Intel Centrino Wireless-N 1000" }, 85 { 0x8086, 0x0085, "Intel Centrino Advanced-N 6205" }, 86 { 0x8086, 0x0087, "Intel Centrino Advanced-N + WiMAX 6250" }, 87 { 0x8086, 0x0089, "Intel Centrino Advanced-N + WiMAX 6250" }, 88 { 0x8086, 0x008a, "Intel Centrino Wireless-N 1030" }, 89 { 0x8086, 0x008b, "Intel Centrino Wireless-N 1030" }, 90 { 0x8086, 0x0090, "Intel Centrino Advanced-N 6230" }, 91 { 0x8086, 0x0091, "Intel Centrino Advanced-N 6230" }, 92 { 0x8086, 0x0885, "Intel Centrino Wireless-N + WiMAX 6150" }, 93 { 0x8086, 0x0886, "Intel Centrino Wireless-N + WiMAX 6150" }, 94 { 0x8086, 0x0896, "Intel Centrino Wireless-N 130" }, 95 { 0x8086, 0x0887, "Intel Centrino Wireless-N 130" }, 96 { 0x8086, 0x08ae, "Intel Centrino Wireless-N 100" }, 97 { 0x8086, 0x08af, "Intel Centrino Wireless-N 100" }, 98 { 0x8086, 0x4229, "Intel Wireless WiFi Link 4965" }, 99 { 0x8086, 0x422b, "Intel Centrino Ultimate-N 6300" }, 100 { 0x8086, 0x422c, "Intel Centrino Advanced-N 6200" }, 101 { 0x8086, 0x422d, "Intel Wireless WiFi Link 4965" }, 102 { 0x8086, 0x4230, "Intel Wireless WiFi Link 4965" }, 103 { 0x8086, 0x4232, "Intel WiFi Link 5100" }, 104 { 0x8086, 0x4233, "Intel Wireless WiFi Link 4965" }, 105 { 0x8086, 0x4235, "Intel Ultimate N WiFi Link 5300" }, 106 { 0x8086, 0x4236, "Intel Ultimate N WiFi Link 5300" }, 107 { 0x8086, 0x4237, "Intel WiFi Link 5100" }, 108 { 0x8086, 0x4238, "Intel Centrino Ultimate-N 6300" }, 109 { 0x8086, 0x4239, "Intel Centrino Advanced-N 6200" }, 110 { 0x8086, 0x423a, "Intel WiMAX/WiFi Link 5350" }, 111 { 0x8086, 0x423b, "Intel WiMAX/WiFi Link 5350" }, 112 { 0x8086, 0x423c, "Intel WiMAX/WiFi Link 5150" }, 113 { 0x8086, 0x423d, "Intel WiMAX/WiFi Link 5150" }, 114 { 0, 0, NULL } 115}; 116 117static int iwn_probe(device_t); 118static int iwn_attach(device_t); 119static int iwn4965_attach(struct iwn_softc *, uint16_t); 120static int iwn5000_attach(struct iwn_softc *, uint16_t); 121static void iwn_radiotap_attach(struct iwn_softc *); 122static void iwn_sysctlattach(struct iwn_softc *); 123static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 124 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 125 const uint8_t [IEEE80211_ADDR_LEN], 126 const uint8_t [IEEE80211_ADDR_LEN]); 127static void iwn_vap_delete(struct ieee80211vap *); 128static int iwn_detach(device_t); 129static int iwn_shutdown(device_t); 130static int iwn_suspend(device_t); 131static int iwn_resume(device_t); 132static int iwn_nic_lock(struct iwn_softc *); 133static int iwn_eeprom_lock(struct iwn_softc *); 134static int iwn_init_otprom(struct iwn_softc *); 135static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 136static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 137static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 138 void **, bus_size_t, bus_size_t); 139static void iwn_dma_contig_free(struct iwn_dma_info *); 140static int iwn_alloc_sched(struct iwn_softc *); 141static void iwn_free_sched(struct iwn_softc *); 142static int iwn_alloc_kw(struct iwn_softc *); 143static void iwn_free_kw(struct iwn_softc *); 144static int iwn_alloc_ict(struct iwn_softc *); 145static void iwn_free_ict(struct iwn_softc *); 146static int iwn_alloc_fwmem(struct iwn_softc *); 147static void iwn_free_fwmem(struct iwn_softc *); 148static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 149static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 150static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 151static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 152 int); 153static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 154static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 155static void iwn5000_ict_reset(struct iwn_softc *); 156static int iwn_read_eeprom(struct iwn_softc *, 157 uint8_t macaddr[IEEE80211_ADDR_LEN]); 158static void iwn4965_read_eeprom(struct iwn_softc *); 159static void iwn4965_print_power_group(struct iwn_softc *, int); 160static void iwn5000_read_eeprom(struct iwn_softc *); 161static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 162static void iwn_read_eeprom_band(struct iwn_softc *, int); 163static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 164static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 165static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 166 struct ieee80211_channel *); 167static int iwn_setregdomain(struct ieee80211com *, 168 struct ieee80211_regdomain *, int, 169 struct ieee80211_channel[]); 170static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 171static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 172 const uint8_t mac[IEEE80211_ADDR_LEN]); 173static void iwn_newassoc(struct ieee80211_node *, int); 174static int iwn_media_change(struct ifnet *); 175static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 176static void iwn_calib_timeout(void *); 177static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 178 struct iwn_rx_data *); 179static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 180 struct iwn_rx_data *); 181static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 182 struct iwn_rx_data *); 183static void iwn5000_rx_calib_results(struct iwn_softc *, 184 struct iwn_rx_desc *, struct iwn_rx_data *); 185static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 186 struct iwn_rx_data *); 187static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 188 struct iwn_rx_data *); 189static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 190 struct iwn_rx_data *); 191static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 192 uint8_t); 193static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *); 194static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 195static void iwn_notif_intr(struct iwn_softc *); 196static void iwn_wakeup_intr(struct iwn_softc *); 197static void iwn_rftoggle_intr(struct iwn_softc *); 198static void iwn_fatal_intr(struct iwn_softc *); 199static void iwn_intr(void *); 200static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 201 uint16_t); 202static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 203 uint16_t); 204#ifdef notyet 205static void iwn5000_reset_sched(struct iwn_softc *, int, int); 206#endif 207static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 208 struct ieee80211_node *); 209static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 210 struct ieee80211_node *, 211 const struct ieee80211_bpf_params *params); 212static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 213 const struct ieee80211_bpf_params *); 214static void iwn_start(struct ifnet *); 215static void iwn_start_locked(struct ifnet *); 216static void iwn_watchdog(void *); 217static int iwn_ioctl(struct ifnet *, u_long, caddr_t); 218static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 219static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 220 int); 221static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 222 int); 223static int iwn_set_link_quality(struct iwn_softc *, 224 struct ieee80211_node *); 225static int iwn_add_broadcast_node(struct iwn_softc *, int); 226static int iwn_updateedca(struct ieee80211com *); 227static void iwn_update_mcast(struct ifnet *); 228static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 229static int iwn_set_critical_temp(struct iwn_softc *); 230static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 231static void iwn4965_power_calibration(struct iwn_softc *, int); 232static int iwn4965_set_txpower(struct iwn_softc *, 233 struct ieee80211_channel *, int); 234static int iwn5000_set_txpower(struct iwn_softc *, 235 struct ieee80211_channel *, int); 236static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 237static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 238static int iwn_get_noise(const struct iwn_rx_general_stats *); 239static int iwn4965_get_temperature(struct iwn_softc *); 240static int iwn5000_get_temperature(struct iwn_softc *); 241static int iwn_init_sensitivity(struct iwn_softc *); 242static void iwn_collect_noise(struct iwn_softc *, 243 const struct iwn_rx_general_stats *); 244static int iwn4965_init_gains(struct iwn_softc *); 245static int iwn5000_init_gains(struct iwn_softc *); 246static int iwn4965_set_gains(struct iwn_softc *); 247static int iwn5000_set_gains(struct iwn_softc *); 248static void iwn_tune_sensitivity(struct iwn_softc *, 249 const struct iwn_rx_stats *); 250static int iwn_send_sensitivity(struct iwn_softc *); 251static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 252static int iwn_send_btcoex(struct iwn_softc *); 253static int iwn_send_advanced_btcoex(struct iwn_softc *); 254static int iwn5000_runtime_calib(struct iwn_softc *); 255static int iwn_config(struct iwn_softc *); 256static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int); 257static int iwn_scan(struct iwn_softc *); 258static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 259static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 260static int iwn_ampdu_rx_start(struct ieee80211_node *, 261 struct ieee80211_rx_ampdu *, int, int, int); 262static void iwn_ampdu_rx_stop(struct ieee80211_node *, 263 struct ieee80211_rx_ampdu *); 264static int iwn_addba_request(struct ieee80211_node *, 265 struct ieee80211_tx_ampdu *, int, int, int); 266static int iwn_addba_response(struct ieee80211_node *, 267 struct ieee80211_tx_ampdu *, int, int, int); 268static int iwn_ampdu_tx_start(struct ieee80211com *, 269 struct ieee80211_node *, uint8_t); 270static void iwn_ampdu_tx_stop(struct ieee80211_node *, 271 struct ieee80211_tx_ampdu *); 272static void iwn4965_ampdu_tx_start(struct iwn_softc *, 273 struct ieee80211_node *, int, uint8_t, uint16_t); 274static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 275 uint8_t, uint16_t); 276static void iwn5000_ampdu_tx_start(struct iwn_softc *, 277 struct ieee80211_node *, int, uint8_t, uint16_t); 278static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 279 uint8_t, uint16_t); 280static int iwn5000_query_calibration(struct iwn_softc *); 281static int iwn5000_send_calibration(struct iwn_softc *); 282static int iwn5000_send_wimax_coex(struct iwn_softc *); 283static int iwn5000_crystal_calib(struct iwn_softc *); 284static int iwn5000_temp_offset_calib(struct iwn_softc *); 285static int iwn4965_post_alive(struct iwn_softc *); 286static int iwn5000_post_alive(struct iwn_softc *); 287static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 288 int); 289static int iwn4965_load_firmware(struct iwn_softc *); 290static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 291 const uint8_t *, int); 292static int iwn5000_load_firmware(struct iwn_softc *); 293static int iwn_read_firmware_leg(struct iwn_softc *, 294 struct iwn_fw_info *); 295static int iwn_read_firmware_tlv(struct iwn_softc *, 296 struct iwn_fw_info *, uint16_t); 297static int iwn_read_firmware(struct iwn_softc *); 298static int iwn_clock_wait(struct iwn_softc *); 299static int iwn_apm_init(struct iwn_softc *); 300static void iwn_apm_stop_master(struct iwn_softc *); 301static void iwn_apm_stop(struct iwn_softc *); 302static int iwn4965_nic_config(struct iwn_softc *); 303static int iwn5000_nic_config(struct iwn_softc *); 304static int iwn_hw_prepare(struct iwn_softc *); 305static int iwn_hw_init(struct iwn_softc *); 306static void iwn_hw_stop(struct iwn_softc *); 307static void iwn_radio_on(void *, int); 308static void iwn_radio_off(void *, int); 309static void iwn_init_locked(struct iwn_softc *); 310static void iwn_init(void *); 311static void iwn_stop_locked(struct iwn_softc *); 312static void iwn_stop(struct iwn_softc *); 313static void iwn_scan_start(struct ieee80211com *); 314static void iwn_scan_end(struct ieee80211com *); 315static void iwn_set_channel(struct ieee80211com *); 316static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 317static void iwn_scan_mindwell(struct ieee80211_scan_state *); 318static void iwn_hw_reset(void *, int); 319 320#define IWN_DEBUG 321#ifdef IWN_DEBUG 322enum { 323 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 324 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 325 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 326 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */ 327 IWN_DEBUG_RESET = 0x00000010, /* reset processing */ 328 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */ 329 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 330 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */ 331 IWN_DEBUG_INTR = 0x00000100, /* ISR */ 332 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */ 333 IWN_DEBUG_NODE = 0x00000400, /* node management */ 334 IWN_DEBUG_LED = 0x00000800, /* led management */ 335 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */ 336 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */ 337 IWN_DEBUG_ANY = 0xffffffff 338}; 339 340#define DPRINTF(sc, m, fmt, ...) do { \ 341 if (sc->sc_debug & (m)) \ 342 printf(fmt, __VA_ARGS__); \ 343} while (0) 344 345static const char * 346iwn_intr_str(uint8_t cmd) 347{ 348 switch (cmd) { 349 /* Notifications */ 350 case IWN_UC_READY: return "UC_READY"; 351 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE"; 352 case IWN_TX_DONE: return "TX_DONE"; 353 case IWN_START_SCAN: return "START_SCAN"; 354 case IWN_STOP_SCAN: return "STOP_SCAN"; 355 case IWN_RX_STATISTICS: return "RX_STATS"; 356 case IWN_BEACON_STATISTICS: return "BEACON_STATS"; 357 case IWN_STATE_CHANGED: return "STATE_CHANGED"; 358 case IWN_BEACON_MISSED: return "BEACON_MISSED"; 359 case IWN_RX_PHY: return "RX_PHY"; 360 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE"; 361 case IWN_RX_DONE: return "RX_DONE"; 362 363 /* Command Notifications */ 364 case IWN_CMD_RXON: return "IWN_CMD_RXON"; 365 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC"; 366 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS"; 367 case IWN_CMD_TIMING: return "IWN_CMD_TIMING"; 368 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY"; 369 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED"; 370 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX"; 371 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG"; 372 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT"; 373 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE"; 374 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE"; 375 case IWN_CMD_SCAN: return "IWN_CMD_SCAN"; 376 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS"; 377 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER"; 378 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM"; 379 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG"; 380 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX"; 381 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP"; 382 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY"; 383 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB"; 384 } 385 return "UNKNOWN INTR NOTIF/CMD"; 386} 387#else 388#define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0) 389#endif 390 391static device_method_t iwn_methods[] = { 392 /* Device interface */ 393 DEVMETHOD(device_probe, iwn_probe), 394 DEVMETHOD(device_attach, iwn_attach), 395 DEVMETHOD(device_detach, iwn_detach), 396 DEVMETHOD(device_shutdown, iwn_shutdown), 397 DEVMETHOD(device_suspend, iwn_suspend), 398 DEVMETHOD(device_resume, iwn_resume), 399 { 0, 0 } 400}; 401 402static driver_t iwn_driver = { 403 "iwn", 404 iwn_methods, 405 sizeof(struct iwn_softc) 406}; 407static devclass_t iwn_devclass; 408 409DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0); 410 411MODULE_VERSION(iwn, 1); 412 413MODULE_DEPEND(iwn, firmware, 1, 1, 1); 414MODULE_DEPEND(iwn, pci, 1, 1, 1); 415MODULE_DEPEND(iwn, wlan, 1, 1, 1); 416 417static int 418iwn_probe(device_t dev) 419{ 420 const struct iwn_ident *ident; 421 422 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 423 if (pci_get_vendor(dev) == ident->vendor && 424 pci_get_device(dev) == ident->device) { 425 device_set_desc(dev, ident->name); 426 return 0; 427 } 428 } 429 return ENXIO; 430} 431 432static int 433iwn_attach(device_t dev) 434{ 435 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 436 struct ieee80211com *ic; 437 struct ifnet *ifp; 438 uint32_t reg; 439 int i, error, result; 440 uint8_t macaddr[IEEE80211_ADDR_LEN]; 441 442 sc->sc_dev = dev; 443 444 /* 445 * Get the offset of the PCI Express Capability Structure in PCI 446 * Configuration Space. 447 */ 448 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 449 if (error != 0) { 450 device_printf(dev, "PCIe capability structure not found!\n"); 451 return error; 452 } 453 454 /* Clear device-specific "PCI retry timeout" register (41h). */ 455 pci_write_config(dev, 0x41, 0, 1); 456 457 /* Hardware bug workaround. */ 458 reg = pci_read_config(dev, PCIR_COMMAND, 1); 459 if (reg & PCIM_CMD_INTxDIS) { 460 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n", 461 __func__); 462 reg &= ~PCIM_CMD_INTxDIS; 463 pci_write_config(dev, PCIR_COMMAND, reg, 1); 464 } 465 466 /* Enable bus-mastering. */ 467 pci_enable_busmaster(dev); 468 469 sc->mem_rid = PCIR_BAR(0); 470 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 471 RF_ACTIVE); 472 if (sc->mem == NULL) { 473 device_printf(dev, "can't map mem space\n"); 474 error = ENOMEM; 475 return error; 476 } 477 sc->sc_st = rman_get_bustag(sc->mem); 478 sc->sc_sh = rman_get_bushandle(sc->mem); 479 480 sc->irq_rid = 0; 481 if ((result = pci_msi_count(dev)) == 1 && 482 pci_alloc_msi(dev, &result) == 0) 483 sc->irq_rid = 1; 484 /* Install interrupt handler. */ 485 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 486 RF_ACTIVE | RF_SHAREABLE); 487 if (sc->irq == NULL) { 488 device_printf(dev, "can't map interrupt\n"); 489 error = ENOMEM; 490 goto fail; 491 } 492 493 IWN_LOCK_INIT(sc); 494 495 /* Read hardware revision and attach. */ 496 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf; 497 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 498 error = iwn4965_attach(sc, pci_get_device(dev)); 499 else 500 error = iwn5000_attach(sc, pci_get_device(dev)); 501 if (error != 0) { 502 device_printf(dev, "could not attach device, error %d\n", 503 error); 504 goto fail; 505 } 506 507 if ((error = iwn_hw_prepare(sc)) != 0) { 508 device_printf(dev, "hardware not ready, error %d\n", error); 509 goto fail; 510 } 511 512 /* Allocate DMA memory for firmware transfers. */ 513 if ((error = iwn_alloc_fwmem(sc)) != 0) { 514 device_printf(dev, 515 "could not allocate memory for firmware, error %d\n", 516 error); 517 goto fail; 518 } 519 520 /* Allocate "Keep Warm" page. */ 521 if ((error = iwn_alloc_kw(sc)) != 0) { 522 device_printf(dev, 523 "could not allocate keep warm page, error %d\n", error); 524 goto fail; 525 } 526 527 /* Allocate ICT table for 5000 Series. */ 528 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 529 (error = iwn_alloc_ict(sc)) != 0) { 530 device_printf(dev, "could not allocate ICT table, error %d\n", 531 error); 532 goto fail; 533 } 534 535 /* Allocate TX scheduler "rings". */ 536 if ((error = iwn_alloc_sched(sc)) != 0) { 537 device_printf(dev, 538 "could not allocate TX scheduler rings, error %d\n", error); 539 goto fail; 540 } 541 542 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 543 for (i = 0; i < sc->ntxqs; i++) { 544 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 545 device_printf(dev, 546 "could not allocate TX ring %d, error %d\n", i, 547 error); 548 goto fail; 549 } 550 } 551 552 /* Allocate RX ring. */ 553 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 554 device_printf(dev, "could not allocate RX ring, error %d\n", 555 error); 556 goto fail; 557 } 558 559 /* Clear pending interrupts. */ 560 IWN_WRITE(sc, IWN_INT, 0xffffffff); 561 562 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 563 if (ifp == NULL) { 564 device_printf(dev, "can not allocate ifnet structure\n"); 565 goto fail; 566 } 567 568 ic = ifp->if_l2com; 569 ic->ic_ifp = ifp; 570 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 571 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 572 573 /* Set device capabilities. */ 574 ic->ic_caps = 575 IEEE80211_C_STA /* station mode supported */ 576 | IEEE80211_C_MONITOR /* monitor mode supported */ 577 | IEEE80211_C_BGSCAN /* background scanning */ 578 | IEEE80211_C_TXPMGT /* tx power management */ 579 | IEEE80211_C_SHSLOT /* short slot time supported */ 580 | IEEE80211_C_WPA 581 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 582#if 0 583 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 584#endif 585 | IEEE80211_C_WME /* WME */ 586 ; 587 588 /* Read MAC address, channels, etc from EEPROM. */ 589 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) { 590 device_printf(dev, "could not read EEPROM, error %d\n", 591 error); 592 goto fail; 593 } 594 595 /* Count the number of available chains. */ 596 sc->ntxchains = 597 ((sc->txchainmask >> 2) & 1) + 598 ((sc->txchainmask >> 1) & 1) + 599 ((sc->txchainmask >> 0) & 1); 600 sc->nrxchains = 601 ((sc->rxchainmask >> 2) & 1) + 602 ((sc->rxchainmask >> 1) & 1) + 603 ((sc->rxchainmask >> 0) & 1); 604 if (bootverbose) { 605 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 606 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 607 macaddr, ":"); 608 } 609 610 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 611 ic->ic_rxstream = sc->nrxchains; 612 ic->ic_txstream = sc->ntxchains; 613 ic->ic_htcaps = 614 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 615 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 616 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 617 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 618#ifdef notyet 619 | IEEE80211_HTCAP_GREENFIELD 620#if IWN_RBUF_SIZE == 8192 621 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 622#else 623 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 624#endif 625#endif 626 /* s/w capabilities */ 627 | IEEE80211_HTC_HT /* HT operation */ 628 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 629#ifdef notyet 630 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 631#endif 632 ; 633 } 634 635 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 636 ifp->if_softc = sc; 637 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 638 ifp->if_init = iwn_init; 639 ifp->if_ioctl = iwn_ioctl; 640 ifp->if_start = iwn_start; 641 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 642 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 643 IFQ_SET_READY(&ifp->if_snd); 644 645 ieee80211_ifattach(ic, macaddr); 646 ic->ic_vap_create = iwn_vap_create; 647 ic->ic_vap_delete = iwn_vap_delete; 648 ic->ic_raw_xmit = iwn_raw_xmit; 649 ic->ic_node_alloc = iwn_node_alloc; 650 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 651 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 652 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 653 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 654 sc->sc_addba_request = ic->ic_addba_request; 655 ic->ic_addba_request = iwn_addba_request; 656 sc->sc_addba_response = ic->ic_addba_response; 657 ic->ic_addba_response = iwn_addba_response; 658 sc->sc_addba_stop = ic->ic_addba_stop; 659 ic->ic_addba_stop = iwn_ampdu_tx_stop; 660 ic->ic_newassoc = iwn_newassoc; 661 ic->ic_wme.wme_update = iwn_updateedca; 662 ic->ic_update_mcast = iwn_update_mcast; 663 ic->ic_scan_start = iwn_scan_start; 664 ic->ic_scan_end = iwn_scan_end; 665 ic->ic_set_channel = iwn_set_channel; 666 ic->ic_scan_curchan = iwn_scan_curchan; 667 ic->ic_scan_mindwell = iwn_scan_mindwell; 668 ic->ic_setregdomain = iwn_setregdomain; 669 670 iwn_radiotap_attach(sc); 671 672 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 673 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 674 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc); 675 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc); 676 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc); 677 678 iwn_sysctlattach(sc); 679 680 /* 681 * Hook our interrupt after all initialization is complete. 682 */ 683 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 684 NULL, iwn_intr, sc, &sc->sc_ih); 685 if (error != 0) { 686 device_printf(dev, "can't establish interrupt, error %d\n", 687 error); 688 goto fail; 689 } 690 691 if (bootverbose) 692 ieee80211_announce(ic); 693 return 0; 694fail: 695 iwn_detach(dev); 696 return error; 697} 698 699static int 700iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 701{ 702 struct iwn_ops *ops = &sc->ops; 703 704 ops->load_firmware = iwn4965_load_firmware; 705 ops->read_eeprom = iwn4965_read_eeprom; 706 ops->post_alive = iwn4965_post_alive; 707 ops->nic_config = iwn4965_nic_config; 708 ops->update_sched = iwn4965_update_sched; 709 ops->get_temperature = iwn4965_get_temperature; 710 ops->get_rssi = iwn4965_get_rssi; 711 ops->set_txpower = iwn4965_set_txpower; 712 ops->init_gains = iwn4965_init_gains; 713 ops->set_gains = iwn4965_set_gains; 714 ops->add_node = iwn4965_add_node; 715 ops->tx_done = iwn4965_tx_done; 716 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 717 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 718 sc->ntxqs = IWN4965_NTXQUEUES; 719 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 720 sc->ndmachnls = IWN4965_NDMACHNLS; 721 sc->broadcast_id = IWN4965_ID_BROADCAST; 722 sc->rxonsz = IWN4965_RXONSZ; 723 sc->schedsz = IWN4965_SCHEDSZ; 724 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 725 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 726 sc->fwsz = IWN4965_FWSZ; 727 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 728 sc->limits = &iwn4965_sensitivity_limits; 729 sc->fwname = "iwn4965fw"; 730 /* Override chains masks, ROM is known to be broken. */ 731 sc->txchainmask = IWN_ANT_AB; 732 sc->rxchainmask = IWN_ANT_ABC; 733 734 return 0; 735} 736 737static int 738iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 739{ 740 struct iwn_ops *ops = &sc->ops; 741 742 ops->load_firmware = iwn5000_load_firmware; 743 ops->read_eeprom = iwn5000_read_eeprom; 744 ops->post_alive = iwn5000_post_alive; 745 ops->nic_config = iwn5000_nic_config; 746 ops->update_sched = iwn5000_update_sched; 747 ops->get_temperature = iwn5000_get_temperature; 748 ops->get_rssi = iwn5000_get_rssi; 749 ops->set_txpower = iwn5000_set_txpower; 750 ops->init_gains = iwn5000_init_gains; 751 ops->set_gains = iwn5000_set_gains; 752 ops->add_node = iwn5000_add_node; 753 ops->tx_done = iwn5000_tx_done; 754 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 755 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 756 sc->ntxqs = IWN5000_NTXQUEUES; 757 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 758 sc->ndmachnls = IWN5000_NDMACHNLS; 759 sc->broadcast_id = IWN5000_ID_BROADCAST; 760 sc->rxonsz = IWN5000_RXONSZ; 761 sc->schedsz = IWN5000_SCHEDSZ; 762 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 763 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 764 sc->fwsz = IWN5000_FWSZ; 765 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 766 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 767 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 768 769 switch (sc->hw_type) { 770 case IWN_HW_REV_TYPE_5100: 771 sc->limits = &iwn5000_sensitivity_limits; 772 sc->fwname = "iwn5000fw"; 773 /* Override chains masks, ROM is known to be broken. */ 774 sc->txchainmask = IWN_ANT_B; 775 sc->rxchainmask = IWN_ANT_AB; 776 break; 777 case IWN_HW_REV_TYPE_5150: 778 sc->limits = &iwn5150_sensitivity_limits; 779 sc->fwname = "iwn5150fw"; 780 break; 781 case IWN_HW_REV_TYPE_5300: 782 case IWN_HW_REV_TYPE_5350: 783 sc->limits = &iwn5000_sensitivity_limits; 784 sc->fwname = "iwn5000fw"; 785 break; 786 case IWN_HW_REV_TYPE_1000: 787 sc->limits = &iwn1000_sensitivity_limits; 788 sc->fwname = "iwn1000fw"; 789 break; 790 case IWN_HW_REV_TYPE_6000: 791 sc->limits = &iwn6000_sensitivity_limits; 792 sc->fwname = "iwn6000fw"; 793 if (pid == 0x422c || pid == 0x4239) { 794 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 795 /* Override chains masks, ROM is known to be broken. */ 796 sc->txchainmask = IWN_ANT_BC; 797 sc->rxchainmask = IWN_ANT_BC; 798 } 799 break; 800 case IWN_HW_REV_TYPE_6050: 801 sc->limits = &iwn6000_sensitivity_limits; 802 sc->fwname = "iwn6050fw"; 803 /* Override chains masks, ROM is known to be broken. */ 804 sc->txchainmask = IWN_ANT_AB; 805 sc->rxchainmask = IWN_ANT_AB; 806 break; 807 case IWN_HW_REV_TYPE_6005: 808 sc->limits = &iwn6000_sensitivity_limits; 809 if (pid != 0x0082 && pid != 0x0085) { 810 sc->fwname = "iwn6000g2bfw"; 811 sc->sc_flags |= IWN_FLAG_ADV_BTCOEX; 812 } else 813 sc->fwname = "iwn6000g2afw"; 814 break; 815 default: 816 device_printf(sc->sc_dev, "adapter type %d not supported\n", 817 sc->hw_type); 818 return ENOTSUP; 819 } 820 return 0; 821} 822 823/* 824 * Attach the interface to 802.11 radiotap. 825 */ 826static void 827iwn_radiotap_attach(struct iwn_softc *sc) 828{ 829 struct ifnet *ifp = sc->sc_ifp; 830 struct ieee80211com *ic = ifp->if_l2com; 831 832 ieee80211_radiotap_attach(ic, 833 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 834 IWN_TX_RADIOTAP_PRESENT, 835 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 836 IWN_RX_RADIOTAP_PRESENT); 837} 838 839static void 840iwn_sysctlattach(struct iwn_softc *sc) 841{ 842 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 843 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 844 845#ifdef IWN_DEBUG 846 sc->sc_debug = 0; 847 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 848 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 849#endif 850} 851 852static struct ieee80211vap * 853iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 854 enum ieee80211_opmode opmode, int flags, 855 const uint8_t bssid[IEEE80211_ADDR_LEN], 856 const uint8_t mac[IEEE80211_ADDR_LEN]) 857{ 858 struct iwn_vap *ivp; 859 struct ieee80211vap *vap; 860 861 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 862 return NULL; 863 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap), 864 M_80211_VAP, M_NOWAIT | M_ZERO); 865 if (ivp == NULL) 866 return NULL; 867 vap = &ivp->iv_vap; 868 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 869 vap->iv_bmissthreshold = 10; /* override default */ 870 /* Override with driver methods. */ 871 ivp->iv_newstate = vap->iv_newstate; 872 vap->iv_newstate = iwn_newstate; 873 874 ieee80211_ratectl_init(vap); 875 /* Complete setup. */ 876 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 877 ic->ic_opmode = opmode; 878 return vap; 879} 880 881static void 882iwn_vap_delete(struct ieee80211vap *vap) 883{ 884 struct iwn_vap *ivp = IWN_VAP(vap); 885 886 ieee80211_ratectl_deinit(vap); 887 ieee80211_vap_detach(vap); 888 free(ivp, M_80211_VAP); 889} 890 891static int 892iwn_detach(device_t dev) 893{ 894 struct iwn_softc *sc = device_get_softc(dev); 895 struct ifnet *ifp = sc->sc_ifp; 896 struct ieee80211com *ic; 897 int qid; 898 899 if (ifp != NULL) { 900 ic = ifp->if_l2com; 901 902 ieee80211_draintask(ic, &sc->sc_reinit_task); 903 ieee80211_draintask(ic, &sc->sc_radioon_task); 904 ieee80211_draintask(ic, &sc->sc_radiooff_task); 905 906 iwn_stop(sc); 907 callout_drain(&sc->watchdog_to); 908 callout_drain(&sc->calib_to); 909 ieee80211_ifdetach(ic); 910 } 911 912 /* Uninstall interrupt handler. */ 913 if (sc->irq != NULL) { 914 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 915 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 916 if (sc->irq_rid == 1) 917 pci_release_msi(dev); 918 } 919 920 /* Free DMA resources. */ 921 iwn_free_rx_ring(sc, &sc->rxq); 922 for (qid = 0; qid < sc->ntxqs; qid++) 923 iwn_free_tx_ring(sc, &sc->txq[qid]); 924 iwn_free_sched(sc); 925 iwn_free_kw(sc); 926 if (sc->ict != NULL) 927 iwn_free_ict(sc); 928 iwn_free_fwmem(sc); 929 930 if (sc->mem != NULL) 931 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 932 933 if (ifp != NULL) 934 if_free(ifp); 935 936 IWN_LOCK_DESTROY(sc); 937 return 0; 938} 939 940static int 941iwn_shutdown(device_t dev) 942{ 943 struct iwn_softc *sc = device_get_softc(dev); 944 945 iwn_stop(sc); 946 return 0; 947} 948 949static int 950iwn_suspend(device_t dev) 951{ 952 struct iwn_softc *sc = device_get_softc(dev); 953 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 954 955 ieee80211_suspend_all(ic); 956 return 0; 957} 958 959static int 960iwn_resume(device_t dev) 961{ 962 struct iwn_softc *sc = device_get_softc(dev); 963 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 964 965 /* Clear device-specific "PCI retry timeout" register (41h). */ 966 pci_write_config(dev, 0x41, 0, 1); 967 968 ieee80211_resume_all(ic); 969 return 0; 970} 971 972static int 973iwn_nic_lock(struct iwn_softc *sc) 974{ 975 int ntries; 976 977 /* Request exclusive access to NIC. */ 978 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 979 980 /* Spin until we actually get the lock. */ 981 for (ntries = 0; ntries < 1000; ntries++) { 982 if ((IWN_READ(sc, IWN_GP_CNTRL) & 983 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 984 IWN_GP_CNTRL_MAC_ACCESS_ENA) 985 return 0; 986 DELAY(10); 987 } 988 return ETIMEDOUT; 989} 990 991static __inline void 992iwn_nic_unlock(struct iwn_softc *sc) 993{ 994 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 995} 996 997static __inline uint32_t 998iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 999{ 1000 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1001 IWN_BARRIER_READ_WRITE(sc); 1002 return IWN_READ(sc, IWN_PRPH_RDATA); 1003} 1004 1005static __inline void 1006iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1007{ 1008 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1009 IWN_BARRIER_WRITE(sc); 1010 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1011} 1012 1013static __inline void 1014iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1015{ 1016 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1017} 1018 1019static __inline void 1020iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1021{ 1022 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1023} 1024 1025static __inline void 1026iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1027 const uint32_t *data, int count) 1028{ 1029 for (; count > 0; count--, data++, addr += 4) 1030 iwn_prph_write(sc, addr, *data); 1031} 1032 1033static __inline uint32_t 1034iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1035{ 1036 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1037 IWN_BARRIER_READ_WRITE(sc); 1038 return IWN_READ(sc, IWN_MEM_RDATA); 1039} 1040 1041static __inline void 1042iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1043{ 1044 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1045 IWN_BARRIER_WRITE(sc); 1046 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1047} 1048 1049static __inline void 1050iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1051{ 1052 uint32_t tmp; 1053 1054 tmp = iwn_mem_read(sc, addr & ~3); 1055 if (addr & 3) 1056 tmp = (tmp & 0x0000ffff) | data << 16; 1057 else 1058 tmp = (tmp & 0xffff0000) | data; 1059 iwn_mem_write(sc, addr & ~3, tmp); 1060} 1061 1062static __inline void 1063iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1064 int count) 1065{ 1066 for (; count > 0; count--, addr += 4) 1067 *data++ = iwn_mem_read(sc, addr); 1068} 1069 1070static __inline void 1071iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1072 int count) 1073{ 1074 for (; count > 0; count--, addr += 4) 1075 iwn_mem_write(sc, addr, val); 1076} 1077 1078static int 1079iwn_eeprom_lock(struct iwn_softc *sc) 1080{ 1081 int i, ntries; 1082 1083 for (i = 0; i < 100; i++) { 1084 /* Request exclusive access to EEPROM. */ 1085 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1086 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1087 1088 /* Spin until we actually get the lock. */ 1089 for (ntries = 0; ntries < 100; ntries++) { 1090 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1091 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1092 return 0; 1093 DELAY(10); 1094 } 1095 } 1096 return ETIMEDOUT; 1097} 1098 1099static __inline void 1100iwn_eeprom_unlock(struct iwn_softc *sc) 1101{ 1102 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1103} 1104 1105/* 1106 * Initialize access by host to One Time Programmable ROM. 1107 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1108 */ 1109static int 1110iwn_init_otprom(struct iwn_softc *sc) 1111{ 1112 uint16_t prev, base, next; 1113 int count, error; 1114 1115 /* Wait for clock stabilization before accessing prph. */ 1116 if ((error = iwn_clock_wait(sc)) != 0) 1117 return error; 1118 1119 if ((error = iwn_nic_lock(sc)) != 0) 1120 return error; 1121 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1122 DELAY(5); 1123 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1124 iwn_nic_unlock(sc); 1125 1126 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1127 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 1128 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1129 IWN_RESET_LINK_PWR_MGMT_DIS); 1130 } 1131 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1132 /* Clear ECC status. */ 1133 IWN_SETBITS(sc, IWN_OTP_GP, 1134 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1135 1136 /* 1137 * Find the block before last block (contains the EEPROM image) 1138 * for HW without OTP shadow RAM. 1139 */ 1140 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 1141 /* Switch to absolute addressing mode. */ 1142 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1143 base = prev = 0; 1144 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 1145 error = iwn_read_prom_data(sc, base, &next, 2); 1146 if (error != 0) 1147 return error; 1148 if (next == 0) /* End of linked-list. */ 1149 break; 1150 prev = base; 1151 base = le16toh(next); 1152 } 1153 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 1154 return EIO; 1155 /* Skip "next" word. */ 1156 sc->prom_base = prev + 1; 1157 } 1158 return 0; 1159} 1160 1161static int 1162iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1163{ 1164 uint8_t *out = data; 1165 uint32_t val, tmp; 1166 int ntries; 1167 1168 addr += sc->prom_base; 1169 for (; count > 0; count -= 2, addr++) { 1170 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1171 for (ntries = 0; ntries < 10; ntries++) { 1172 val = IWN_READ(sc, IWN_EEPROM); 1173 if (val & IWN_EEPROM_READ_VALID) 1174 break; 1175 DELAY(5); 1176 } 1177 if (ntries == 10) { 1178 device_printf(sc->sc_dev, 1179 "timeout reading ROM at 0x%x\n", addr); 1180 return ETIMEDOUT; 1181 } 1182 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1183 /* OTPROM, check for ECC errors. */ 1184 tmp = IWN_READ(sc, IWN_OTP_GP); 1185 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1186 device_printf(sc->sc_dev, 1187 "OTPROM ECC error at 0x%x\n", addr); 1188 return EIO; 1189 } 1190 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1191 /* Correctable ECC error, clear bit. */ 1192 IWN_SETBITS(sc, IWN_OTP_GP, 1193 IWN_OTP_GP_ECC_CORR_STTS); 1194 } 1195 } 1196 *out++ = val >> 16; 1197 if (count > 1) 1198 *out++ = val >> 24; 1199 } 1200 return 0; 1201} 1202 1203static void 1204iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1205{ 1206 if (error != 0) 1207 return; 1208 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1209 *(bus_addr_t *)arg = segs[0].ds_addr; 1210} 1211 1212static int 1213iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1214 void **kvap, bus_size_t size, bus_size_t alignment) 1215{ 1216 int error; 1217 1218 dma->tag = NULL; 1219 dma->size = size; 1220 1221 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1222 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1223 1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag); 1224 if (error != 0) 1225 goto fail; 1226 1227 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1228 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1229 if (error != 0) 1230 goto fail; 1231 1232 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1233 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1234 if (error != 0) 1235 goto fail; 1236 1237 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1238 1239 if (kvap != NULL) 1240 *kvap = dma->vaddr; 1241 1242 return 0; 1243 1244fail: iwn_dma_contig_free(dma); 1245 return error; 1246} 1247 1248static void 1249iwn_dma_contig_free(struct iwn_dma_info *dma) 1250{ 1251 if (dma->map != NULL) { 1252 if (dma->vaddr != NULL) { 1253 bus_dmamap_sync(dma->tag, dma->map, 1254 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1255 bus_dmamap_unload(dma->tag, dma->map); 1256 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map); 1257 dma->vaddr = NULL; 1258 } 1259 bus_dmamap_destroy(dma->tag, dma->map); 1260 dma->map = NULL; 1261 } 1262 if (dma->tag != NULL) { 1263 bus_dma_tag_destroy(dma->tag); 1264 dma->tag = NULL; 1265 } 1266} 1267 1268static int 1269iwn_alloc_sched(struct iwn_softc *sc) 1270{ 1271 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1272 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1273 sc->schedsz, 1024); 1274} 1275 1276static void 1277iwn_free_sched(struct iwn_softc *sc) 1278{ 1279 iwn_dma_contig_free(&sc->sched_dma); 1280} 1281 1282static int 1283iwn_alloc_kw(struct iwn_softc *sc) 1284{ 1285 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1286 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1287} 1288 1289static void 1290iwn_free_kw(struct iwn_softc *sc) 1291{ 1292 iwn_dma_contig_free(&sc->kw_dma); 1293} 1294 1295static int 1296iwn_alloc_ict(struct iwn_softc *sc) 1297{ 1298 /* ICT table must be aligned on a 4KB boundary. */ 1299 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1300 IWN_ICT_SIZE, 4096); 1301} 1302 1303static void 1304iwn_free_ict(struct iwn_softc *sc) 1305{ 1306 iwn_dma_contig_free(&sc->ict_dma); 1307} 1308 1309static int 1310iwn_alloc_fwmem(struct iwn_softc *sc) 1311{ 1312 /* Must be aligned on a 16-byte boundary. */ 1313 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1314} 1315 1316static void 1317iwn_free_fwmem(struct iwn_softc *sc) 1318{ 1319 iwn_dma_contig_free(&sc->fw_dma); 1320} 1321 1322static int 1323iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1324{ 1325 bus_size_t size; 1326 int i, error; 1327 1328 ring->cur = 0; 1329 1330 /* Allocate RX descriptors (256-byte aligned). */ 1331 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1332 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1333 size, 256); 1334 if (error != 0) { 1335 device_printf(sc->sc_dev, 1336 "%s: could not allocate RX ring DMA memory, error %d\n", 1337 __func__, error); 1338 goto fail; 1339 } 1340 1341 /* Allocate RX status area (16-byte aligned). */ 1342 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1343 sizeof (struct iwn_rx_status), 16); 1344 if (error != 0) { 1345 device_printf(sc->sc_dev, 1346 "%s: could not allocate RX status DMA memory, error %d\n", 1347 __func__, error); 1348 goto fail; 1349 } 1350 1351 /* Create RX buffer DMA tag. */ 1352 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1353 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1354 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL, 1355 &ring->data_dmat); 1356 if (error != 0) { 1357 device_printf(sc->sc_dev, 1358 "%s: could not create RX buf DMA tag, error %d\n", 1359 __func__, error); 1360 goto fail; 1361 } 1362 1363 /* 1364 * Allocate and map RX buffers. 1365 */ 1366 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1367 struct iwn_rx_data *data = &ring->data[i]; 1368 bus_addr_t paddr; 1369 1370 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1371 if (error != 0) { 1372 device_printf(sc->sc_dev, 1373 "%s: could not create RX buf DMA map, error %d\n", 1374 __func__, error); 1375 goto fail; 1376 } 1377 1378 data->m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 1379 IWN_RBUF_SIZE); 1380 if (data->m == NULL) { 1381 device_printf(sc->sc_dev, 1382 "%s: could not allocate RX mbuf\n", __func__); 1383 error = ENOBUFS; 1384 goto fail; 1385 } 1386 1387 error = bus_dmamap_load(ring->data_dmat, data->map, 1388 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1389 &paddr, BUS_DMA_NOWAIT); 1390 if (error != 0 && error != EFBIG) { 1391 device_printf(sc->sc_dev, 1392 "%s: can't not map mbuf, error %d\n", __func__, 1393 error); 1394 goto fail; 1395 } 1396 1397 /* Set physical address of RX buffer (256-byte aligned). */ 1398 ring->desc[i] = htole32(paddr >> 8); 1399 } 1400 1401 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1402 BUS_DMASYNC_PREWRITE); 1403 1404 return 0; 1405 1406fail: iwn_free_rx_ring(sc, ring); 1407 return error; 1408} 1409 1410static void 1411iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1412{ 1413 int ntries; 1414 1415 if (iwn_nic_lock(sc) == 0) { 1416 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1417 for (ntries = 0; ntries < 1000; ntries++) { 1418 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1419 IWN_FH_RX_STATUS_IDLE) 1420 break; 1421 DELAY(10); 1422 } 1423 iwn_nic_unlock(sc); 1424 } 1425 ring->cur = 0; 1426 sc->last_rx_valid = 0; 1427} 1428 1429static void 1430iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1431{ 1432 int i; 1433 1434 iwn_dma_contig_free(&ring->desc_dma); 1435 iwn_dma_contig_free(&ring->stat_dma); 1436 1437 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1438 struct iwn_rx_data *data = &ring->data[i]; 1439 1440 if (data->m != NULL) { 1441 bus_dmamap_sync(ring->data_dmat, data->map, 1442 BUS_DMASYNC_POSTREAD); 1443 bus_dmamap_unload(ring->data_dmat, data->map); 1444 m_freem(data->m); 1445 data->m = NULL; 1446 } 1447 if (data->map != NULL) 1448 bus_dmamap_destroy(ring->data_dmat, data->map); 1449 } 1450 if (ring->data_dmat != NULL) { 1451 bus_dma_tag_destroy(ring->data_dmat); 1452 ring->data_dmat = NULL; 1453 } 1454} 1455 1456static int 1457iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1458{ 1459 bus_addr_t paddr; 1460 bus_size_t size; 1461 int i, error; 1462 1463 ring->qid = qid; 1464 ring->queued = 0; 1465 ring->cur = 0; 1466 1467 /* Allocate TX descriptors (256-byte aligned). */ 1468 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1469 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1470 size, 256); 1471 if (error != 0) { 1472 device_printf(sc->sc_dev, 1473 "%s: could not allocate TX ring DMA memory, error %d\n", 1474 __func__, error); 1475 goto fail; 1476 } 1477 1478 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1479 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 1480 size, 4); 1481 if (error != 0) { 1482 device_printf(sc->sc_dev, 1483 "%s: could not allocate TX cmd DMA memory, error %d\n", 1484 __func__, error); 1485 goto fail; 1486 } 1487 1488 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1489 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1490 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, 1491 &ring->data_dmat); 1492 if (error != 0) { 1493 device_printf(sc->sc_dev, 1494 "%s: could not create TX buf DMA tag, error %d\n", 1495 __func__, error); 1496 goto fail; 1497 } 1498 1499 paddr = ring->cmd_dma.paddr; 1500 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1501 struct iwn_tx_data *data = &ring->data[i]; 1502 1503 data->cmd_paddr = paddr; 1504 data->scratch_paddr = paddr + 12; 1505 paddr += sizeof (struct iwn_tx_cmd); 1506 1507 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1508 if (error != 0) { 1509 device_printf(sc->sc_dev, 1510 "%s: could not create TX buf DMA map, error %d\n", 1511 __func__, error); 1512 goto fail; 1513 } 1514 } 1515 return 0; 1516 1517fail: iwn_free_tx_ring(sc, ring); 1518 return error; 1519} 1520 1521static void 1522iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1523{ 1524 int i; 1525 1526 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1527 struct iwn_tx_data *data = &ring->data[i]; 1528 1529 if (data->m != NULL) { 1530 bus_dmamap_sync(ring->data_dmat, data->map, 1531 BUS_DMASYNC_POSTWRITE); 1532 bus_dmamap_unload(ring->data_dmat, data->map); 1533 m_freem(data->m); 1534 data->m = NULL; 1535 } 1536 } 1537 /* Clear TX descriptors. */ 1538 memset(ring->desc, 0, ring->desc_dma.size); 1539 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1540 BUS_DMASYNC_PREWRITE); 1541 sc->qfullmsk &= ~(1 << ring->qid); 1542 ring->queued = 0; 1543 ring->cur = 0; 1544} 1545 1546static void 1547iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1548{ 1549 int i; 1550 1551 iwn_dma_contig_free(&ring->desc_dma); 1552 iwn_dma_contig_free(&ring->cmd_dma); 1553 1554 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1555 struct iwn_tx_data *data = &ring->data[i]; 1556 1557 if (data->m != NULL) { 1558 bus_dmamap_sync(ring->data_dmat, data->map, 1559 BUS_DMASYNC_POSTWRITE); 1560 bus_dmamap_unload(ring->data_dmat, data->map); 1561 m_freem(data->m); 1562 } 1563 if (data->map != NULL) 1564 bus_dmamap_destroy(ring->data_dmat, data->map); 1565 } 1566 if (ring->data_dmat != NULL) { 1567 bus_dma_tag_destroy(ring->data_dmat); 1568 ring->data_dmat = NULL; 1569 } 1570} 1571 1572static void 1573iwn5000_ict_reset(struct iwn_softc *sc) 1574{ 1575 /* Disable interrupts. */ 1576 IWN_WRITE(sc, IWN_INT_MASK, 0); 1577 1578 /* Reset ICT table. */ 1579 memset(sc->ict, 0, IWN_ICT_SIZE); 1580 sc->ict_cur = 0; 1581 1582 /* Set physical address of ICT table (4KB aligned). */ 1583 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 1584 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1585 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1586 1587 /* Enable periodic RX interrupt. */ 1588 sc->int_mask |= IWN_INT_RX_PERIODIC; 1589 /* Switch to ICT interrupt mode in driver. */ 1590 sc->sc_flags |= IWN_FLAG_USE_ICT; 1591 1592 /* Re-enable interrupts. */ 1593 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1594 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1595} 1596 1597static int 1598iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 1599{ 1600 struct iwn_ops *ops = &sc->ops; 1601 uint16_t val; 1602 int error; 1603 1604 /* Check whether adapter has an EEPROM or an OTPROM. */ 1605 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1606 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1607 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1608 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 1609 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 1610 1611 /* Adapter has to be powered on for EEPROM access to work. */ 1612 if ((error = iwn_apm_init(sc)) != 0) { 1613 device_printf(sc->sc_dev, 1614 "%s: could not power ON adapter, error %d\n", __func__, 1615 error); 1616 return error; 1617 } 1618 1619 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1620 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 1621 return EIO; 1622 } 1623 if ((error = iwn_eeprom_lock(sc)) != 0) { 1624 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 1625 __func__, error); 1626 return error; 1627 } 1628 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1629 if ((error = iwn_init_otprom(sc)) != 0) { 1630 device_printf(sc->sc_dev, 1631 "%s: could not initialize OTPROM, error %d\n", 1632 __func__, error); 1633 return error; 1634 } 1635 } 1636 1637 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1638 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 1639 /* Check if HT support is bonded out. */ 1640 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1641 sc->sc_flags |= IWN_FLAG_HAS_11N; 1642 1643 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1644 sc->rfcfg = le16toh(val); 1645 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 1646 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1647 if (sc->txchainmask == 0) 1648 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1649 if (sc->rxchainmask == 0) 1650 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1651 1652 /* Read MAC address. */ 1653 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 1654 1655 /* Read adapter-specific information from EEPROM. */ 1656 ops->read_eeprom(sc); 1657 1658 iwn_apm_stop(sc); /* Power OFF adapter. */ 1659 1660 iwn_eeprom_unlock(sc); 1661 return 0; 1662} 1663 1664static void 1665iwn4965_read_eeprom(struct iwn_softc *sc) 1666{ 1667 uint32_t addr; 1668 uint16_t val; 1669 int i; 1670 1671 /* Read regulatory domain (4 ASCII characters). */ 1672 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1673 1674 /* Read the list of authorized channels (20MHz ones only). */ 1675 for (i = 0; i < 7; i++) { 1676 addr = iwn4965_regulatory_bands[i]; 1677 iwn_read_eeprom_channels(sc, i, addr); 1678 } 1679 1680 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1681 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1682 sc->maxpwr2GHz = val & 0xff; 1683 sc->maxpwr5GHz = val >> 8; 1684 /* Check that EEPROM values are within valid range. */ 1685 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1686 sc->maxpwr5GHz = 38; 1687 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1688 sc->maxpwr2GHz = 38; 1689 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 1690 sc->maxpwr2GHz, sc->maxpwr5GHz); 1691 1692 /* Read samples for each TX power group. */ 1693 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1694 sizeof sc->bands); 1695 1696 /* Read voltage at which samples were taken. */ 1697 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1698 sc->eeprom_voltage = (int16_t)le16toh(val); 1699 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 1700 sc->eeprom_voltage); 1701 1702#ifdef IWN_DEBUG 1703 /* Print samples. */ 1704 if (sc->sc_debug & IWN_DEBUG_ANY) { 1705 for (i = 0; i < IWN_NBANDS; i++) 1706 iwn4965_print_power_group(sc, i); 1707 } 1708#endif 1709} 1710 1711#ifdef IWN_DEBUG 1712static void 1713iwn4965_print_power_group(struct iwn_softc *sc, int i) 1714{ 1715 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1716 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1717 int j, c; 1718 1719 printf("===band %d===\n", i); 1720 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1721 printf("chan1 num=%d\n", chans[0].num); 1722 for (c = 0; c < 2; c++) { 1723 for (j = 0; j < IWN_NSAMPLES; j++) { 1724 printf("chain %d, sample %d: temp=%d gain=%d " 1725 "power=%d pa_det=%d\n", c, j, 1726 chans[0].samples[c][j].temp, 1727 chans[0].samples[c][j].gain, 1728 chans[0].samples[c][j].power, 1729 chans[0].samples[c][j].pa_det); 1730 } 1731 } 1732 printf("chan2 num=%d\n", chans[1].num); 1733 for (c = 0; c < 2; c++) { 1734 for (j = 0; j < IWN_NSAMPLES; j++) { 1735 printf("chain %d, sample %d: temp=%d gain=%d " 1736 "power=%d pa_det=%d\n", c, j, 1737 chans[1].samples[c][j].temp, 1738 chans[1].samples[c][j].gain, 1739 chans[1].samples[c][j].power, 1740 chans[1].samples[c][j].pa_det); 1741 } 1742 } 1743} 1744#endif 1745 1746static void 1747iwn5000_read_eeprom(struct iwn_softc *sc) 1748{ 1749 struct iwn5000_eeprom_calib_hdr hdr; 1750 int32_t volt; 1751 uint32_t base, addr; 1752 uint16_t val; 1753 int i; 1754 1755 /* Read regulatory domain (4 ASCII characters). */ 1756 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1757 base = le16toh(val); 1758 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1759 sc->eeprom_domain, 4); 1760 1761 /* Read the list of authorized channels (20MHz ones only). */ 1762 for (i = 0; i < 7; i++) { 1763 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1764 addr = base + iwn6000_regulatory_bands[i]; 1765 else 1766 addr = base + iwn5000_regulatory_bands[i]; 1767 iwn_read_eeprom_channels(sc, i, addr); 1768 } 1769 1770 /* Read enhanced TX power information for 6000 Series. */ 1771 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1772 iwn_read_eeprom_enhinfo(sc); 1773 1774 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1775 base = le16toh(val); 1776 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1777 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 1778 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 1779 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 1780 sc->calib_ver = hdr.version; 1781 1782 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1783 /* Compute temperature offset. */ 1784 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1785 sc->eeprom_temp = le16toh(val); 1786 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1787 volt = le16toh(val); 1788 sc->temp_off = sc->eeprom_temp - (volt / -5); 1789 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 1790 sc->eeprom_temp, volt, sc->temp_off); 1791 } else { 1792 /* Read crystal calibration. */ 1793 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1794 &sc->eeprom_crystal, sizeof (uint32_t)); 1795 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 1796 le32toh(sc->eeprom_crystal)); 1797 } 1798} 1799 1800/* 1801 * Translate EEPROM flags to net80211. 1802 */ 1803static uint32_t 1804iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 1805{ 1806 uint32_t nflags; 1807 1808 nflags = 0; 1809 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 1810 nflags |= IEEE80211_CHAN_PASSIVE; 1811 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 1812 nflags |= IEEE80211_CHAN_NOADHOC; 1813 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 1814 nflags |= IEEE80211_CHAN_DFS; 1815 /* XXX apparently IBSS may still be marked */ 1816 nflags |= IEEE80211_CHAN_NOADHOC; 1817 } 1818 1819 return nflags; 1820} 1821 1822static void 1823iwn_read_eeprom_band(struct iwn_softc *sc, int n) 1824{ 1825 struct ifnet *ifp = sc->sc_ifp; 1826 struct ieee80211com *ic = ifp->if_l2com; 1827 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1828 const struct iwn_chan_band *band = &iwn_bands[n]; 1829 struct ieee80211_channel *c; 1830 uint8_t chan; 1831 int i, nflags; 1832 1833 for (i = 0; i < band->nchan; i++) { 1834 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1835 DPRINTF(sc, IWN_DEBUG_RESET, 1836 "skip chan %d flags 0x%x maxpwr %d\n", 1837 band->chan[i], channels[i].flags, 1838 channels[i].maxpwr); 1839 continue; 1840 } 1841 chan = band->chan[i]; 1842 nflags = iwn_eeprom_channel_flags(&channels[i]); 1843 1844 c = &ic->ic_channels[ic->ic_nchans++]; 1845 c->ic_ieee = chan; 1846 c->ic_maxregpower = channels[i].maxpwr; 1847 c->ic_maxpower = 2*c->ic_maxregpower; 1848 1849 if (n == 0) { /* 2GHz band */ 1850 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G); 1851 /* G =>'s B is supported */ 1852 c->ic_flags = IEEE80211_CHAN_B | nflags; 1853 c = &ic->ic_channels[ic->ic_nchans++]; 1854 c[0] = c[-1]; 1855 c->ic_flags = IEEE80211_CHAN_G | nflags; 1856 } else { /* 5GHz band */ 1857 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A); 1858 c->ic_flags = IEEE80211_CHAN_A | nflags; 1859 } 1860 1861 /* Save maximum allowed TX power for this channel. */ 1862 sc->maxpwr[chan] = channels[i].maxpwr; 1863 1864 DPRINTF(sc, IWN_DEBUG_RESET, 1865 "add chan %d flags 0x%x maxpwr %d\n", chan, 1866 channels[i].flags, channels[i].maxpwr); 1867 1868 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 1869 /* add HT20, HT40 added separately */ 1870 c = &ic->ic_channels[ic->ic_nchans++]; 1871 c[0] = c[-1]; 1872 c->ic_flags |= IEEE80211_CHAN_HT20; 1873 } 1874 } 1875} 1876 1877static void 1878iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 1879{ 1880 struct ifnet *ifp = sc->sc_ifp; 1881 struct ieee80211com *ic = ifp->if_l2com; 1882 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 1883 const struct iwn_chan_band *band = &iwn_bands[n]; 1884 struct ieee80211_channel *c, *cent, *extc; 1885 uint8_t chan; 1886 int i, nflags; 1887 1888 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) 1889 return; 1890 1891 for (i = 0; i < band->nchan; i++) { 1892 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 1893 DPRINTF(sc, IWN_DEBUG_RESET, 1894 "skip chan %d flags 0x%x maxpwr %d\n", 1895 band->chan[i], channels[i].flags, 1896 channels[i].maxpwr); 1897 continue; 1898 } 1899 chan = band->chan[i]; 1900 nflags = iwn_eeprom_channel_flags(&channels[i]); 1901 1902 /* 1903 * Each entry defines an HT40 channel pair; find the 1904 * center channel, then the extension channel above. 1905 */ 1906 cent = ieee80211_find_channel_byieee(ic, chan, 1907 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 1908 if (cent == NULL) { /* XXX shouldn't happen */ 1909 device_printf(sc->sc_dev, 1910 "%s: no entry for channel %d\n", __func__, chan); 1911 continue; 1912 } 1913 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 1914 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 1915 if (extc == NULL) { 1916 DPRINTF(sc, IWN_DEBUG_RESET, 1917 "%s: skip chan %d, extension channel not found\n", 1918 __func__, chan); 1919 continue; 1920 } 1921 1922 DPRINTF(sc, IWN_DEBUG_RESET, 1923 "add ht40 chan %d flags 0x%x maxpwr %d\n", 1924 chan, channels[i].flags, channels[i].maxpwr); 1925 1926 c = &ic->ic_channels[ic->ic_nchans++]; 1927 c[0] = cent[0]; 1928 c->ic_extieee = extc->ic_ieee; 1929 c->ic_flags &= ~IEEE80211_CHAN_HT; 1930 c->ic_flags |= IEEE80211_CHAN_HT40U | nflags; 1931 c = &ic->ic_channels[ic->ic_nchans++]; 1932 c[0] = extc[0]; 1933 c->ic_extieee = cent->ic_ieee; 1934 c->ic_flags &= ~IEEE80211_CHAN_HT; 1935 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags; 1936 } 1937} 1938 1939static void 1940iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1941{ 1942 struct ifnet *ifp = sc->sc_ifp; 1943 struct ieee80211com *ic = ifp->if_l2com; 1944 1945 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 1946 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 1947 1948 if (n < 5) 1949 iwn_read_eeprom_band(sc, n); 1950 else 1951 iwn_read_eeprom_ht40(sc, n); 1952 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 1953} 1954 1955static struct iwn_eeprom_chan * 1956iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 1957{ 1958 int band, chan, i, j; 1959 1960 if (IEEE80211_IS_CHAN_HT40(c)) { 1961 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 1962 if (IEEE80211_IS_CHAN_HT40D(c)) 1963 chan = c->ic_extieee; 1964 else 1965 chan = c->ic_ieee; 1966 for (i = 0; i < iwn_bands[band].nchan; i++) { 1967 if (iwn_bands[band].chan[i] == chan) 1968 return &sc->eeprom_channels[band][i]; 1969 } 1970 } else { 1971 for (j = 0; j < 5; j++) { 1972 for (i = 0; i < iwn_bands[j].nchan; i++) { 1973 if (iwn_bands[j].chan[i] == c->ic_ieee) 1974 return &sc->eeprom_channels[j][i]; 1975 } 1976 } 1977 } 1978 return NULL; 1979} 1980 1981/* 1982 * Enforce flags read from EEPROM. 1983 */ 1984static int 1985iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 1986 int nchan, struct ieee80211_channel chans[]) 1987{ 1988 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1989 int i; 1990 1991 for (i = 0; i < nchan; i++) { 1992 struct ieee80211_channel *c = &chans[i]; 1993 struct iwn_eeprom_chan *channel; 1994 1995 channel = iwn_find_eeprom_channel(sc, c); 1996 if (channel == NULL) { 1997 if_printf(ic->ic_ifp, 1998 "%s: invalid channel %u freq %u/0x%x\n", 1999 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2000 return EINVAL; 2001 } 2002 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2003 } 2004 2005 return 0; 2006} 2007 2008static void 2009iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2010{ 2011 struct iwn_eeprom_enhinfo enhinfo[35]; 2012 struct ifnet *ifp = sc->sc_ifp; 2013 struct ieee80211com *ic = ifp->if_l2com; 2014 struct ieee80211_channel *c; 2015 uint16_t val, base; 2016 int8_t maxpwr; 2017 uint8_t flags; 2018 int i, j; 2019 2020 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2021 base = le16toh(val); 2022 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2023 enhinfo, sizeof enhinfo); 2024 2025 for (i = 0; i < nitems(enhinfo); i++) { 2026 flags = enhinfo[i].flags; 2027 if (!(flags & IWN_ENHINFO_VALID)) 2028 continue; /* Skip invalid entries. */ 2029 2030 maxpwr = 0; 2031 if (sc->txchainmask & IWN_ANT_A) 2032 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2033 if (sc->txchainmask & IWN_ANT_B) 2034 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2035 if (sc->txchainmask & IWN_ANT_C) 2036 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2037 if (sc->ntxchains == 2) 2038 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2039 else if (sc->ntxchains == 3) 2040 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2041 2042 for (j = 0; j < ic->ic_nchans; j++) { 2043 c = &ic->ic_channels[j]; 2044 if ((flags & IWN_ENHINFO_5GHZ)) { 2045 if (!IEEE80211_IS_CHAN_A(c)) 2046 continue; 2047 } else if ((flags & IWN_ENHINFO_OFDM)) { 2048 if (!IEEE80211_IS_CHAN_G(c)) 2049 continue; 2050 } else if (!IEEE80211_IS_CHAN_B(c)) 2051 continue; 2052 if ((flags & IWN_ENHINFO_HT40)) { 2053 if (!IEEE80211_IS_CHAN_HT40(c)) 2054 continue; 2055 } else { 2056 if (IEEE80211_IS_CHAN_HT40(c)) 2057 continue; 2058 } 2059 if (enhinfo[i].chan != 0 && 2060 enhinfo[i].chan != c->ic_ieee) 2061 continue; 2062 2063 DPRINTF(sc, IWN_DEBUG_RESET, 2064 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2065 c->ic_flags, maxpwr / 2); 2066 c->ic_maxregpower = maxpwr / 2; 2067 c->ic_maxpower = maxpwr; 2068 } 2069 } 2070} 2071 2072static struct ieee80211_node * 2073iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2074{ 2075 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO); 2076} 2077 2078static __inline int 2079rate2plcp(int rate) 2080{ 2081 switch (rate & 0xff) { 2082 case 12: return 0xd; 2083 case 18: return 0xf; 2084 case 24: return 0x5; 2085 case 36: return 0x7; 2086 case 48: return 0x9; 2087 case 72: return 0xb; 2088 case 96: return 0x1; 2089 case 108: return 0x3; 2090 case 2: return 10; 2091 case 4: return 20; 2092 case 11: return 55; 2093 case 22: return 110; 2094 } 2095 return 0; 2096} 2097 2098static void 2099iwn_newassoc(struct ieee80211_node *ni, int isnew) 2100{ 2101#define RV(v) ((v) & IEEE80211_RATE_VAL) 2102 struct ieee80211com *ic = ni->ni_ic; 2103 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2104 struct iwn_node *wn = (void *)ni; 2105 uint8_t txant1, txant2; 2106 int i, plcp, rate, ridx; 2107 2108 /* Use the first valid TX antenna. */ 2109 txant1 = IWN_LSB(sc->txchainmask); 2110 txant2 = IWN_LSB(sc->txchainmask & ~txant1); 2111 2112 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 2113 ridx = ni->ni_rates.rs_nrates - 1; 2114 for (i = ni->ni_htrates.rs_nrates - 1; i >= 0; i--) { 2115 plcp = RV(ni->ni_htrates.rs_rates[i]) | IWN_RFLAG_MCS; 2116 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2117 plcp |= IWN_RFLAG_HT40; 2118 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2119 plcp |= IWN_RFLAG_SGI; 2120 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) 2121 plcp |= IWN_RFLAG_SGI; 2122 if (RV(ni->ni_htrates.rs_rates[i]) > 7) 2123 plcp |= IWN_RFLAG_ANT(txant1 | txant2); 2124 else 2125 plcp |= IWN_RFLAG_ANT(txant1); 2126 if (ridx >= 0) { 2127 rate = RV(ni->ni_rates.rs_rates[ridx]); 2128 wn->ridx[rate] = plcp; 2129 } 2130 wn->ridx[IEEE80211_RATE_MCS | i] = plcp; 2131 ridx--; 2132 } 2133 } else { 2134 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 2135 rate = RV(ni->ni_rates.rs_rates[i]); 2136 plcp = rate2plcp(rate); 2137 ridx = ic->ic_rt->rateCodeToIndex[rate]; 2138 if (ridx < IWN_RIDX_OFDM6 && 2139 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2140 plcp |= IWN_RFLAG_CCK; 2141 plcp |= IWN_RFLAG_ANT(txant1); 2142 wn->ridx[rate] = htole32(plcp); 2143 } 2144 } 2145#undef RV 2146} 2147 2148static int 2149iwn_media_change(struct ifnet *ifp) 2150{ 2151 int error; 2152 2153 error = ieee80211_media_change(ifp); 2154 /* NB: only the fixed rate can change and that doesn't need a reset */ 2155 return (error == ENETRESET ? 0 : error); 2156} 2157 2158static int 2159iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2160{ 2161 struct iwn_vap *ivp = IWN_VAP(vap); 2162 struct ieee80211com *ic = vap->iv_ic; 2163 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2164 int error = 0; 2165 2166 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2167 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2168 2169 IEEE80211_UNLOCK(ic); 2170 IWN_LOCK(sc); 2171 callout_stop(&sc->calib_to); 2172 2173 switch (nstate) { 2174 case IEEE80211_S_ASSOC: 2175 if (vap->iv_state != IEEE80211_S_RUN) 2176 break; 2177 /* FALLTHROUGH */ 2178 case IEEE80211_S_AUTH: 2179 if (vap->iv_state == IEEE80211_S_AUTH) 2180 break; 2181 2182 /* 2183 * !AUTH -> AUTH transition requires state reset to handle 2184 * reassociations correctly. 2185 */ 2186 sc->rxon.associd = 0; 2187 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 2188 sc->calib.state = IWN_CALIB_STATE_INIT; 2189 2190 if ((error = iwn_auth(sc, vap)) != 0) { 2191 device_printf(sc->sc_dev, 2192 "%s: could not move to auth state\n", __func__); 2193 } 2194 break; 2195 2196 case IEEE80211_S_RUN: 2197 /* 2198 * RUN -> RUN transition; Just restart the timers. 2199 */ 2200 if (vap->iv_state == IEEE80211_S_RUN) { 2201 sc->calib_cnt = 0; 2202 break; 2203 } 2204 2205 /* 2206 * !RUN -> RUN requires setting the association id 2207 * which is done with a firmware cmd. We also defer 2208 * starting the timers until that work is done. 2209 */ 2210 if ((error = iwn_run(sc, vap)) != 0) { 2211 device_printf(sc->sc_dev, 2212 "%s: could not move to run state\n", __func__); 2213 } 2214 break; 2215 2216 case IEEE80211_S_INIT: 2217 sc->calib.state = IWN_CALIB_STATE_INIT; 2218 break; 2219 2220 default: 2221 break; 2222 } 2223 IWN_UNLOCK(sc); 2224 IEEE80211_LOCK(ic); 2225 if (error != 0) 2226 return error; 2227 return ivp->iv_newstate(vap, nstate, arg); 2228} 2229 2230static void 2231iwn_calib_timeout(void *arg) 2232{ 2233 struct iwn_softc *sc = arg; 2234 2235 IWN_LOCK_ASSERT(sc); 2236 2237 /* Force automatic TX power calibration every 60 secs. */ 2238 if (++sc->calib_cnt >= 120) { 2239 uint32_t flags = 0; 2240 2241 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2242 "sending request for statistics"); 2243 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2244 sizeof flags, 1); 2245 sc->calib_cnt = 0; 2246 } 2247 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2248 sc); 2249} 2250 2251/* 2252 * Process an RX_PHY firmware notification. This is usually immediately 2253 * followed by an MPDU_RX_DONE notification. 2254 */ 2255static void 2256iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2257 struct iwn_rx_data *data) 2258{ 2259 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2260 2261 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2262 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2263 2264 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2265 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2266 sc->last_rx_valid = 1; 2267} 2268 2269/* 2270 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2271 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2272 */ 2273static void 2274iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2275 struct iwn_rx_data *data) 2276{ 2277 struct iwn_ops *ops = &sc->ops; 2278 struct ifnet *ifp = sc->sc_ifp; 2279 struct ieee80211com *ic = ifp->if_l2com; 2280 struct iwn_rx_ring *ring = &sc->rxq; 2281 struct ieee80211_frame *wh; 2282 struct ieee80211_node *ni; 2283 struct mbuf *m, *m1; 2284 struct iwn_rx_stat *stat; 2285 caddr_t head; 2286 bus_addr_t paddr; 2287 uint32_t flags; 2288 int error, len, rssi, nf; 2289 2290 if (desc->type == IWN_MPDU_RX_DONE) { 2291 /* Check for prior RX_PHY notification. */ 2292 if (!sc->last_rx_valid) { 2293 DPRINTF(sc, IWN_DEBUG_ANY, 2294 "%s: missing RX_PHY\n", __func__); 2295 return; 2296 } 2297 stat = &sc->last_rx_stat; 2298 } else 2299 stat = (struct iwn_rx_stat *)(desc + 1); 2300 2301 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2302 2303 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2304 device_printf(sc->sc_dev, 2305 "%s: invalid RX statistic header, len %d\n", __func__, 2306 stat->cfg_phy_len); 2307 return; 2308 } 2309 if (desc->type == IWN_MPDU_RX_DONE) { 2310 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2311 head = (caddr_t)(mpdu + 1); 2312 len = le16toh(mpdu->len); 2313 } else { 2314 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2315 len = le16toh(stat->len); 2316 } 2317 2318 flags = le32toh(*(uint32_t *)(head + len)); 2319 2320 /* Discard frames with a bad FCS early. */ 2321 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2322 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 2323 __func__, flags); 2324 ifp->if_ierrors++; 2325 return; 2326 } 2327 /* Discard frames that are too short. */ 2328 if (len < sizeof (*wh)) { 2329 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2330 __func__, len); 2331 ifp->if_ierrors++; 2332 return; 2333 } 2334 2335 m1 = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 2336 if (m1 == NULL) { 2337 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 2338 __func__); 2339 ifp->if_ierrors++; 2340 return; 2341 } 2342 bus_dmamap_unload(ring->data_dmat, data->map); 2343 2344 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 2345 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 2346 if (error != 0 && error != EFBIG) { 2347 device_printf(sc->sc_dev, 2348 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 2349 m_freem(m1); 2350 2351 /* Try to reload the old mbuf. */ 2352 error = bus_dmamap_load(ring->data_dmat, data->map, 2353 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 2354 &paddr, BUS_DMA_NOWAIT); 2355 if (error != 0 && error != EFBIG) { 2356 panic("%s: could not load old RX mbuf", __func__); 2357 } 2358 /* Physical address may have changed. */ 2359 ring->desc[ring->cur] = htole32(paddr >> 8); 2360 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map, 2361 BUS_DMASYNC_PREWRITE); 2362 ifp->if_ierrors++; 2363 return; 2364 } 2365 2366 m = data->m; 2367 data->m = m1; 2368 /* Update RX descriptor. */ 2369 ring->desc[ring->cur] = htole32(paddr >> 8); 2370 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2371 BUS_DMASYNC_PREWRITE); 2372 2373 /* Finalize mbuf. */ 2374 m->m_pkthdr.rcvif = ifp; 2375 m->m_data = head; 2376 m->m_pkthdr.len = m->m_len = len; 2377 2378 /* Grab a reference to the source node. */ 2379 wh = mtod(m, struct ieee80211_frame *); 2380 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2381 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 2382 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 2383 2384 rssi = ops->get_rssi(sc, stat); 2385 2386 if (ieee80211_radiotap_active(ic)) { 2387 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2388 2389 tap->wr_flags = 0; 2390 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2391 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2392 tap->wr_dbm_antsignal = (int8_t)rssi; 2393 tap->wr_dbm_antnoise = (int8_t)nf; 2394 tap->wr_tsft = stat->tstamp; 2395 switch (stat->rate) { 2396 /* CCK rates. */ 2397 case 10: tap->wr_rate = 2; break; 2398 case 20: tap->wr_rate = 4; break; 2399 case 55: tap->wr_rate = 11; break; 2400 case 110: tap->wr_rate = 22; break; 2401 /* OFDM rates. */ 2402 case 0xd: tap->wr_rate = 12; break; 2403 case 0xf: tap->wr_rate = 18; break; 2404 case 0x5: tap->wr_rate = 24; break; 2405 case 0x7: tap->wr_rate = 36; break; 2406 case 0x9: tap->wr_rate = 48; break; 2407 case 0xb: tap->wr_rate = 72; break; 2408 case 0x1: tap->wr_rate = 96; break; 2409 case 0x3: tap->wr_rate = 108; break; 2410 /* Unknown rate: should not happen. */ 2411 default: tap->wr_rate = 0; 2412 } 2413 } 2414 2415 IWN_UNLOCK(sc); 2416 2417 /* Send the frame to the 802.11 layer. */ 2418 if (ni != NULL) { 2419 if (ni->ni_flags & IEEE80211_NODE_HT) 2420 m->m_flags |= M_AMPDU; 2421 (void)ieee80211_input(ni, m, rssi - nf, nf); 2422 /* Node is no longer needed. */ 2423 ieee80211_free_node(ni); 2424 } else 2425 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 2426 2427 IWN_LOCK(sc); 2428} 2429 2430/* Process an incoming Compressed BlockAck. */ 2431static void 2432iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2433 struct iwn_rx_data *data) 2434{ 2435 struct iwn_ops *ops = &sc->ops; 2436 struct ifnet *ifp = sc->sc_ifp; 2437 struct iwn_node *wn; 2438 struct ieee80211_node *ni; 2439 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 2440 struct iwn_tx_ring *txq; 2441 struct iwn_tx_data *txdata; 2442 struct ieee80211_tx_ampdu *tap; 2443 struct mbuf *m; 2444 uint64_t bitmap; 2445 uint16_t ssn; 2446 uint8_t tid; 2447 int ackfailcnt = 0, i, lastidx, qid, *res, shift; 2448 2449 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2450 2451 qid = le16toh(ba->qid); 2452 txq = &sc->txq[ba->qid]; 2453 tap = sc->qid2tap[ba->qid]; 2454 tid = WME_AC_TO_TID(tap->txa_ac); 2455 wn = (void *)tap->txa_ni; 2456 2457 res = NULL; 2458 ssn = 0; 2459 if (!IEEE80211_AMPDU_RUNNING(tap)) { 2460 res = tap->txa_private; 2461 ssn = tap->txa_start & 0xfff; 2462 } 2463 2464 for (lastidx = le16toh(ba->ssn) & 0xff; txq->read != lastidx;) { 2465 txdata = &txq->data[txq->read]; 2466 2467 /* Unmap and free mbuf. */ 2468 bus_dmamap_sync(txq->data_dmat, txdata->map, 2469 BUS_DMASYNC_POSTWRITE); 2470 bus_dmamap_unload(txq->data_dmat, txdata->map); 2471 m = txdata->m, txdata->m = NULL; 2472 ni = txdata->ni, txdata->ni = NULL; 2473 2474 KASSERT(ni != NULL, ("no node")); 2475 KASSERT(m != NULL, ("no mbuf")); 2476 2477 if (m->m_flags & M_TXCB) 2478 ieee80211_process_callback(ni, m, 1); 2479 2480 m_freem(m); 2481 ieee80211_free_node(ni); 2482 2483 txq->queued--; 2484 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 2485 } 2486 2487 if (txq->queued == 0 && res != NULL) { 2488 iwn_nic_lock(sc); 2489 ops->ampdu_tx_stop(sc, qid, tid, ssn); 2490 iwn_nic_unlock(sc); 2491 sc->qid2tap[qid] = NULL; 2492 free(res, M_DEVBUF); 2493 return; 2494 } 2495 2496 if (wn->agg[tid].bitmap == 0) 2497 return; 2498 2499 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 2500 if (shift < 0) 2501 shift += 0x100; 2502 2503 if (wn->agg[tid].nframes > (64 - shift)) 2504 return; 2505 2506 ni = tap->txa_ni; 2507 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap; 2508 for (i = 0; bitmap; i++) { 2509 if ((bitmap & 1) == 0) { 2510 ifp->if_oerrors++; 2511 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 2512 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2513 } else { 2514 ifp->if_opackets++; 2515 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 2516 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2517 } 2518 bitmap >>= 1; 2519 } 2520} 2521 2522/* 2523 * Process a CALIBRATION_RESULT notification sent by the initialization 2524 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2525 */ 2526static void 2527iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2528 struct iwn_rx_data *data) 2529{ 2530 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2531 int len, idx = -1; 2532 2533 /* Runtime firmware should not send such a notification. */ 2534 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2535 return; 2536 2537 len = (le32toh(desc->len) & 0x3fff) - 4; 2538 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2539 2540 switch (calib->code) { 2541 case IWN5000_PHY_CALIB_DC: 2542 if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0 && 2543 (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2544 sc->hw_type >= IWN_HW_REV_TYPE_6000) && 2545 sc->hw_type != IWN_HW_REV_TYPE_6050) 2546 idx = 0; 2547 break; 2548 case IWN5000_PHY_CALIB_LO: 2549 idx = 1; 2550 break; 2551 case IWN5000_PHY_CALIB_TX_IQ: 2552 idx = 2; 2553 break; 2554 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2555 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2556 sc->hw_type != IWN_HW_REV_TYPE_5150) 2557 idx = 3; 2558 break; 2559 case IWN5000_PHY_CALIB_BASE_BAND: 2560 idx = 4; 2561 break; 2562 } 2563 if (idx == -1) /* Ignore other results. */ 2564 return; 2565 2566 /* Save calibration result. */ 2567 if (sc->calibcmd[idx].buf != NULL) 2568 free(sc->calibcmd[idx].buf, M_DEVBUF); 2569 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2570 if (sc->calibcmd[idx].buf == NULL) { 2571 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2572 "not enough memory for calibration result %d\n", 2573 calib->code); 2574 return; 2575 } 2576 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2577 "saving calibration result code=%d len=%d\n", calib->code, len); 2578 sc->calibcmd[idx].len = len; 2579 memcpy(sc->calibcmd[idx].buf, calib, len); 2580} 2581 2582/* 2583 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2584 * The latter is sent by the firmware after each received beacon. 2585 */ 2586static void 2587iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2588 struct iwn_rx_data *data) 2589{ 2590 struct iwn_ops *ops = &sc->ops; 2591 struct ifnet *ifp = sc->sc_ifp; 2592 struct ieee80211com *ic = ifp->if_l2com; 2593 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2594 struct iwn_calib_state *calib = &sc->calib; 2595 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2596 int temp; 2597 2598 /* Ignore statistics received during a scan. */ 2599 if (vap->iv_state != IEEE80211_S_RUN || 2600 (ic->ic_flags & IEEE80211_F_SCAN)) 2601 return; 2602 2603 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2604 2605 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received statistics, cmd %d\n", 2606 __func__, desc->type); 2607 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2608 2609 /* Test if temperature has changed. */ 2610 if (stats->general.temp != sc->rawtemp) { 2611 /* Convert "raw" temperature to degC. */ 2612 sc->rawtemp = stats->general.temp; 2613 temp = ops->get_temperature(sc); 2614 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 2615 __func__, temp); 2616 2617 /* Update TX power if need be (4965AGN only). */ 2618 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2619 iwn4965_power_calibration(sc, temp); 2620 } 2621 2622 if (desc->type != IWN_BEACON_STATISTICS) 2623 return; /* Reply to a statistics request. */ 2624 2625 sc->noise = iwn_get_noise(&stats->rx.general); 2626 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 2627 2628 /* Test that RSSI and noise are present in stats report. */ 2629 if (le32toh(stats->rx.general.flags) != 1) { 2630 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 2631 "received statistics without RSSI"); 2632 return; 2633 } 2634 2635 if (calib->state == IWN_CALIB_STATE_ASSOC) 2636 iwn_collect_noise(sc, &stats->rx.general); 2637 else if (calib->state == IWN_CALIB_STATE_RUN) 2638 iwn_tune_sensitivity(sc, &stats->rx); 2639} 2640 2641/* 2642 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2643 * and 5000 adapters have different incompatible TX status formats. 2644 */ 2645static void 2646iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2647 struct iwn_rx_data *data) 2648{ 2649 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2650 struct iwn_tx_ring *ring; 2651 int qid; 2652 2653 qid = desc->qid & 0xf; 2654 ring = &sc->txq[qid]; 2655 2656 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2657 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2658 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2659 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2660 le32toh(stat->status)); 2661 2662 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2663 if (qid >= sc->firstaggqueue) { 2664 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 2665 &stat->status); 2666 } else { 2667 iwn_tx_done(sc, desc, stat->ackfailcnt, 2668 le32toh(stat->status) & 0xff); 2669 } 2670} 2671 2672static void 2673iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2674 struct iwn_rx_data *data) 2675{ 2676 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2677 struct iwn_tx_ring *ring; 2678 int qid; 2679 2680 qid = desc->qid & 0xf; 2681 ring = &sc->txq[qid]; 2682 2683 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 2684 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 2685 __func__, desc->qid, desc->idx, stat->ackfailcnt, 2686 stat->btkillcnt, stat->rate, le16toh(stat->duration), 2687 le32toh(stat->status)); 2688 2689#ifdef notyet 2690 /* Reset TX scheduler slot. */ 2691 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 2692#endif 2693 2694 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2695 if (qid >= sc->firstaggqueue) { 2696 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 2697 &stat->status); 2698 } else { 2699 iwn_tx_done(sc, desc, stat->ackfailcnt, 2700 le16toh(stat->status) & 0xff); 2701 } 2702} 2703 2704/* 2705 * Adapter-independent backend for TX_DONE firmware notifications. 2706 */ 2707static void 2708iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 2709 uint8_t status) 2710{ 2711 struct ifnet *ifp = sc->sc_ifp; 2712 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 2713 struct iwn_tx_data *data = &ring->data[desc->idx]; 2714 struct mbuf *m; 2715 struct ieee80211_node *ni; 2716 struct ieee80211vap *vap; 2717 2718 KASSERT(data->ni != NULL, ("no node")); 2719 2720 /* Unmap and free mbuf. */ 2721 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 2722 bus_dmamap_unload(ring->data_dmat, data->map); 2723 m = data->m, data->m = NULL; 2724 ni = data->ni, data->ni = NULL; 2725 vap = ni->ni_vap; 2726 2727 if (m->m_flags & M_TXCB) { 2728 /* 2729 * Channels marked for "radar" require traffic to be received 2730 * to unlock before we can transmit. Until traffic is seen 2731 * any attempt to transmit is returned immediately with status 2732 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 2733 * happen on first authenticate after scanning. To workaround 2734 * this we ignore a failure of this sort in AUTH state so the 2735 * 802.11 layer will fall back to using a timeout to wait for 2736 * the AUTH reply. This allows the firmware time to see 2737 * traffic so a subsequent retry of AUTH succeeds. It's 2738 * unclear why the firmware does not maintain state for 2739 * channels recently visited as this would allow immediate 2740 * use of the channel after a scan (where we see traffic). 2741 */ 2742 if (status == IWN_TX_FAIL_TX_LOCKED && 2743 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 2744 ieee80211_process_callback(ni, m, 0); 2745 else 2746 ieee80211_process_callback(ni, m, 2747 (status & IWN_TX_FAIL) != 0); 2748 } 2749 2750 /* 2751 * Update rate control statistics for the node. 2752 */ 2753 if (status & IWN_TX_FAIL) { 2754 ifp->if_oerrors++; 2755 ieee80211_ratectl_tx_complete(vap, ni, 2756 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 2757 } else { 2758 ifp->if_opackets++; 2759 ieee80211_ratectl_tx_complete(vap, ni, 2760 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 2761 } 2762 m_freem(m); 2763 ieee80211_free_node(ni); 2764 2765 sc->sc_tx_timer = 0; 2766 if (--ring->queued < IWN_TX_RING_LOMARK) { 2767 sc->qfullmsk &= ~(1 << ring->qid); 2768 if (sc->qfullmsk == 0 && 2769 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2770 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2771 iwn_start_locked(ifp); 2772 } 2773 } 2774} 2775 2776/* 2777 * Process a "command done" firmware notification. This is where we wakeup 2778 * processes waiting for a synchronous command completion. 2779 */ 2780static void 2781iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2782{ 2783 struct iwn_tx_ring *ring = &sc->txq[4]; 2784 struct iwn_tx_data *data; 2785 2786 if ((desc->qid & 0xf) != 4) 2787 return; /* Not a command ack. */ 2788 2789 data = &ring->data[desc->idx]; 2790 2791 /* If the command was mapped in an mbuf, free it. */ 2792 if (data->m != NULL) { 2793 bus_dmamap_sync(ring->data_dmat, data->map, 2794 BUS_DMASYNC_POSTWRITE); 2795 bus_dmamap_unload(ring->data_dmat, data->map); 2796 m_freem(data->m); 2797 data->m = NULL; 2798 } 2799 wakeup(&ring->desc[desc->idx]); 2800} 2801 2802static void 2803iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 2804 void *stat) 2805{ 2806 struct iwn_ops *ops = &sc->ops; 2807 struct ifnet *ifp = sc->sc_ifp; 2808 struct iwn_tx_ring *ring = &sc->txq[qid]; 2809 struct iwn_tx_data *data; 2810 struct mbuf *m; 2811 struct iwn_node *wn; 2812 struct ieee80211_node *ni; 2813 struct ieee80211_tx_ampdu *tap; 2814 uint64_t bitmap; 2815 uint32_t *status = stat; 2816 uint16_t *aggstatus = stat; 2817 uint16_t ssn; 2818 uint8_t tid; 2819 int bit, i, lastidx, *res, seqno, shift, start; 2820 2821#ifdef NOT_YET 2822 if (nframes == 1) { 2823 if ((*status & 0xff) != 1 && (*status & 0xff) != 2) 2824 printf("ieee80211_send_bar()\n"); 2825 } 2826#endif 2827 2828 bitmap = 0; 2829 start = idx; 2830 for (i = 0; i < nframes; i++) { 2831 if (le16toh(aggstatus[i * 2]) & 0xc) 2832 continue; 2833 2834 idx = le16toh(aggstatus[2*i + 1]) & 0xff; 2835 bit = idx - start; 2836 shift = 0; 2837 if (bit >= 64) { 2838 shift = 0x100 - idx + start; 2839 bit = 0; 2840 start = idx; 2841 } else if (bit <= -64) 2842 bit = 0x100 - start + idx; 2843 else if (bit < 0) { 2844 shift = start - idx; 2845 start = idx; 2846 bit = 0; 2847 } 2848 bitmap = bitmap << shift; 2849 bitmap |= 1ULL << bit; 2850 } 2851 tap = sc->qid2tap[qid]; 2852 tid = WME_AC_TO_TID(tap->txa_ac); 2853 wn = (void *)tap->txa_ni; 2854 wn->agg[tid].bitmap = bitmap; 2855 wn->agg[tid].startidx = start; 2856 wn->agg[tid].nframes = nframes; 2857 2858 res = NULL; 2859 ssn = 0; 2860 if (!IEEE80211_AMPDU_RUNNING(tap)) { 2861 res = tap->txa_private; 2862 ssn = tap->txa_start & 0xfff; 2863 } 2864 2865 seqno = le32toh(*(status + nframes)) & 0xfff; 2866 for (lastidx = (seqno & 0xff); ring->read != lastidx;) { 2867 data = &ring->data[ring->read]; 2868 2869 /* Unmap and free mbuf. */ 2870 bus_dmamap_sync(ring->data_dmat, data->map, 2871 BUS_DMASYNC_POSTWRITE); 2872 bus_dmamap_unload(ring->data_dmat, data->map); 2873 m = data->m, data->m = NULL; 2874 ni = data->ni, data->ni = NULL; 2875 2876 KASSERT(ni != NULL, ("no node")); 2877 KASSERT(m != NULL, ("no mbuf")); 2878 2879 if (m->m_flags & M_TXCB) 2880 ieee80211_process_callback(ni, m, 1); 2881 2882 m_freem(m); 2883 ieee80211_free_node(ni); 2884 2885 ring->queued--; 2886 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT; 2887 } 2888 2889 if (ring->queued == 0 && res != NULL) { 2890 iwn_nic_lock(sc); 2891 ops->ampdu_tx_stop(sc, qid, tid, ssn); 2892 iwn_nic_unlock(sc); 2893 sc->qid2tap[qid] = NULL; 2894 free(res, M_DEVBUF); 2895 return; 2896 } 2897 2898 sc->sc_tx_timer = 0; 2899 if (ring->queued < IWN_TX_RING_LOMARK) { 2900 sc->qfullmsk &= ~(1 << ring->qid); 2901 if (sc->qfullmsk == 0 && 2902 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) { 2903 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2904 iwn_start_locked(ifp); 2905 } 2906 } 2907} 2908 2909/* 2910 * Process an INT_FH_RX or INT_SW_RX interrupt. 2911 */ 2912static void 2913iwn_notif_intr(struct iwn_softc *sc) 2914{ 2915 struct iwn_ops *ops = &sc->ops; 2916 struct ifnet *ifp = sc->sc_ifp; 2917 struct ieee80211com *ic = ifp->if_l2com; 2918 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2919 uint16_t hw; 2920 2921 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 2922 BUS_DMASYNC_POSTREAD); 2923 2924 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 2925 while (sc->rxq.cur != hw) { 2926 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2927 struct iwn_rx_desc *desc; 2928 2929 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2930 BUS_DMASYNC_POSTREAD); 2931 desc = mtod(data->m, struct iwn_rx_desc *); 2932 2933 DPRINTF(sc, IWN_DEBUG_RECV, 2934 "%s: qid %x idx %d flags %x type %d(%s) len %d\n", 2935 __func__, desc->qid & 0xf, desc->idx, desc->flags, 2936 desc->type, iwn_intr_str(desc->type), 2937 le16toh(desc->len)); 2938 2939 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2940 iwn_cmd_done(sc, desc); 2941 2942 switch (desc->type) { 2943 case IWN_RX_PHY: 2944 iwn_rx_phy(sc, desc, data); 2945 break; 2946 2947 case IWN_RX_DONE: /* 4965AGN only. */ 2948 case IWN_MPDU_RX_DONE: 2949 /* An 802.11 frame has been received. */ 2950 iwn_rx_done(sc, desc, data); 2951 break; 2952 2953 case IWN_RX_COMPRESSED_BA: 2954 /* A Compressed BlockAck has been received. */ 2955 iwn_rx_compressed_ba(sc, desc, data); 2956 break; 2957 2958 case IWN_TX_DONE: 2959 /* An 802.11 frame has been transmitted. */ 2960 ops->tx_done(sc, desc, data); 2961 break; 2962 2963 case IWN_RX_STATISTICS: 2964 case IWN_BEACON_STATISTICS: 2965 iwn_rx_statistics(sc, desc, data); 2966 break; 2967 2968 case IWN_BEACON_MISSED: 2969 { 2970 struct iwn_beacon_missed *miss = 2971 (struct iwn_beacon_missed *)(desc + 1); 2972 int misses; 2973 2974 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 2975 BUS_DMASYNC_POSTREAD); 2976 misses = le32toh(miss->consecutive); 2977 2978 DPRINTF(sc, IWN_DEBUG_STATE, 2979 "%s: beacons missed %d/%d\n", __func__, 2980 misses, le32toh(miss->total)); 2981 /* 2982 * If more than 5 consecutive beacons are missed, 2983 * reinitialize the sensitivity state machine. 2984 */ 2985 if (vap->iv_state == IEEE80211_S_RUN && 2986 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 2987 if (misses > 5) 2988 (void)iwn_init_sensitivity(sc); 2989 if (misses >= vap->iv_bmissthreshold) { 2990 IWN_UNLOCK(sc); 2991 ieee80211_beacon_miss(ic); 2992 IWN_LOCK(sc); 2993 } 2994 } 2995 break; 2996 } 2997 case IWN_UC_READY: 2998 { 2999 struct iwn_ucode_info *uc = 3000 (struct iwn_ucode_info *)(desc + 1); 3001 3002 /* The microcontroller is ready. */ 3003 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3004 BUS_DMASYNC_POSTREAD); 3005 DPRINTF(sc, IWN_DEBUG_RESET, 3006 "microcode alive notification version=%d.%d " 3007 "subtype=%x alive=%x\n", uc->major, uc->minor, 3008 uc->subtype, le32toh(uc->valid)); 3009 3010 if (le32toh(uc->valid) != 1) { 3011 device_printf(sc->sc_dev, 3012 "microcontroller initialization failed"); 3013 break; 3014 } 3015 if (uc->subtype == IWN_UCODE_INIT) { 3016 /* Save microcontroller report. */ 3017 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 3018 } 3019 /* Save the address of the error log in SRAM. */ 3020 sc->errptr = le32toh(uc->errptr); 3021 break; 3022 } 3023 case IWN_STATE_CHANGED: 3024 { 3025 uint32_t *status = (uint32_t *)(desc + 1); 3026 3027 /* 3028 * State change allows hardware switch change to be 3029 * noted. However, we handle this in iwn_intr as we 3030 * get both the enable/disble intr. 3031 */ 3032 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3033 BUS_DMASYNC_POSTREAD); 3034 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n", 3035 le32toh(*status)); 3036 break; 3037 } 3038 case IWN_START_SCAN: 3039 { 3040 struct iwn_start_scan *scan = 3041 (struct iwn_start_scan *)(desc + 1); 3042 3043 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3044 BUS_DMASYNC_POSTREAD); 3045 DPRINTF(sc, IWN_DEBUG_ANY, 3046 "%s: scanning channel %d status %x\n", 3047 __func__, scan->chan, le32toh(scan->status)); 3048 break; 3049 } 3050 case IWN_STOP_SCAN: 3051 { 3052 struct iwn_stop_scan *scan = 3053 (struct iwn_stop_scan *)(desc + 1); 3054 3055 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3056 BUS_DMASYNC_POSTREAD); 3057 DPRINTF(sc, IWN_DEBUG_STATE, 3058 "scan finished nchan=%d status=%d chan=%d\n", 3059 scan->nchan, scan->status, scan->chan); 3060 3061 IWN_UNLOCK(sc); 3062 ieee80211_scan_next(vap); 3063 IWN_LOCK(sc); 3064 break; 3065 } 3066 case IWN5000_CALIBRATION_RESULT: 3067 iwn5000_rx_calib_results(sc, desc, data); 3068 break; 3069 3070 case IWN5000_CALIBRATION_DONE: 3071 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3072 wakeup(sc); 3073 break; 3074 } 3075 3076 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3077 } 3078 3079 /* Tell the firmware what we have processed. */ 3080 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3081 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3082} 3083 3084/* 3085 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3086 * from power-down sleep mode. 3087 */ 3088static void 3089iwn_wakeup_intr(struct iwn_softc *sc) 3090{ 3091 int qid; 3092 3093 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 3094 __func__); 3095 3096 /* Wakeup RX and TX rings. */ 3097 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 3098 for (qid = 0; qid < sc->ntxqs; qid++) { 3099 struct iwn_tx_ring *ring = &sc->txq[qid]; 3100 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 3101 } 3102} 3103 3104static void 3105iwn_rftoggle_intr(struct iwn_softc *sc) 3106{ 3107 struct ifnet *ifp = sc->sc_ifp; 3108 struct ieee80211com *ic = ifp->if_l2com; 3109 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 3110 3111 IWN_LOCK_ASSERT(sc); 3112 3113 device_printf(sc->sc_dev, "RF switch: radio %s\n", 3114 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 3115 if (tmp & IWN_GP_CNTRL_RFKILL) 3116 ieee80211_runtask(ic, &sc->sc_radioon_task); 3117 else 3118 ieee80211_runtask(ic, &sc->sc_radiooff_task); 3119} 3120 3121/* 3122 * Dump the error log of the firmware when a firmware panic occurs. Although 3123 * we can't debug the firmware because it is neither open source nor free, it 3124 * can help us to identify certain classes of problems. 3125 */ 3126static void 3127iwn_fatal_intr(struct iwn_softc *sc) 3128{ 3129 struct iwn_fw_dump dump; 3130 int i; 3131 3132 IWN_LOCK_ASSERT(sc); 3133 3134 /* Force a complete recalibration on next init. */ 3135 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 3136 3137 /* Check that the error log address is valid. */ 3138 if (sc->errptr < IWN_FW_DATA_BASE || 3139 sc->errptr + sizeof (dump) > 3140 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 3141 printf("%s: bad firmware error log address 0x%08x\n", __func__, 3142 sc->errptr); 3143 return; 3144 } 3145 if (iwn_nic_lock(sc) != 0) { 3146 printf("%s: could not read firmware error log\n", __func__); 3147 return; 3148 } 3149 /* Read firmware error log from SRAM. */ 3150 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 3151 sizeof (dump) / sizeof (uint32_t)); 3152 iwn_nic_unlock(sc); 3153 3154 if (dump.valid == 0) { 3155 printf("%s: firmware error log is empty\n", __func__); 3156 return; 3157 } 3158 printf("firmware error log:\n"); 3159 printf(" error type = \"%s\" (0x%08X)\n", 3160 (dump.id < nitems(iwn_fw_errmsg)) ? 3161 iwn_fw_errmsg[dump.id] : "UNKNOWN", 3162 dump.id); 3163 printf(" program counter = 0x%08X\n", dump.pc); 3164 printf(" source line = 0x%08X\n", dump.src_line); 3165 printf(" error data = 0x%08X%08X\n", 3166 dump.error_data[0], dump.error_data[1]); 3167 printf(" branch link = 0x%08X%08X\n", 3168 dump.branch_link[0], dump.branch_link[1]); 3169 printf(" interrupt link = 0x%08X%08X\n", 3170 dump.interrupt_link[0], dump.interrupt_link[1]); 3171 printf(" time = %u\n", dump.time[0]); 3172 3173 /* Dump driver status (TX and RX rings) while we're here. */ 3174 printf("driver status:\n"); 3175 for (i = 0; i < sc->ntxqs; i++) { 3176 struct iwn_tx_ring *ring = &sc->txq[i]; 3177 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 3178 i, ring->qid, ring->cur, ring->queued); 3179 } 3180 printf(" rx ring: cur=%d\n", sc->rxq.cur); 3181} 3182 3183static void 3184iwn_intr(void *arg) 3185{ 3186 struct iwn_softc *sc = arg; 3187 struct ifnet *ifp = sc->sc_ifp; 3188 uint32_t r1, r2, tmp; 3189 3190 IWN_LOCK(sc); 3191 3192#if !defined(__HAIKU__) 3193 /* Disable interrupts. */ 3194 IWN_WRITE(sc, IWN_INT_MASK, 0); 3195 3196 /* Read interrupts from ICT (fast) or from registers (slow). */ 3197 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3198 tmp = 0; 3199 while (sc->ict[sc->ict_cur] != 0) { 3200 tmp |= sc->ict[sc->ict_cur]; 3201 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 3202 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 3203 } 3204 tmp = le32toh(tmp); 3205 if (tmp == 0xffffffff) /* Shouldn't happen. */ 3206 tmp = 0; 3207 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 3208 tmp |= 0x8000; 3209 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 3210 r2 = 0; /* Unused. */ 3211 } else { 3212 r1 = IWN_READ(sc, IWN_INT); 3213 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 3214 return; /* Hardware gone! */ 3215 r2 = IWN_READ(sc, IWN_FH_INT); 3216 } 3217#else 3218 r1 = atomic_get((int32 *)&sc->sc_intr_status_1); 3219 r2 = atomic_get((int32 *)&sc->sc_intr_status_2); 3220#endif 3221 3222 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2); 3223 3224 if (r1 == 0 && r2 == 0) 3225 goto done; /* Interrupt not for us. */ 3226 3227 /* Acknowledge interrupts. */ 3228 IWN_WRITE(sc, IWN_INT, r1); 3229 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 3230 IWN_WRITE(sc, IWN_FH_INT, r2); 3231 3232 if (r1 & IWN_INT_RF_TOGGLED) { 3233 iwn_rftoggle_intr(sc); 3234 goto done; 3235 } 3236 if (r1 & IWN_INT_CT_REACHED) { 3237 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 3238 __func__); 3239 } 3240 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 3241 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 3242 __func__); 3243 /* Dump firmware error log and stop. */ 3244 iwn_fatal_intr(sc); 3245 ifp->if_flags &= ~IFF_UP; 3246 iwn_stop_locked(sc); 3247 goto done; 3248 } 3249 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 3250 (r2 & IWN_FH_INT_RX)) { 3251 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3252 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 3253 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 3254 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3255 IWN_INT_PERIODIC_DIS); 3256 iwn_notif_intr(sc); 3257 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 3258 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3259 IWN_INT_PERIODIC_ENA); 3260 } 3261 } else 3262 iwn_notif_intr(sc); 3263 } 3264 3265 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 3266 if (sc->sc_flags & IWN_FLAG_USE_ICT) 3267 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 3268 wakeup(sc); /* FH DMA transfer completed. */ 3269 } 3270 3271 if (r1 & IWN_INT_ALIVE) 3272 wakeup(sc); /* Firmware is alive. */ 3273 3274 if (r1 & IWN_INT_WAKEUP) 3275 iwn_wakeup_intr(sc); 3276 3277done: 3278 /* Re-enable interrupts. */ 3279 if (ifp->if_flags & IFF_UP) 3280 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3281 3282 IWN_UNLOCK(sc); 3283} 3284 3285/* 3286 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 3287 * 5000 adapters use a slightly different format). 3288 */ 3289static void 3290iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3291 uint16_t len) 3292{ 3293 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3294 3295 *w = htole16(len + 8); 3296 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3297 BUS_DMASYNC_PREWRITE); 3298 if (idx < IWN_SCHED_WINSZ) { 3299 *(w + IWN_TX_RING_COUNT) = *w; 3300 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3301 BUS_DMASYNC_PREWRITE); 3302 } 3303} 3304 3305static void 3306iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3307 uint16_t len) 3308{ 3309 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3310 3311 *w = htole16(id << 12 | (len + 8)); 3312 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3313 BUS_DMASYNC_PREWRITE); 3314 if (idx < IWN_SCHED_WINSZ) { 3315 *(w + IWN_TX_RING_COUNT) = *w; 3316 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3317 BUS_DMASYNC_PREWRITE); 3318 } 3319} 3320 3321#ifdef notyet 3322static void 3323iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3324{ 3325 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3326 3327 *w = (*w & htole16(0xf000)) | htole16(1); 3328 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3329 BUS_DMASYNC_PREWRITE); 3330 if (idx < IWN_SCHED_WINSZ) { 3331 *(w + IWN_TX_RING_COUNT) = *w; 3332 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3333 BUS_DMASYNC_PREWRITE); 3334 } 3335} 3336#endif 3337 3338static int 3339iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3340{ 3341 struct iwn_ops *ops = &sc->ops; 3342 const struct ieee80211_txparam *tp; 3343 struct ieee80211vap *vap = ni->ni_vap; 3344 struct ieee80211com *ic = ni->ni_ic; 3345 struct iwn_node *wn = (void *)ni; 3346 struct iwn_tx_ring *ring; 3347 struct iwn_tx_desc *desc; 3348 struct iwn_tx_data *data; 3349 struct iwn_tx_cmd *cmd; 3350 struct iwn_cmd_data *tx; 3351 struct ieee80211_frame *wh; 3352 struct ieee80211_key *k = NULL; 3353 struct mbuf *m1; 3354 uint32_t flags; 3355 uint16_t qos; 3356 u_int hdrlen; 3357 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3358 uint8_t tid, ridx, txant, type; 3359 int ac, i, totlen, error, pad, nsegs = 0, rate; 3360 3361 IWN_LOCK_ASSERT(sc); 3362 3363 wh = mtod(m, struct ieee80211_frame *); 3364 hdrlen = ieee80211_anyhdrsize(wh); 3365 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3366 3367 /* Select EDCA Access Category and TX ring for this frame. */ 3368 if (IEEE80211_QOS_HAS_SEQ(wh)) { 3369 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 3370 tid = qos & IEEE80211_QOS_TID; 3371 } else { 3372 qos = 0; 3373 tid = 0; 3374 } 3375 ac = M_WME_GETAC(m); 3376 if (m->m_flags & M_AMPDU_MPDU) { 3377 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 3378 3379 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3380 m_freem(m); 3381 return EINVAL; 3382 } 3383 3384 ac = *(int *)tap->txa_private; 3385 *(uint16_t *)wh->i_seq = 3386 htole16(ni->ni_txseqs[tid] << IEEE80211_SEQ_SEQ_SHIFT); 3387 ni->ni_txseqs[tid]++; 3388 } 3389 ring = &sc->txq[ac]; 3390 desc = &ring->desc[ring->cur]; 3391 data = &ring->data[ring->cur]; 3392 3393 /* Choose a TX rate index. */ 3394 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 3395 if (type == IEEE80211_FC0_TYPE_MGT) 3396 rate = tp->mgmtrate; 3397 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3398 rate = tp->mcastrate; 3399 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 3400 rate = tp->ucastrate; 3401 else { 3402 /* XXX pass pktlen */ 3403 (void) ieee80211_ratectl_rate(ni, NULL, 0); 3404 rate = ni->ni_txrate; 3405 } 3406 ridx = ic->ic_rt->rateCodeToIndex[rate]; 3407 3408 /* Encrypt the frame if need be. */ 3409 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 3410 /* Retrieve key for TX. */ 3411 k = ieee80211_crypto_encap(ni, m); 3412 if (k == NULL) { 3413 m_freem(m); 3414 return ENOBUFS; 3415 } 3416 /* 802.11 header may have moved. */ 3417 wh = mtod(m, struct ieee80211_frame *); 3418 } 3419 totlen = m->m_pkthdr.len; 3420 3421 if (ieee80211_radiotap_active_vap(vap)) { 3422 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3423 3424 tap->wt_flags = 0; 3425 tap->wt_rate = rate; 3426 if (k != NULL) 3427 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3428 3429 ieee80211_radiotap_tx(vap, m); 3430 } 3431 3432 /* Prepare TX firmware command. */ 3433 cmd = &ring->cmd[ring->cur]; 3434 cmd->code = IWN_CMD_TX_DATA; 3435 cmd->flags = 0; 3436 cmd->qid = ring->qid; 3437 cmd->idx = ring->cur; 3438 3439 tx = (struct iwn_cmd_data *)cmd->data; 3440 /* NB: No need to clear tx, all fields are reinitialized here. */ 3441 tx->scratch = 0; /* clear "scratch" area */ 3442 3443 flags = 0; 3444 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3445 /* Unicast frame, check if an ACK is expected. */ 3446 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 3447 IEEE80211_QOS_ACKPOLICY_NOACK) 3448 flags |= IWN_TX_NEED_ACK; 3449 } 3450 if ((wh->i_fc[0] & 3451 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 3452 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 3453 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 3454 3455 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3456 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3457 3458 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3459 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3460 /* NB: Group frames are sent using CCK in 802.11b/g. */ 3461 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 3462 flags |= IWN_TX_NEED_RTS; 3463 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3464 ridx >= IWN_RIDX_OFDM6) { 3465 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3466 flags |= IWN_TX_NEED_CTS; 3467 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3468 flags |= IWN_TX_NEED_RTS; 3469 } 3470 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3471 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3472 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3473 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3474 flags |= IWN_TX_NEED_PROTECTION; 3475 } else 3476 flags |= IWN_TX_FULL_TXOP; 3477 } 3478 } 3479 3480 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3481 type != IEEE80211_FC0_TYPE_DATA) 3482 tx->id = sc->broadcast_id; 3483 else 3484 tx->id = wn->id; 3485 3486 if (type == IEEE80211_FC0_TYPE_MGT) { 3487 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3488 3489 /* Tell HW to set timestamp in probe responses. */ 3490 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3491 flags |= IWN_TX_INSERT_TSTAMP; 3492 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3493 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3494 tx->timeout = htole16(3); 3495 else 3496 tx->timeout = htole16(2); 3497 } else 3498 tx->timeout = htole16(0); 3499 3500 if (hdrlen & 3) { 3501 /* First segment length must be a multiple of 4. */ 3502 flags |= IWN_TX_NEED_PADDING; 3503 pad = 4 - (hdrlen & 3); 3504 } else 3505 pad = 0; 3506 3507 tx->len = htole16(totlen); 3508 tx->tid = tid; 3509 tx->rts_ntries = 60; 3510 tx->data_ntries = 15; 3511 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3512 tx->rate = wn->ridx[rate]; 3513 if (tx->id == sc->broadcast_id) { 3514 /* Group or management frame. */ 3515 tx->linkq = 0; 3516 /* XXX Alternate between antenna A and B? */ 3517 txant = IWN_LSB(sc->txchainmask); 3518 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 3519 } else { 3520 tx->linkq = ni->ni_rates.rs_nrates - ridx - 1; 3521 flags |= IWN_TX_LINKQ; /* enable MRR */ 3522 } 3523 /* Set physical address of "scratch area". */ 3524 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3525 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3526 3527 /* Copy 802.11 header in TX command. */ 3528 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3529 3530 /* Trim 802.11 header. */ 3531 m_adj(m, hdrlen); 3532 tx->security = 0; 3533 tx->flags = htole32(flags); 3534 3535 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3536 &nsegs, BUS_DMA_NOWAIT); 3537 if (error != 0) { 3538 if (error != EFBIG) { 3539 device_printf(sc->sc_dev, 3540 "%s: can't map mbuf (error %d)\n", __func__, error); 3541 m_freem(m); 3542 return error; 3543 } 3544 /* Too many DMA segments, linearize mbuf. */ 3545 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3546 if (m1 == NULL) { 3547 device_printf(sc->sc_dev, 3548 "%s: could not defrag mbuf\n", __func__); 3549 m_freem(m); 3550 return ENOBUFS; 3551 } 3552 m = m1; 3553 3554 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3555 segs, &nsegs, BUS_DMA_NOWAIT); 3556 if (error != 0) { 3557 device_printf(sc->sc_dev, 3558 "%s: can't map mbuf (error %d)\n", __func__, error); 3559 m_freem(m); 3560 return error; 3561 } 3562 } 3563 3564 data->m = m; 3565 data->ni = ni; 3566 3567 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3568 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3569 3570 /* Fill TX descriptor. */ 3571 desc->nsegs = 1; 3572 if (m->m_len != 0) 3573 desc->nsegs += nsegs; 3574 /* First DMA segment is used by the TX command. */ 3575 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3576 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3577 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3578 /* Other DMA segments are for data payload. */ 3579 seg = &segs[0]; 3580 for (i = 1; i <= nsegs; i++) { 3581 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3582 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3583 seg->ds_len << 4); 3584 seg++; 3585 } 3586 3587 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3588 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3589 BUS_DMASYNC_PREWRITE); 3590 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3591 BUS_DMASYNC_PREWRITE); 3592 3593 /* Update TX scheduler. */ 3594 if (ring->qid >= sc->firstaggqueue) 3595 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3596 3597 /* Kick TX ring. */ 3598 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3599 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3600 3601 /* Mark TX ring as full if we reach a certain threshold. */ 3602 if (++ring->queued > IWN_TX_RING_HIMARK) 3603 sc->qfullmsk |= 1 << ring->qid; 3604 3605 return 0; 3606} 3607 3608static int 3609iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 3610 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3611{ 3612 struct iwn_ops *ops = &sc->ops; 3613 struct ifnet *ifp = sc->sc_ifp; 3614 struct ieee80211vap *vap = ni->ni_vap; 3615 struct ieee80211com *ic = ifp->if_l2com; 3616 struct iwn_tx_cmd *cmd; 3617 struct iwn_cmd_data *tx; 3618 struct ieee80211_frame *wh; 3619 struct iwn_tx_ring *ring; 3620 struct iwn_tx_desc *desc; 3621 struct iwn_tx_data *data; 3622 struct mbuf *m1; 3623 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 3624 uint32_t flags; 3625 u_int hdrlen; 3626 int ac, totlen, error, pad, nsegs = 0, i, rate; 3627 uint8_t ridx, type, txant; 3628 3629 IWN_LOCK_ASSERT(sc); 3630 3631 wh = mtod(m, struct ieee80211_frame *); 3632 hdrlen = ieee80211_anyhdrsize(wh); 3633 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3634 3635 ac = params->ibp_pri & 3; 3636 3637 ring = &sc->txq[ac]; 3638 desc = &ring->desc[ring->cur]; 3639 data = &ring->data[ring->cur]; 3640 3641 /* Choose a TX rate index. */ 3642 rate = params->ibp_rate0; 3643 ridx = ic->ic_rt->rateCodeToIndex[rate]; 3644 if (ridx == (uint8_t)-1) { 3645 /* XXX fall back to mcast/mgmt rate? */ 3646 m_freem(m); 3647 return EINVAL; 3648 } 3649 3650 totlen = m->m_pkthdr.len; 3651 3652 /* Prepare TX firmware command. */ 3653 cmd = &ring->cmd[ring->cur]; 3654 cmd->code = IWN_CMD_TX_DATA; 3655 cmd->flags = 0; 3656 cmd->qid = ring->qid; 3657 cmd->idx = ring->cur; 3658 3659 tx = (struct iwn_cmd_data *)cmd->data; 3660 /* NB: No need to clear tx, all fields are reinitialized here. */ 3661 tx->scratch = 0; /* clear "scratch" area */ 3662 3663 flags = 0; 3664 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 3665 flags |= IWN_TX_NEED_ACK; 3666 if (params->ibp_flags & IEEE80211_BPF_RTS) { 3667 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3668 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3669 flags &= ~IWN_TX_NEED_RTS; 3670 flags |= IWN_TX_NEED_PROTECTION; 3671 } else 3672 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 3673 } 3674 if (params->ibp_flags & IEEE80211_BPF_CTS) { 3675 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3676 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3677 flags &= ~IWN_TX_NEED_CTS; 3678 flags |= IWN_TX_NEED_PROTECTION; 3679 } else 3680 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 3681 } 3682 if (type == IEEE80211_FC0_TYPE_MGT) { 3683 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3684 3685 /* Tell HW to set timestamp in probe responses. */ 3686 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3687 flags |= IWN_TX_INSERT_TSTAMP; 3688 3689 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3690 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3691 tx->timeout = htole16(3); 3692 else 3693 tx->timeout = htole16(2); 3694 } else 3695 tx->timeout = htole16(0); 3696 3697 if (hdrlen & 3) { 3698 /* First segment length must be a multiple of 4. */ 3699 flags |= IWN_TX_NEED_PADDING; 3700 pad = 4 - (hdrlen & 3); 3701 } else 3702 pad = 0; 3703 3704 if (ieee80211_radiotap_active_vap(vap)) { 3705 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3706 3707 tap->wt_flags = 0; 3708 tap->wt_rate = rate; 3709 3710 ieee80211_radiotap_tx(vap, m); 3711 } 3712 3713 tx->len = htole16(totlen); 3714 tx->tid = 0; 3715 tx->id = sc->broadcast_id; 3716 tx->rts_ntries = params->ibp_try1; 3717 tx->data_ntries = params->ibp_try0; 3718 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3719 tx->rate = htole32(rate2plcp(rate)); 3720 if (ridx < IWN_RIDX_OFDM6 && 3721 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 3722 tx->rate |= htole32(IWN_RFLAG_CCK); 3723 /* Group or management frame. */ 3724 tx->linkq = 0; 3725 txant = IWN_LSB(sc->txchainmask); 3726 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 3727 /* Set physical address of "scratch area". */ 3728 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3729 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3730 3731 /* Copy 802.11 header in TX command. */ 3732 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3733 3734 /* Trim 802.11 header. */ 3735 m_adj(m, hdrlen); 3736 tx->security = 0; 3737 tx->flags = htole32(flags); 3738 3739 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 3740 &nsegs, BUS_DMA_NOWAIT); 3741 if (error != 0) { 3742 if (error != EFBIG) { 3743 device_printf(sc->sc_dev, 3744 "%s: can't map mbuf (error %d)\n", __func__, error); 3745 m_freem(m); 3746 return error; 3747 } 3748 /* Too many DMA segments, linearize mbuf. */ 3749 m1 = m_collapse(m, M_DONTWAIT, IWN_MAX_SCATTER); 3750 if (m1 == NULL) { 3751 device_printf(sc->sc_dev, 3752 "%s: could not defrag mbuf\n", __func__); 3753 m_freem(m); 3754 return ENOBUFS; 3755 } 3756 m = m1; 3757 3758 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3759 segs, &nsegs, BUS_DMA_NOWAIT); 3760 if (error != 0) { 3761 device_printf(sc->sc_dev, 3762 "%s: can't map mbuf (error %d)\n", __func__, error); 3763 m_freem(m); 3764 return error; 3765 } 3766 } 3767 3768 data->m = m; 3769 data->ni = ni; 3770 3771 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 3772 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 3773 3774 /* Fill TX descriptor. */ 3775 desc->nsegs = 1; 3776 if (m->m_len != 0) 3777 desc->nsegs += nsegs; 3778 /* First DMA segment is used by the TX command. */ 3779 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3780 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3781 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3782 /* Other DMA segments are for data payload. */ 3783 seg = &segs[0]; 3784 for (i = 1; i <= nsegs; i++) { 3785 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3786 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3787 seg->ds_len << 4); 3788 seg++; 3789 } 3790 3791 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 3792 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 3793 BUS_DMASYNC_PREWRITE); 3794 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3795 BUS_DMASYNC_PREWRITE); 3796 3797 /* Update TX scheduler. */ 3798 if (ring->qid >= sc->firstaggqueue) 3799 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3800 3801 /* Kick TX ring. */ 3802 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3803 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3804 3805 /* Mark TX ring as full if we reach a certain threshold. */ 3806 if (++ring->queued > IWN_TX_RING_HIMARK) 3807 sc->qfullmsk |= 1 << ring->qid; 3808 3809 return 0; 3810} 3811 3812static int 3813iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3814 const struct ieee80211_bpf_params *params) 3815{ 3816 struct ieee80211com *ic = ni->ni_ic; 3817 struct ifnet *ifp = ic->ic_ifp; 3818 struct iwn_softc *sc = ifp->if_softc; 3819 int error = 0; 3820 3821 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3822 ieee80211_free_node(ni); 3823 m_freem(m); 3824 return ENETDOWN; 3825 } 3826 3827 IWN_LOCK(sc); 3828 if (params == NULL) { 3829 /* 3830 * Legacy path; interpret frame contents to decide 3831 * precisely how to send the frame. 3832 */ 3833 error = iwn_tx_data(sc, m, ni); 3834 } else { 3835 /* 3836 * Caller supplied explicit parameters to use in 3837 * sending the frame. 3838 */ 3839 error = iwn_tx_data_raw(sc, m, ni, params); 3840 } 3841 if (error != 0) { 3842 /* NB: m is reclaimed on tx failure */ 3843 ieee80211_free_node(ni); 3844 ifp->if_oerrors++; 3845 } 3846 sc->sc_tx_timer = 5; 3847 3848 IWN_UNLOCK(sc); 3849 return error; 3850} 3851 3852static void 3853iwn_start(struct ifnet *ifp) 3854{ 3855 struct iwn_softc *sc = ifp->if_softc; 3856 3857 IWN_LOCK(sc); 3858 iwn_start_locked(ifp); 3859 IWN_UNLOCK(sc); 3860} 3861 3862static void 3863iwn_start_locked(struct ifnet *ifp) 3864{ 3865 struct iwn_softc *sc = ifp->if_softc; 3866 struct ieee80211_node *ni; 3867 struct mbuf *m; 3868 3869 IWN_LOCK_ASSERT(sc); 3870 3871 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 3872 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3873 return; 3874 3875 for (;;) { 3876 if (sc->qfullmsk != 0) { 3877 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3878 break; 3879 } 3880 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 3881 if (m == NULL) 3882 break; 3883 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3884 if (iwn_tx_data(sc, m, ni) != 0) { 3885 ieee80211_free_node(ni); 3886 ifp->if_oerrors++; 3887 continue; 3888 } 3889 sc->sc_tx_timer = 5; 3890 } 3891} 3892 3893static void 3894iwn_watchdog(void *arg) 3895{ 3896 struct iwn_softc *sc = arg; 3897 struct ifnet *ifp = sc->sc_ifp; 3898 struct ieee80211com *ic = ifp->if_l2com; 3899 3900 IWN_LOCK_ASSERT(sc); 3901 3902 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 3903 3904 if (sc->sc_tx_timer > 0) { 3905 if (--sc->sc_tx_timer == 0) { 3906 if_printf(ifp, "device timeout\n"); 3907 ieee80211_runtask(ic, &sc->sc_reinit_task); 3908 return; 3909 } 3910 } 3911 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 3912} 3913 3914static int 3915iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3916{ 3917 struct iwn_softc *sc = ifp->if_softc; 3918 struct ieee80211com *ic = ifp->if_l2com; 3919 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3920 struct ifreq *ifr = (struct ifreq *) data; 3921 int error = 0, startall = 0, stop = 0; 3922 3923 switch (cmd) { 3924 case SIOCGIFADDR: 3925 error = ether_ioctl(ifp, cmd, data); 3926 break; 3927 case SIOCSIFFLAGS: 3928 IWN_LOCK(sc); 3929 if (ifp->if_flags & IFF_UP) { 3930 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3931 iwn_init_locked(sc); 3932 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 3933 startall = 1; 3934 else 3935 stop = 1; 3936 } 3937 } else { 3938 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3939 iwn_stop_locked(sc); 3940 } 3941 IWN_UNLOCK(sc); 3942 if (startall) 3943 ieee80211_start_all(ic); 3944 else if (vap != NULL && stop) 3945 ieee80211_stop(vap); 3946 break; 3947 case SIOCGIFMEDIA: 3948 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 3949 break; 3950 default: 3951 error = EINVAL; 3952 break; 3953 } 3954 return error; 3955} 3956 3957/* 3958 * Send a command to the firmware. 3959 */ 3960static int 3961iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3962{ 3963 struct iwn_tx_ring *ring = &sc->txq[4]; 3964 struct iwn_tx_desc *desc; 3965 struct iwn_tx_data *data; 3966 struct iwn_tx_cmd *cmd; 3967 struct mbuf *m; 3968 bus_addr_t paddr; 3969 int totlen, error; 3970 3971 if (async == 0) 3972 IWN_LOCK_ASSERT(sc); 3973 3974 desc = &ring->desc[ring->cur]; 3975 data = &ring->data[ring->cur]; 3976 totlen = 4 + size; 3977 3978 if (size > sizeof cmd->data) { 3979 /* Command is too large to fit in a descriptor. */ 3980 if (totlen > MCLBYTES) 3981 return EINVAL; 3982 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 3983 if (m == NULL) 3984 return ENOMEM; 3985 cmd = mtod(m, struct iwn_tx_cmd *); 3986 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 3987 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3988 if (error != 0) { 3989 m_freem(m); 3990 return error; 3991 } 3992 data->m = m; 3993 } else { 3994 cmd = &ring->cmd[ring->cur]; 3995 paddr = data->cmd_paddr; 3996 } 3997 3998 cmd->code = code; 3999 cmd->flags = 0; 4000 cmd->qid = ring->qid; 4001 cmd->idx = ring->cur; 4002 memcpy(cmd->data, buf, size); 4003 4004 desc->nsegs = 1; 4005 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 4006 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 4007 4008 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 4009 __func__, iwn_intr_str(cmd->code), cmd->code, 4010 cmd->flags, cmd->qid, cmd->idx); 4011 4012 if (size > sizeof cmd->data) { 4013 bus_dmamap_sync(ring->data_dmat, data->map, 4014 BUS_DMASYNC_PREWRITE); 4015 } else { 4016 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4017 BUS_DMASYNC_PREWRITE); 4018 } 4019 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4020 BUS_DMASYNC_PREWRITE); 4021 4022 /* Kick command ring. */ 4023 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4024 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4025 4026 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 4027} 4028 4029static int 4030iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 4031{ 4032 struct iwn4965_node_info hnode; 4033 caddr_t src, dst; 4034 4035 /* 4036 * We use the node structure for 5000 Series internally (it is 4037 * a superset of the one for 4965AGN). We thus copy the common 4038 * fields before sending the command. 4039 */ 4040 src = (caddr_t)node; 4041 dst = (caddr_t)&hnode; 4042 memcpy(dst, src, 48); 4043 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 4044 memcpy(dst + 48, src + 72, 20); 4045 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 4046} 4047 4048static int 4049iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 4050{ 4051 /* Direct mapping. */ 4052 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 4053} 4054 4055static int 4056iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 4057{ 4058#define RV(v) ((v) & IEEE80211_RATE_VAL) 4059 struct iwn_node *wn = (void *)ni; 4060 struct ieee80211_rateset *rs = &ni->ni_rates; 4061 struct iwn_cmd_link_quality linkq; 4062 uint8_t txant; 4063 int i, rate, txrate; 4064 4065 /* Use the first valid TX antenna. */ 4066 txant = IWN_LSB(sc->txchainmask); 4067 4068 memset(&linkq, 0, sizeof linkq); 4069 linkq.id = wn->id; 4070 linkq.antmsk_1stream = txant; 4071 linkq.antmsk_2stream = IWN_ANT_AB; 4072 linkq.ampdu_max = 64; 4073 linkq.ampdu_threshold = 3; 4074 linkq.ampdu_limit = htole16(4000); /* 4ms */ 4075 4076 /* Start at highest available bit-rate. */ 4077 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) 4078 txrate = ni->ni_htrates.rs_nrates - 1; 4079 else 4080 txrate = rs->rs_nrates - 1; 4081 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 4082 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) 4083 rate = IEEE80211_RATE_MCS | txrate; 4084 else 4085 rate = RV(rs->rs_rates[txrate]); 4086 linkq.retry[i] = wn->ridx[rate]; 4087 4088 if ((le32toh(wn->ridx[rate]) & IWN_RFLAG_MCS) && 4089 RV(le32toh(wn->ridx[rate])) > 7) 4090 linkq.mimo = i + 1; 4091 4092 /* Next retry at immediate lower bit-rate. */ 4093 if (txrate > 0) 4094 txrate--; 4095 } 4096 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 4097#undef RV 4098} 4099 4100/* 4101 * Broadcast node is used to send group-addressed and management frames. 4102 */ 4103static int 4104iwn_add_broadcast_node(struct iwn_softc *sc, int async) 4105{ 4106 struct iwn_ops *ops = &sc->ops; 4107 struct ifnet *ifp = sc->sc_ifp; 4108 struct ieee80211com *ic = ifp->if_l2com; 4109 struct iwn_node_info node; 4110 struct iwn_cmd_link_quality linkq; 4111 uint8_t txant; 4112 int i, error; 4113 4114 memset(&node, 0, sizeof node); 4115 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 4116 node.id = sc->broadcast_id; 4117 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 4118 if ((error = ops->add_node(sc, &node, async)) != 0) 4119 return error; 4120 4121 /* Use the first valid TX antenna. */ 4122 txant = IWN_LSB(sc->txchainmask); 4123 4124 memset(&linkq, 0, sizeof linkq); 4125 linkq.id = sc->broadcast_id; 4126 linkq.antmsk_1stream = txant; 4127 linkq.antmsk_2stream = IWN_ANT_AB; 4128 linkq.ampdu_max = 64; 4129 linkq.ampdu_threshold = 3; 4130 linkq.ampdu_limit = htole16(4000); /* 4ms */ 4131 4132 /* Use lowest mandatory bit-rate. */ 4133 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 4134 linkq.retry[0] = htole32(0xd); 4135 else 4136 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 4137 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 4138 /* Use same bit-rate for all TX retries. */ 4139 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 4140 linkq.retry[i] = linkq.retry[0]; 4141 } 4142 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 4143} 4144 4145static int 4146iwn_updateedca(struct ieee80211com *ic) 4147{ 4148#define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 4149 struct iwn_softc *sc = ic->ic_ifp->if_softc; 4150 struct iwn_edca_params cmd; 4151 int aci; 4152 4153 memset(&cmd, 0, sizeof cmd); 4154 cmd.flags = htole32(IWN_EDCA_UPDATE); 4155 for (aci = 0; aci < WME_NUM_AC; aci++) { 4156 const struct wmeParams *ac = 4157 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 4158 cmd.ac[aci].aifsn = ac->wmep_aifsn; 4159 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 4160 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 4161 cmd.ac[aci].txoplimit = 4162 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 4163 } 4164 IEEE80211_UNLOCK(ic); 4165 IWN_LOCK(sc); 4166 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4167 IWN_UNLOCK(sc); 4168 IEEE80211_LOCK(ic); 4169 return 0; 4170#undef IWN_EXP2 4171} 4172 4173static void 4174iwn_update_mcast(struct ifnet *ifp) 4175{ 4176 /* Ignore */ 4177} 4178 4179static void 4180iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 4181{ 4182 struct iwn_cmd_led led; 4183 4184 /* Clear microcode LED ownership. */ 4185 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 4186 4187 led.which = which; 4188 led.unit = htole32(10000); /* on/off in unit of 100ms */ 4189 led.off = off; 4190 led.on = on; 4191 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 4192} 4193 4194/* 4195 * Set the critical temperature at which the firmware will stop the radio 4196 * and notify us. 4197 */ 4198static int 4199iwn_set_critical_temp(struct iwn_softc *sc) 4200{ 4201 struct iwn_critical_temp crit; 4202 int32_t temp; 4203 4204 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 4205 4206 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 4207 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 4208 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 4209 temp = IWN_CTOK(110); 4210 else 4211 temp = 110; 4212 memset(&crit, 0, sizeof crit); 4213 crit.tempR = htole32(temp); 4214 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 4215 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 4216} 4217 4218static int 4219iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 4220{ 4221 struct iwn_cmd_timing cmd; 4222 uint64_t val, mod; 4223 4224 memset(&cmd, 0, sizeof cmd); 4225 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 4226 cmd.bintval = htole16(ni->ni_intval); 4227 cmd.lintval = htole16(10); 4228 4229 /* Compute remaining time until next beacon. */ 4230 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 4231 mod = le64toh(cmd.tstamp) % val; 4232 cmd.binitval = htole32((uint32_t)(val - mod)); 4233 4234 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 4235 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 4236 4237 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 4238} 4239 4240static void 4241iwn4965_power_calibration(struct iwn_softc *sc, int temp) 4242{ 4243 struct ifnet *ifp = sc->sc_ifp; 4244 struct ieee80211com *ic = ifp->if_l2com; 4245 4246 /* Adjust TX power if need be (delta >= 3 degC). */ 4247 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 4248 __func__, sc->temp, temp); 4249 if (abs(temp - sc->temp) >= 3) { 4250 /* Record temperature of last calibration. */ 4251 sc->temp = temp; 4252 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 4253 } 4254} 4255 4256/* 4257 * Set TX power for current channel (each rate has its own power settings). 4258 * This function takes into account the regulatory information from EEPROM, 4259 * the current temperature and the current voltage. 4260 */ 4261static int 4262iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4263 int async) 4264{ 4265/* Fixed-point arithmetic division using a n-bit fractional part. */ 4266#define fdivround(a, b, n) \ 4267 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 4268/* Linear interpolation. */ 4269#define interpolate(x, x1, y1, x2, y2, n) \ 4270 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 4271 4272 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 4273 struct iwn_ucode_info *uc = &sc->ucode_info; 4274 struct iwn4965_cmd_txpower cmd; 4275 struct iwn4965_eeprom_chan_samples *chans; 4276 const uint8_t *rf_gain, *dsp_gain; 4277 int32_t vdiff, tdiff; 4278 int i, c, grp, maxpwr; 4279 uint8_t chan; 4280 4281 /* Retrieve current channel from last RXON. */ 4282 chan = sc->rxon.chan; 4283 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 4284 chan); 4285 4286 memset(&cmd, 0, sizeof cmd); 4287 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 4288 cmd.chan = chan; 4289 4290 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 4291 maxpwr = sc->maxpwr5GHz; 4292 rf_gain = iwn4965_rf_gain_5ghz; 4293 dsp_gain = iwn4965_dsp_gain_5ghz; 4294 } else { 4295 maxpwr = sc->maxpwr2GHz; 4296 rf_gain = iwn4965_rf_gain_2ghz; 4297 dsp_gain = iwn4965_dsp_gain_2ghz; 4298 } 4299 4300 /* Compute voltage compensation. */ 4301 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 4302 if (vdiff > 0) 4303 vdiff *= 2; 4304 if (abs(vdiff) > 2) 4305 vdiff = 0; 4306 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4307 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 4308 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 4309 4310 /* Get channel attenuation group. */ 4311 if (chan <= 20) /* 1-20 */ 4312 grp = 4; 4313 else if (chan <= 43) /* 34-43 */ 4314 grp = 0; 4315 else if (chan <= 70) /* 44-70 */ 4316 grp = 1; 4317 else if (chan <= 124) /* 71-124 */ 4318 grp = 2; 4319 else /* 125-200 */ 4320 grp = 3; 4321 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4322 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 4323 4324 /* Get channel sub-band. */ 4325 for (i = 0; i < IWN_NBANDS; i++) 4326 if (sc->bands[i].lo != 0 && 4327 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 4328 break; 4329 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 4330 return EINVAL; 4331 chans = sc->bands[i].chans; 4332 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4333 "%s: chan %d sub-band=%d\n", __func__, chan, i); 4334 4335 for (c = 0; c < 2; c++) { 4336 uint8_t power, gain, temp; 4337 int maxchpwr, pwr, ridx, idx; 4338 4339 power = interpolate(chan, 4340 chans[0].num, chans[0].samples[c][1].power, 4341 chans[1].num, chans[1].samples[c][1].power, 1); 4342 gain = interpolate(chan, 4343 chans[0].num, chans[0].samples[c][1].gain, 4344 chans[1].num, chans[1].samples[c][1].gain, 1); 4345 temp = interpolate(chan, 4346 chans[0].num, chans[0].samples[c][1].temp, 4347 chans[1].num, chans[1].samples[c][1].temp, 1); 4348 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4349 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 4350 __func__, c, power, gain, temp); 4351 4352 /* Compute temperature compensation. */ 4353 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 4354 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4355 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 4356 __func__, tdiff, sc->temp, temp); 4357 4358 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 4359 /* Convert dBm to half-dBm. */ 4360 maxchpwr = sc->maxpwr[chan] * 2; 4361 if ((ridx / 8) & 1) 4362 maxchpwr -= 6; /* MIMO 2T: -3dB */ 4363 4364 pwr = maxpwr; 4365 4366 /* Adjust TX power based on rate. */ 4367 if ((ridx % 8) == 5) 4368 pwr -= 15; /* OFDM48: -7.5dB */ 4369 else if ((ridx % 8) == 6) 4370 pwr -= 17; /* OFDM54: -8.5dB */ 4371 else if ((ridx % 8) == 7) 4372 pwr -= 20; /* OFDM60: -10dB */ 4373 else 4374 pwr -= 10; /* Others: -5dB */ 4375 4376 /* Do not exceed channel max TX power. */ 4377 if (pwr > maxchpwr) 4378 pwr = maxchpwr; 4379 4380 idx = gain - (pwr - power) - tdiff - vdiff; 4381 if ((ridx / 8) & 1) /* MIMO */ 4382 idx += (int32_t)le32toh(uc->atten[grp][c]); 4383 4384 if (cmd.band == 0) 4385 idx += 9; /* 5GHz */ 4386 if (ridx == IWN_RIDX_MAX) 4387 idx += 5; /* CCK */ 4388 4389 /* Make sure idx stays in a valid range. */ 4390 if (idx < 0) 4391 idx = 0; 4392 else if (idx > IWN4965_MAX_PWR_INDEX) 4393 idx = IWN4965_MAX_PWR_INDEX; 4394 4395 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4396 "%s: Tx chain %d, rate idx %d: power=%d\n", 4397 __func__, c, ridx, idx); 4398 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 4399 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 4400 } 4401 } 4402 4403 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 4404 "%s: set tx power for chan %d\n", __func__, chan); 4405 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 4406 4407#undef interpolate 4408#undef fdivround 4409} 4410 4411static int 4412iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 4413 int async) 4414{ 4415 struct iwn5000_cmd_txpower cmd; 4416 4417 /* 4418 * TX power calibration is handled automatically by the firmware 4419 * for 5000 Series. 4420 */ 4421 memset(&cmd, 0, sizeof cmd); 4422 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 4423 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 4424 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 4425 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 4426 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 4427} 4428 4429/* 4430 * Retrieve the maximum RSSI (in dBm) among receivers. 4431 */ 4432static int 4433iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4434{ 4435 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 4436 uint8_t mask, agc; 4437 int rssi; 4438 4439 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 4440 agc = (le16toh(phy->agc) >> 7) & 0x7f; 4441 4442 rssi = 0; 4443 if (mask & IWN_ANT_A) 4444 rssi = MAX(rssi, phy->rssi[0]); 4445 if (mask & IWN_ANT_B) 4446 rssi = MAX(rssi, phy->rssi[2]); 4447 if (mask & IWN_ANT_C) 4448 rssi = MAX(rssi, phy->rssi[4]); 4449 4450 DPRINTF(sc, IWN_DEBUG_RECV, 4451 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 4452 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 4453 rssi - agc - IWN_RSSI_TO_DBM); 4454 return rssi - agc - IWN_RSSI_TO_DBM; 4455} 4456 4457static int 4458iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 4459{ 4460 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 4461 uint8_t agc; 4462 int rssi; 4463 4464 agc = (le32toh(phy->agc) >> 9) & 0x7f; 4465 4466 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 4467 le16toh(phy->rssi[1]) & 0xff); 4468 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 4469 4470 DPRINTF(sc, IWN_DEBUG_RECV, 4471 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 4472 phy->rssi[0], phy->rssi[1], phy->rssi[2], 4473 rssi - agc - IWN_RSSI_TO_DBM); 4474 return rssi - agc - IWN_RSSI_TO_DBM; 4475} 4476 4477/* 4478 * Retrieve the average noise (in dBm) among receivers. 4479 */ 4480static int 4481iwn_get_noise(const struct iwn_rx_general_stats *stats) 4482{ 4483 int i, total, nbant, noise; 4484 4485 total = nbant = 0; 4486 for (i = 0; i < 3; i++) { 4487 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 4488 continue; 4489 total += noise; 4490 nbant++; 4491 } 4492 /* There should be at least one antenna but check anyway. */ 4493 return (nbant == 0) ? -127 : (total / nbant) - 107; 4494} 4495 4496/* 4497 * Compute temperature (in degC) from last received statistics. 4498 */ 4499static int 4500iwn4965_get_temperature(struct iwn_softc *sc) 4501{ 4502 struct iwn_ucode_info *uc = &sc->ucode_info; 4503 int32_t r1, r2, r3, r4, temp; 4504 4505 r1 = le32toh(uc->temp[0].chan20MHz); 4506 r2 = le32toh(uc->temp[1].chan20MHz); 4507 r3 = le32toh(uc->temp[2].chan20MHz); 4508 r4 = le32toh(sc->rawtemp); 4509 4510 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 4511 return 0; 4512 4513 /* Sign-extend 23-bit R4 value to 32-bit. */ 4514 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 4515 /* Compute temperature in Kelvin. */ 4516 temp = (259 * (r4 - r2)) / (r3 - r1); 4517 temp = (temp * 97) / 100 + 8; 4518 4519 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 4520 IWN_KTOC(temp)); 4521 return IWN_KTOC(temp); 4522} 4523 4524static int 4525iwn5000_get_temperature(struct iwn_softc *sc) 4526{ 4527 int32_t temp; 4528 4529 /* 4530 * Temperature is not used by the driver for 5000 Series because 4531 * TX power calibration is handled by firmware. 4532 */ 4533 temp = le32toh(sc->rawtemp); 4534 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4535 temp = (temp / -5) + sc->temp_off; 4536 temp = IWN_KTOC(temp); 4537 } 4538 return temp; 4539} 4540 4541/* 4542 * Initialize sensitivity calibration state machine. 4543 */ 4544static int 4545iwn_init_sensitivity(struct iwn_softc *sc) 4546{ 4547 struct iwn_ops *ops = &sc->ops; 4548 struct iwn_calib_state *calib = &sc->calib; 4549 uint32_t flags; 4550 int error; 4551 4552 /* Reset calibration state machine. */ 4553 memset(calib, 0, sizeof (*calib)); 4554 calib->state = IWN_CALIB_STATE_INIT; 4555 calib->cck_state = IWN_CCK_STATE_HIFA; 4556 /* Set initial correlation values. */ 4557 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4558 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4559 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4560 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4561 calib->cck_x4 = 125; 4562 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4563 calib->energy_cck = sc->limits->energy_cck; 4564 4565 /* Write initial sensitivity. */ 4566 if ((error = iwn_send_sensitivity(sc)) != 0) 4567 return error; 4568 4569 /* Write initial gains. */ 4570 if ((error = ops->init_gains(sc)) != 0) 4571 return error; 4572 4573 /* Request statistics at each beacon interval. */ 4574 flags = 0; 4575 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 4576 __func__); 4577 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4578} 4579 4580/* 4581 * Collect noise and RSSI statistics for the first 20 beacons received 4582 * after association and use them to determine connected antennas and 4583 * to set differential gains. 4584 */ 4585static void 4586iwn_collect_noise(struct iwn_softc *sc, 4587 const struct iwn_rx_general_stats *stats) 4588{ 4589 struct iwn_ops *ops = &sc->ops; 4590 struct iwn_calib_state *calib = &sc->calib; 4591 uint32_t val; 4592 int i; 4593 4594 /* Accumulate RSSI and noise for all 3 antennas. */ 4595 for (i = 0; i < 3; i++) { 4596 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 4597 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 4598 } 4599 /* NB: We update differential gains only once after 20 beacons. */ 4600 if (++calib->nbeacons < 20) 4601 return; 4602 4603 /* Determine highest average RSSI. */ 4604 val = MAX(calib->rssi[0], calib->rssi[1]); 4605 val = MAX(calib->rssi[2], val); 4606 4607 /* Determine which antennas are connected. */ 4608 sc->chainmask = sc->rxchainmask; 4609 for (i = 0; i < 3; i++) 4610 if (val - calib->rssi[i] > 15 * 20) 4611 sc->chainmask &= ~(1 << i); 4612 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4613 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 4614 __func__, sc->rxchainmask, sc->chainmask); 4615 4616 /* If none of the TX antennas are connected, keep at least one. */ 4617 if ((sc->chainmask & sc->txchainmask) == 0) 4618 sc->chainmask |= IWN_LSB(sc->txchainmask); 4619 4620 (void)ops->set_gains(sc); 4621 calib->state = IWN_CALIB_STATE_RUN; 4622 4623#ifdef notyet 4624 /* XXX Disable RX chains with no antennas connected. */ 4625 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4626 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4627#endif 4628 4629#if 0 4630 /* XXX: not yet */ 4631 /* Enable power-saving mode if requested by user. */ 4632 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4633 (void)iwn_set_pslevel(sc, 0, 3, 1); 4634#endif 4635} 4636 4637static int 4638iwn4965_init_gains(struct iwn_softc *sc) 4639{ 4640 struct iwn_phy_calib_gain cmd; 4641 4642 memset(&cmd, 0, sizeof cmd); 4643 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4644 /* Differential gains initially set to 0 for all 3 antennas. */ 4645 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4646 "%s: setting initial differential gains\n", __func__); 4647 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4648} 4649 4650static int 4651iwn5000_init_gains(struct iwn_softc *sc) 4652{ 4653 struct iwn_phy_calib cmd; 4654 4655 memset(&cmd, 0, sizeof cmd); 4656 cmd.code = sc->reset_noise_gain; 4657 cmd.ngroups = 1; 4658 cmd.isvalid = 1; 4659 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4660 "%s: setting initial differential gains\n", __func__); 4661 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4662} 4663 4664static int 4665iwn4965_set_gains(struct iwn_softc *sc) 4666{ 4667 struct iwn_calib_state *calib = &sc->calib; 4668 struct iwn_phy_calib_gain cmd; 4669 int i, delta, noise; 4670 4671 /* Get minimal noise among connected antennas. */ 4672 noise = INT_MAX; /* NB: There's at least one antenna. */ 4673 for (i = 0; i < 3; i++) 4674 if (sc->chainmask & (1 << i)) 4675 noise = MIN(calib->noise[i], noise); 4676 4677 memset(&cmd, 0, sizeof cmd); 4678 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4679 /* Set differential gains for connected antennas. */ 4680 for (i = 0; i < 3; i++) { 4681 if (sc->chainmask & (1 << i)) { 4682 /* Compute attenuation (in unit of 1.5dB). */ 4683 delta = (noise - (int32_t)calib->noise[i]) / 30; 4684 /* NB: delta <= 0 */ 4685 /* Limit to [-4.5dB,0]. */ 4686 cmd.gain[i] = MIN(abs(delta), 3); 4687 if (delta < 0) 4688 cmd.gain[i] |= 1 << 2; /* sign bit */ 4689 } 4690 } 4691 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4692 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4693 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 4694 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4695} 4696 4697static int 4698iwn5000_set_gains(struct iwn_softc *sc) 4699{ 4700 struct iwn_calib_state *calib = &sc->calib; 4701 struct iwn_phy_calib_gain cmd; 4702 int i, ant, div, delta; 4703 4704 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4705 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4706 4707 memset(&cmd, 0, sizeof cmd); 4708 cmd.code = sc->noise_gain; 4709 cmd.ngroups = 1; 4710 cmd.isvalid = 1; 4711 /* Get first available RX antenna as referential. */ 4712 ant = IWN_LSB(sc->rxchainmask); 4713 /* Set differential gains for other antennas. */ 4714 for (i = ant + 1; i < 3; i++) { 4715 if (sc->chainmask & (1 << i)) { 4716 /* The delta is relative to antenna "ant". */ 4717 delta = ((int32_t)calib->noise[ant] - 4718 (int32_t)calib->noise[i]) / div; 4719 /* Limit to [-4.5dB,+4.5dB]. */ 4720 cmd.gain[i - 1] = MIN(abs(delta), 3); 4721 if (delta < 0) 4722 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 4723 } 4724 } 4725 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4726 "setting differential gains Ant B/C: %x/%x (%x)\n", 4727 cmd.gain[0], cmd.gain[1], sc->chainmask); 4728 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4729} 4730 4731/* 4732 * Tune RF RX sensitivity based on the number of false alarms detected 4733 * during the last beacon period. 4734 */ 4735static void 4736iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4737{ 4738#define inc(val, inc, max) \ 4739 if ((val) < (max)) { \ 4740 if ((val) < (max) - (inc)) \ 4741 (val) += (inc); \ 4742 else \ 4743 (val) = (max); \ 4744 needs_update = 1; \ 4745 } 4746#define dec(val, dec, min) \ 4747 if ((val) > (min)) { \ 4748 if ((val) > (min) + (dec)) \ 4749 (val) -= (dec); \ 4750 else \ 4751 (val) = (min); \ 4752 needs_update = 1; \ 4753 } 4754 4755 const struct iwn_sensitivity_limits *limits = sc->limits; 4756 struct iwn_calib_state *calib = &sc->calib; 4757 uint32_t val, rxena, fa; 4758 uint32_t energy[3], energy_min; 4759 uint8_t noise[3], noise_ref; 4760 int i, needs_update = 0; 4761 4762 /* Check that we've been enabled long enough. */ 4763 if ((rxena = le32toh(stats->general.load)) == 0) 4764 return; 4765 4766 /* Compute number of false alarms since last call for OFDM. */ 4767 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4768 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 4769 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4770 4771 /* Save counters values for next call. */ 4772 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp); 4773 calib->fa_ofdm = le32toh(stats->ofdm.fa); 4774 4775 if (fa > 50 * rxena) { 4776 /* High false alarm count, decrease sensitivity. */ 4777 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4778 "%s: OFDM high false alarm count: %u\n", __func__, fa); 4779 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4780 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4781 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4782 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4783 4784 } else if (fa < 5 * rxena) { 4785 /* Low false alarm count, increase sensitivity. */ 4786 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4787 "%s: OFDM low false alarm count: %u\n", __func__, fa); 4788 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4789 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4790 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4791 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4792 } 4793 4794 /* Compute maximum noise among 3 receivers. */ 4795 for (i = 0; i < 3; i++) 4796 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 4797 val = MAX(noise[0], noise[1]); 4798 val = MAX(noise[2], val); 4799 /* Insert it into our samples table. */ 4800 calib->noise_samples[calib->cur_noise_sample] = val; 4801 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4802 4803 /* Compute maximum noise among last 20 samples. */ 4804 noise_ref = calib->noise_samples[0]; 4805 for (i = 1; i < 20; i++) 4806 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4807 4808 /* Compute maximum energy among 3 receivers. */ 4809 for (i = 0; i < 3; i++) 4810 energy[i] = le32toh(stats->general.energy[i]); 4811 val = MIN(energy[0], energy[1]); 4812 val = MIN(energy[2], val); 4813 /* Insert it into our samples table. */ 4814 calib->energy_samples[calib->cur_energy_sample] = val; 4815 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4816 4817 /* Compute minimum energy among last 10 samples. */ 4818 energy_min = calib->energy_samples[0]; 4819 for (i = 1; i < 10; i++) 4820 energy_min = MAX(energy_min, calib->energy_samples[i]); 4821 energy_min += 6; 4822 4823 /* Compute number of false alarms since last call for CCK. */ 4824 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4825 fa += le32toh(stats->cck.fa) - calib->fa_cck; 4826 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4827 4828 /* Save counters values for next call. */ 4829 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp); 4830 calib->fa_cck = le32toh(stats->cck.fa); 4831 4832 if (fa > 50 * rxena) { 4833 /* High false alarm count, decrease sensitivity. */ 4834 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4835 "%s: CCK high false alarm count: %u\n", __func__, fa); 4836 calib->cck_state = IWN_CCK_STATE_HIFA; 4837 calib->low_fa = 0; 4838 4839 if (calib->cck_x4 > 160) { 4840 calib->noise_ref = noise_ref; 4841 if (calib->energy_cck > 2) 4842 dec(calib->energy_cck, 2, energy_min); 4843 } 4844 if (calib->cck_x4 < 160) { 4845 calib->cck_x4 = 161; 4846 needs_update = 1; 4847 } else 4848 inc(calib->cck_x4, 3, limits->max_cck_x4); 4849 4850 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4851 4852 } else if (fa < 5 * rxena) { 4853 /* Low false alarm count, increase sensitivity. */ 4854 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4855 "%s: CCK low false alarm count: %u\n", __func__, fa); 4856 calib->cck_state = IWN_CCK_STATE_LOFA; 4857 calib->low_fa++; 4858 4859 if (calib->cck_state != IWN_CCK_STATE_INIT && 4860 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4861 calib->low_fa > 100)) { 4862 inc(calib->energy_cck, 2, limits->min_energy_cck); 4863 dec(calib->cck_x4, 3, limits->min_cck_x4); 4864 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4865 } 4866 } else { 4867 /* Not worth to increase or decrease sensitivity. */ 4868 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4869 "%s: CCK normal false alarm count: %u\n", __func__, fa); 4870 calib->low_fa = 0; 4871 calib->noise_ref = noise_ref; 4872 4873 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4874 /* Previous interval had many false alarms. */ 4875 dec(calib->energy_cck, 8, energy_min); 4876 } 4877 calib->cck_state = IWN_CCK_STATE_INIT; 4878 } 4879 4880 if (needs_update) 4881 (void)iwn_send_sensitivity(sc); 4882#undef dec 4883#undef inc 4884} 4885 4886static int 4887iwn_send_sensitivity(struct iwn_softc *sc) 4888{ 4889 struct iwn_calib_state *calib = &sc->calib; 4890 struct iwn_enhanced_sensitivity_cmd cmd; 4891 int len; 4892 4893 memset(&cmd, 0, sizeof cmd); 4894 len = sizeof (struct iwn_sensitivity_cmd); 4895 cmd.which = IWN_SENSITIVITY_WORKTBL; 4896 /* OFDM modulation. */ 4897 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4898 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4899 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4900 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4901 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4902 cmd.energy_ofdm_th = htole16(62); 4903 /* CCK modulation. */ 4904 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4905 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4906 cmd.energy_cck = htole16(calib->energy_cck); 4907 /* Barker modulation: use default values. */ 4908 cmd.corr_barker = htole16(190); 4909 cmd.corr_barker_mrc = htole16(390); 4910 4911 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 4912 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 4913 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 4914 calib->ofdm_mrc_x4, calib->cck_x4, 4915 calib->cck_mrc_x4, calib->energy_cck); 4916 4917 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4918 goto send; 4919 /* Enhanced sensitivity settings. */ 4920 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4921 cmd.ofdm_det_slope_mrc = htole16(668); 4922 cmd.ofdm_det_icept_mrc = htole16(4); 4923 cmd.ofdm_det_slope = htole16(486); 4924 cmd.ofdm_det_icept = htole16(37); 4925 cmd.cck_det_slope_mrc = htole16(853); 4926 cmd.cck_det_icept_mrc = htole16(4); 4927 cmd.cck_det_slope = htole16(476); 4928 cmd.cck_det_icept = htole16(99); 4929send: 4930 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4931} 4932 4933/* 4934 * Set STA mode power saving level (between 0 and 5). 4935 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4936 */ 4937static int 4938iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4939{ 4940 struct iwn_pmgt_cmd cmd; 4941 const struct iwn_pmgt *pmgt; 4942 uint32_t max, skip_dtim; 4943 uint32_t reg; 4944 int i; 4945 4946 /* Select which PS parameters to use. */ 4947 if (dtim <= 2) 4948 pmgt = &iwn_pmgt[0][level]; 4949 else if (dtim <= 10) 4950 pmgt = &iwn_pmgt[1][level]; 4951 else 4952 pmgt = &iwn_pmgt[2][level]; 4953 4954 memset(&cmd, 0, sizeof cmd); 4955 if (level != 0) /* not CAM */ 4956 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4957 if (level == 5) 4958 cmd.flags |= htole16(IWN_PS_FAST_PD); 4959 /* Retrieve PCIe Active State Power Management (ASPM). */ 4960 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 4961 if (!(reg & 0x1)) /* L0s Entry disabled. */ 4962 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4963 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4964 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4965 4966 if (dtim == 0) { 4967 dtim = 1; 4968 skip_dtim = 0; 4969 } else 4970 skip_dtim = pmgt->skip_dtim; 4971 if (skip_dtim != 0) { 4972 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4973 max = pmgt->intval[4]; 4974 if (max == (uint32_t)-1) 4975 max = dtim * (skip_dtim + 1); 4976 else if (max > dtim) 4977 max = (max / dtim) * dtim; 4978 } else 4979 max = dtim; 4980 for (i = 0; i < 5; i++) 4981 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4982 4983 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 4984 level); 4985 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4986} 4987 4988static int 4989iwn_send_btcoex(struct iwn_softc *sc) 4990{ 4991 struct iwn_bluetooth cmd; 4992 4993 memset(&cmd, 0, sizeof cmd); 4994 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4995 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 4996 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 4997 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 4998 __func__); 4999 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 5000} 5001 5002static int 5003iwn_send_advanced_btcoex(struct iwn_softc *sc) 5004{ 5005 static const uint32_t btcoex_3wire[12] = { 5006 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 5007 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 5008 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 5009 }; 5010 struct iwn6000_btcoex_config btconfig; 5011 struct iwn_btcoex_priotable btprio; 5012 struct iwn_btcoex_prot btprot; 5013 int error, i; 5014 5015 memset(&btconfig, 0, sizeof btconfig); 5016 btconfig.flags = 145; 5017 btconfig.max_kill = 5; 5018 btconfig.bt3_t7_timer = 1; 5019 btconfig.kill_ack = htole32(0xffff0000); 5020 btconfig.kill_cts = htole32(0xffff0000); 5021 btconfig.sample_time = 2; 5022 btconfig.bt3_t2_timer = 0xc; 5023 for (i = 0; i < 12; i++) 5024 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 5025 btconfig.valid = htole16(0xff); 5026 btconfig.prio_boost = 0xf0; 5027 DPRINTF(sc, IWN_DEBUG_RESET, 5028 "%s: configuring advanced bluetooth coexistence\n", __func__); 5029 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, sizeof(btconfig), 1); 5030 if (error != 0) 5031 return error; 5032 5033 memset(&btprio, 0, sizeof btprio); 5034 btprio.calib_init1 = 0x6; 5035 btprio.calib_init2 = 0x7; 5036 btprio.calib_periodic_low1 = 0x2; 5037 btprio.calib_periodic_low2 = 0x3; 5038 btprio.calib_periodic_high1 = 0x4; 5039 btprio.calib_periodic_high2 = 0x5; 5040 btprio.dtim = 0x6; 5041 btprio.scan52 = 0x8; 5042 btprio.scan24 = 0xa; 5043 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 5044 1); 5045 if (error != 0) 5046 return error; 5047 5048 /* Force BT state machine change. */ 5049 memset(&btprot, 0, sizeof btprio); 5050 btprot.open = 1; 5051 btprot.type = 1; 5052 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 5053 if (error != 0) 5054 return error; 5055 btprot.open = 0; 5056 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 5057} 5058 5059static int 5060iwn5000_runtime_calib(struct iwn_softc *sc) 5061{ 5062 struct iwn5000_calib_config cmd; 5063 5064 memset(&cmd, 0, sizeof cmd); 5065 cmd.ucode.once.enable = 0xffffffff; 5066 cmd.ucode.once.start = IWN5000_CALIB_DC; 5067 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5068 "%s: configuring runtime calibration\n", __func__); 5069 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 5070} 5071 5072static int 5073iwn_config(struct iwn_softc *sc) 5074{ 5075 struct iwn_ops *ops = &sc->ops; 5076 struct ifnet *ifp = sc->sc_ifp; 5077 struct ieee80211com *ic = ifp->if_l2com; 5078 uint32_t txmask; 5079 uint16_t rxchain; 5080 int error; 5081 5082 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 5083 /* Set radio temperature sensor offset. */ 5084 error = iwn5000_temp_offset_calib(sc); 5085 if (error != 0) { 5086 device_printf(sc->sc_dev, 5087 "%s: could not set temperature offset\n", __func__); 5088 return error; 5089 } 5090 } 5091 5092 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5093 /* Configure runtime DC calibration. */ 5094 error = iwn5000_runtime_calib(sc); 5095 if (error != 0) { 5096 device_printf(sc->sc_dev, 5097 "%s: could not configure runtime calibration\n", 5098 __func__); 5099 return error; 5100 } 5101 } 5102 5103 /* Configure valid TX chains for >=5000 Series. */ 5104 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 5105 txmask = htole32(sc->txchainmask); 5106 DPRINTF(sc, IWN_DEBUG_RESET, 5107 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 5108 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 5109 sizeof txmask, 0); 5110 if (error != 0) { 5111 device_printf(sc->sc_dev, 5112 "%s: could not configure valid TX chains, " 5113 "error %d\n", __func__, error); 5114 return error; 5115 } 5116 } 5117 5118 /* Configure bluetooth coexistence. */ 5119 if (sc->sc_flags & IWN_FLAG_ADV_BTCOEX) 5120 error = iwn_send_advanced_btcoex(sc); 5121 else 5122 error = iwn_send_btcoex(sc); 5123 if (error != 0) { 5124 device_printf(sc->sc_dev, 5125 "%s: could not configure bluetooth coexistence, error %d\n", 5126 __func__, error); 5127 return error; 5128 } 5129 5130 /* Set mode, channel, RX filter and enable RX. */ 5131 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 5132 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp)); 5133 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp)); 5134 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 5135 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5136 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 5137 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5138 switch (ic->ic_opmode) { 5139 case IEEE80211_M_STA: 5140 sc->rxon.mode = IWN_MODE_STA; 5141 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 5142 break; 5143 case IEEE80211_M_MONITOR: 5144 sc->rxon.mode = IWN_MODE_MONITOR; 5145 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 5146 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 5147 break; 5148 default: 5149 /* Should not get there. */ 5150 break; 5151 } 5152 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 5153 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 5154 sc->rxon.ht_single_mask = 0xff; 5155 sc->rxon.ht_dual_mask = 0xff; 5156 sc->rxon.ht_triple_mask = 0xff; 5157 rxchain = 5158 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5159 IWN_RXCHAIN_MIMO_COUNT(2) | 5160 IWN_RXCHAIN_IDLE_COUNT(2); 5161 sc->rxon.rxchain = htole16(rxchain); 5162 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 5163 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 5164 if (error != 0) { 5165 device_printf(sc->sc_dev, "%s: RXON command failed\n", 5166 __func__); 5167 return error; 5168 } 5169 5170 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 5171 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 5172 __func__); 5173 return error; 5174 } 5175 5176 /* Configuration has changed, set TX power accordingly. */ 5177 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) { 5178 device_printf(sc->sc_dev, "%s: could not set TX power\n", 5179 __func__); 5180 return error; 5181 } 5182 5183 if ((error = iwn_set_critical_temp(sc)) != 0) { 5184 device_printf(sc->sc_dev, 5185 "%s: could not set critical temperature\n", __func__); 5186 return error; 5187 } 5188 5189 /* Set power saving level to CAM during initialization. */ 5190 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 5191 device_printf(sc->sc_dev, 5192 "%s: could not set power saving level\n", __func__); 5193 return error; 5194 } 5195 return 0; 5196} 5197 5198/* 5199 * Add an ssid element to a frame. 5200 */ 5201static uint8_t * 5202ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len) 5203{ 5204 *frm++ = IEEE80211_ELEMID_SSID; 5205 *frm++ = len; 5206 memcpy(frm, ssid, len); 5207 return frm + len; 5208} 5209 5210static int 5211iwn_scan(struct iwn_softc *sc) 5212{ 5213 struct ifnet *ifp = sc->sc_ifp; 5214 struct ieee80211com *ic = ifp->if_l2com; 5215 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/ 5216 struct ieee80211_node *ni = ss->ss_vap->iv_bss; 5217 struct iwn_scan_hdr *hdr; 5218 struct iwn_cmd_data *tx; 5219 struct iwn_scan_essid *essid; 5220 struct iwn_scan_chan *chan; 5221 struct ieee80211_frame *wh; 5222 struct ieee80211_rateset *rs; 5223 struct ieee80211_channel *c; 5224 uint8_t *buf, *frm; 5225 uint16_t rxchain; 5226 uint8_t txant; 5227 int buflen, error; 5228 5229 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 5230 if (buf == NULL) { 5231 device_printf(sc->sc_dev, 5232 "%s: could not allocate buffer for scan command\n", 5233 __func__); 5234 return ENOMEM; 5235 } 5236 hdr = (struct iwn_scan_hdr *)buf; 5237 /* 5238 * Move to the next channel if no frames are received within 10ms 5239 * after sending the probe request. 5240 */ 5241 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 5242 hdr->quiet_threshold = htole16(1); /* min # of packets */ 5243 5244 /* Select antennas for scanning. */ 5245 rxchain = 5246 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5247 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 5248 IWN_RXCHAIN_DRIVER_FORCE; 5249 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) && 5250 sc->hw_type == IWN_HW_REV_TYPE_4965) { 5251 /* Ant A must be avoided in 5GHz because of an HW bug. */ 5252 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 5253 } else /* Use all available RX antennas. */ 5254 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5255 hdr->rxchain = htole16(rxchain); 5256 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 5257 5258 tx = (struct iwn_cmd_data *)(hdr + 1); 5259 tx->flags = htole32(IWN_TX_AUTO_SEQ); 5260 tx->id = sc->broadcast_id; 5261 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 5262 5263 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) { 5264 /* Send probe requests at 6Mbps. */ 5265 tx->rate = htole32(0xd); 5266 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 5267 } else { 5268 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 5269 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 5270 sc->rxon.associd && sc->rxon.chan > 14) 5271 tx->rate = htole32(0xd); 5272 else { 5273 /* Send probe requests at 1Mbps. */ 5274 tx->rate = htole32(10 | IWN_RFLAG_CCK); 5275 } 5276 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 5277 } 5278 /* Use the first valid TX antenna. */ 5279 txant = IWN_LSB(sc->txchainmask); 5280 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 5281 5282 essid = (struct iwn_scan_essid *)(tx + 1); 5283 if (ss->ss_ssid[0].len != 0) { 5284 essid[0].id = IEEE80211_ELEMID_SSID; 5285 essid[0].len = ss->ss_ssid[0].len; 5286 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 5287 } 5288 /* 5289 * Build a probe request frame. Most of the following code is a 5290 * copy & paste of what is done in net80211. 5291 */ 5292 wh = (struct ieee80211_frame *)(essid + 20); 5293 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 5294 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 5295 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 5296 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 5297 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 5298 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 5299 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 5300 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 5301 5302 frm = (uint8_t *)(wh + 1); 5303 frm = ieee80211_add_ssid(frm, NULL, 0); 5304 frm = ieee80211_add_rates(frm, rs); 5305 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 5306 frm = ieee80211_add_xrates(frm, rs); 5307 if (ic->ic_htcaps & IEEE80211_HTC_HT) 5308 frm = ieee80211_add_htcap(frm, ni); 5309 5310 /* Set length of probe request. */ 5311 tx->len = htole16(frm - (uint8_t *)wh); 5312 5313 c = ic->ic_curchan; 5314 chan = (struct iwn_scan_chan *)frm; 5315 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 5316 chan->flags = 0; 5317 if (ss->ss_nssid > 0) 5318 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 5319 chan->dsp_gain = 0x6e; 5320 if (IEEE80211_IS_CHAN_5GHZ(c) && 5321 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5322 chan->rf_gain = 0x3b; 5323 chan->active = htole16(24); 5324 chan->passive = htole16(110); 5325 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5326 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 5327 chan->rf_gain = 0x3b; 5328 chan->active = htole16(24); 5329 if (sc->rxon.associd) 5330 chan->passive = htole16(78); 5331 else 5332 chan->passive = htole16(110); 5333 hdr->crc_threshold = 0xffff; 5334 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 5335 chan->rf_gain = 0x28; 5336 chan->active = htole16(36); 5337 chan->passive = htole16(120); 5338 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5339 } else { 5340 chan->rf_gain = 0x28; 5341 chan->active = htole16(36); 5342 if (sc->rxon.associd) 5343 chan->passive = htole16(88); 5344 else 5345 chan->passive = htole16(120); 5346 hdr->crc_threshold = 0xffff; 5347 } 5348 5349 DPRINTF(sc, IWN_DEBUG_STATE, 5350 "%s: chan %u flags 0x%x rf_gain 0x%x " 5351 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__, 5352 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 5353 chan->active, chan->passive); 5354 5355 hdr->nchan++; 5356 chan++; 5357 buflen = (uint8_t *)chan - buf; 5358 hdr->len = htole16(buflen); 5359 5360 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 5361 hdr->nchan); 5362 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5363 free(buf, M_DEVBUF); 5364 return error; 5365} 5366 5367static int 5368iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 5369{ 5370 struct iwn_ops *ops = &sc->ops; 5371 struct ifnet *ifp = sc->sc_ifp; 5372 struct ieee80211com *ic = ifp->if_l2com; 5373 struct ieee80211_node *ni = vap->iv_bss; 5374 int error; 5375 5376 /* Update adapter configuration. */ 5377 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5378 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5379 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5380 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5381 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5382 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5383 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5384 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5385 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5386 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5387 sc->rxon.cck_mask = 0; 5388 sc->rxon.ofdm_mask = 0x15; 5389 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5390 sc->rxon.cck_mask = 0x03; 5391 sc->rxon.ofdm_mask = 0; 5392 } else { 5393 /* Assume 802.11b/g. */ 5394 sc->rxon.cck_mask = 0x0f; 5395 sc->rxon.ofdm_mask = 0x15; 5396 } 5397 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 5398 sc->rxon.chan, sc->rxon.flags, sc->rxon.cck_mask, 5399 sc->rxon.ofdm_mask); 5400 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5401 if (error != 0) { 5402 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 5403 __func__, error); 5404 return error; 5405 } 5406 5407 /* Configuration has changed, set TX power accordingly. */ 5408 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5409 device_printf(sc->sc_dev, 5410 "%s: could not set TX power, error %d\n", __func__, error); 5411 return error; 5412 } 5413 /* 5414 * Reconfiguring RXON clears the firmware nodes table so we must 5415 * add the broadcast node again. 5416 */ 5417 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 5418 device_printf(sc->sc_dev, 5419 "%s: could not add broadcast node, error %d\n", __func__, 5420 error); 5421 return error; 5422 } 5423 return 0; 5424} 5425 5426static int 5427iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 5428{ 5429 struct iwn_ops *ops = &sc->ops; 5430 struct ifnet *ifp = sc->sc_ifp; 5431 struct ieee80211com *ic = ifp->if_l2com; 5432 struct ieee80211_node *ni = vap->iv_bss; 5433 struct iwn_node_info node; 5434 uint32_t htflags = 0; 5435 int error; 5436 5437 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5438 /* Link LED blinks while monitoring. */ 5439 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 5440 return 0; 5441 } 5442 if ((error = iwn_set_timing(sc, ni)) != 0) { 5443 device_printf(sc->sc_dev, 5444 "%s: could not set timing, error %d\n", __func__, error); 5445 return error; 5446 } 5447 5448 /* Update adapter configuration. */ 5449 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5450 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 5451 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5452 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5453 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 5454 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5455 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5456 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5457 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5458 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5459 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 5460 sc->rxon.cck_mask = 0; 5461 sc->rxon.ofdm_mask = 0x15; 5462 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 5463 sc->rxon.cck_mask = 0x03; 5464 sc->rxon.ofdm_mask = 0; 5465 } else { 5466 /* Assume 802.11b/g. */ 5467 sc->rxon.cck_mask = 0x0f; 5468 sc->rxon.ofdm_mask = 0x15; 5469 } 5470 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 5471 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 5472 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 5473 switch (ic->ic_curhtprotmode) { 5474 case IEEE80211_HTINFO_OPMODE_HT20PR: 5475 htflags |= IWN_RXON_HT_MODEPURE40; 5476 break; 5477 default: 5478 htflags |= IWN_RXON_HT_MODEMIXED; 5479 break; 5480 } 5481 } 5482 if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 5483 htflags |= IWN_RXON_HT_HT40MINUS; 5484 } 5485 sc->rxon.flags |= htole32(htflags); 5486 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 5487 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n", 5488 sc->rxon.chan, sc->rxon.flags); 5489 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5490 if (error != 0) { 5491 device_printf(sc->sc_dev, 5492 "%s: could not update configuration, error %d\n", __func__, 5493 error); 5494 return error; 5495 } 5496 5497 /* Configuration has changed, set TX power accordingly. */ 5498 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 5499 device_printf(sc->sc_dev, 5500 "%s: could not set TX power, error %d\n", __func__, error); 5501 return error; 5502 } 5503 5504 /* Fake a join to initialize the TX rate. */ 5505 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 5506 iwn_newassoc(ni, 1); 5507 5508 /* Add BSS node. */ 5509 memset(&node, 0, sizeof node); 5510 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 5511 node.id = IWN_ID_BSS; 5512 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 5513 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 5514 case IEEE80211_HTCAP_SMPS_ENA: 5515 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 5516 break; 5517 case IEEE80211_HTCAP_SMPS_DYNAMIC: 5518 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 5519 break; 5520 } 5521 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 5522 IWN_AMDPU_DENSITY(5)); /* 4us */ 5523 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 5524 node.htflags |= htole32(IWN_NODE_HT40); 5525 } 5526 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 5527 error = ops->add_node(sc, &node, 1); 5528 if (error != 0) { 5529 device_printf(sc->sc_dev, 5530 "%s: could not add BSS node, error %d\n", __func__, error); 5531 return error; 5532 } 5533 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 5534 __func__, node.id); 5535 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 5536 device_printf(sc->sc_dev, 5537 "%s: could not setup link quality for node %d, error %d\n", 5538 __func__, node.id, error); 5539 return error; 5540 } 5541 5542 if ((error = iwn_init_sensitivity(sc)) != 0) { 5543 device_printf(sc->sc_dev, 5544 "%s: could not set sensitivity, error %d\n", __func__, 5545 error); 5546 return error; 5547 } 5548 /* Start periodic calibration timer. */ 5549 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5550 sc->calib_cnt = 0; 5551 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 5552 sc); 5553 5554 /* Link LED always on while associated. */ 5555 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5556 return 0; 5557} 5558 5559/* 5560 * This function is called by upper layer when an ADDBA request is received 5561 * from another STA and before the ADDBA response is sent. 5562 */ 5563static int 5564iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 5565 int baparamset, int batimeout, int baseqctl) 5566{ 5567#define MS(_v, _f) (((_v) & _f) >> _f##_S) 5568 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5569 struct iwn_ops *ops = &sc->ops; 5570 struct iwn_node *wn = (void *)ni; 5571 struct iwn_node_info node; 5572 uint16_t ssn; 5573 uint8_t tid; 5574 int error; 5575 5576 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 5577 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 5578 5579 memset(&node, 0, sizeof node); 5580 node.id = wn->id; 5581 node.control = IWN_NODE_UPDATE; 5582 node.flags = IWN_FLAG_SET_ADDBA; 5583 node.addba_tid = tid; 5584 node.addba_ssn = htole16(ssn); 5585 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 5586 wn->id, tid, ssn); 5587 error = ops->add_node(sc, &node, 1); 5588 if (error != 0) 5589 return error; 5590 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 5591#undef MS 5592} 5593 5594/* 5595 * This function is called by upper layer on teardown of an HT-immediate 5596 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5597 */ 5598static void 5599iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 5600{ 5601 struct ieee80211com *ic = ni->ni_ic; 5602 struct iwn_softc *sc = ic->ic_ifp->if_softc; 5603 struct iwn_ops *ops = &sc->ops; 5604 struct iwn_node *wn = (void *)ni; 5605 struct iwn_node_info node; 5606 uint8_t tid; 5607 5608 /* XXX: tid as an argument */ 5609 for (tid = 0; tid < WME_NUM_TID; tid++) { 5610 if (&ni->ni_rx_ampdu[tid] == rap) 5611 break; 5612 } 5613 5614 memset(&node, 0, sizeof node); 5615 node.id = wn->id; 5616 node.control = IWN_NODE_UPDATE; 5617 node.flags = IWN_FLAG_SET_DELBA; 5618 node.delba_tid = tid; 5619 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 5620 (void)ops->add_node(sc, &node, 1); 5621 sc->sc_ampdu_rx_stop(ni, rap); 5622} 5623 5624static int 5625iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5626 int dialogtoken, int baparamset, int batimeout) 5627{ 5628 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5629 int qid; 5630 5631 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 5632 if (sc->qid2tap[qid] == NULL) 5633 break; 5634 } 5635 if (qid == sc->ntxqs) { 5636 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 5637 __func__); 5638 return 0; 5639 } 5640 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 5641 if (tap->txa_private == NULL) { 5642 device_printf(sc->sc_dev, 5643 "%s: failed to alloc TX aggregation structure\n", __func__); 5644 return 0; 5645 } 5646 sc->qid2tap[qid] = tap; 5647 *(int *)tap->txa_private = qid; 5648 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 5649 batimeout); 5650} 5651 5652static int 5653iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5654 int code, int baparamset, int batimeout) 5655{ 5656 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5657 int qid = *(int *)tap->txa_private; 5658 uint8_t tid = WME_AC_TO_TID(tap->txa_ac); 5659 int ret; 5660 5661 if (code == IEEE80211_STATUS_SUCCESS) { 5662 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 5663 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 5664 if (ret != 1) 5665 return ret; 5666 } else { 5667 sc->qid2tap[qid] = NULL; 5668 free(tap->txa_private, M_DEVBUF); 5669 tap->txa_private = NULL; 5670 } 5671 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 5672} 5673 5674/* 5675 * This function is called by upper layer when an ADDBA response is received 5676 * from another STA. 5677 */ 5678static int 5679iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5680 uint8_t tid) 5681{ 5682 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[TID_TO_WME_AC(tid)]; 5683 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5684 struct iwn_ops *ops = &sc->ops; 5685 struct iwn_node *wn = (void *)ni; 5686 struct iwn_node_info node; 5687 int error, qid; 5688 5689 /* Enable TX for the specified RA/TID. */ 5690 wn->disable_tid &= ~(1 << tid); 5691 memset(&node, 0, sizeof node); 5692 node.id = wn->id; 5693 node.control = IWN_NODE_UPDATE; 5694 node.flags = IWN_FLAG_SET_DISABLE_TID; 5695 node.disable_tid = htole16(wn->disable_tid); 5696 error = ops->add_node(sc, &node, 1); 5697 if (error != 0) 5698 return 0; 5699 5700 if ((error = iwn_nic_lock(sc)) != 0) 5701 return 0; 5702 qid = *(int *)tap->txa_private; 5703 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 5704 __func__, wn->id, tid, tap->txa_start, qid); 5705 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 5706 iwn_nic_unlock(sc); 5707 5708 iwn_set_link_quality(sc, ni); 5709 return 1; 5710} 5711 5712static void 5713iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 5714{ 5715 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5716 struct iwn_ops *ops = &sc->ops; 5717 uint8_t tid = WME_AC_TO_TID(tap->txa_ac); 5718 int qid; 5719 5720 sc->sc_addba_stop(ni, tap); 5721 5722 if (tap->txa_private == NULL) 5723 return; 5724 5725 qid = *(int *)tap->txa_private; 5726 if (sc->txq[qid].queued != 0) 5727 return; 5728 if (iwn_nic_lock(sc) != 0) 5729 return; 5730 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 5731 iwn_nic_unlock(sc); 5732 sc->qid2tap[qid] = NULL; 5733 free(tap->txa_private, M_DEVBUF); 5734 tap->txa_private = NULL; 5735} 5736 5737static void 5738iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5739 int qid, uint8_t tid, uint16_t ssn) 5740{ 5741 struct iwn_node *wn = (void *)ni; 5742 5743 /* Stop TX scheduler while we're changing its configuration. */ 5744 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5745 IWN4965_TXQ_STATUS_CHGACT); 5746 5747 /* Assign RA/TID translation to the queue. */ 5748 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5749 wn->id << 4 | tid); 5750 5751 /* Enable chain-building mode for the queue. */ 5752 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5753 5754 /* Set starting sequence number from the ADDBA request. */ 5755 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 5756 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5757 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5758 5759 /* Set scheduler window size. */ 5760 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5761 IWN_SCHED_WINSZ); 5762 /* Set scheduler frame limit. */ 5763 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5764 IWN_SCHED_LIMIT << 16); 5765 5766 /* Enable interrupts for the queue. */ 5767 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5768 5769 /* Mark the queue as active. */ 5770 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5771 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5772 iwn_tid2fifo[tid] << 1); 5773} 5774 5775static void 5776iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 5777{ 5778 /* Stop TX scheduler while we're changing its configuration. */ 5779 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5780 IWN4965_TXQ_STATUS_CHGACT); 5781 5782 /* Set starting sequence number from the ADDBA request. */ 5783 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5784 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5785 5786 /* Disable interrupts for the queue. */ 5787 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5788 5789 /* Mark the queue as inactive. */ 5790 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5791 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5792} 5793 5794static void 5795iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5796 int qid, uint8_t tid, uint16_t ssn) 5797{ 5798 struct iwn_node *wn = (void *)ni; 5799 5800 /* Stop TX scheduler while we're changing its configuration. */ 5801 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5802 IWN5000_TXQ_STATUS_CHGACT); 5803 5804 /* Assign RA/TID translation to the queue. */ 5805 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5806 wn->id << 4 | tid); 5807 5808 /* Enable chain-building mode for the queue. */ 5809 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5810 5811 /* Enable aggregation for the queue. */ 5812 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5813 5814 /* Set starting sequence number from the ADDBA request. */ 5815 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 5816 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5817 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5818 5819 /* Set scheduler window size and frame limit. */ 5820 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5821 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 5822 5823 /* Enable interrupts for the queue. */ 5824 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5825 5826 /* Mark the queue as active. */ 5827 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5828 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 5829} 5830 5831static void 5832iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 5833{ 5834 /* Stop TX scheduler while we're changing its configuration. */ 5835 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5836 IWN5000_TXQ_STATUS_CHGACT); 5837 5838 /* Disable aggregation for the queue. */ 5839 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5840 5841 /* Set starting sequence number from the ADDBA request. */ 5842 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 5843 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5844 5845 /* Disable interrupts for the queue. */ 5846 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 5847 5848 /* Mark the queue as inactive. */ 5849 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5850 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 5851} 5852 5853/* 5854 * Query calibration tables from the initialization firmware. We do this 5855 * only once at first boot. Called from a process context. 5856 */ 5857static int 5858iwn5000_query_calibration(struct iwn_softc *sc) 5859{ 5860 struct iwn5000_calib_config cmd; 5861 int error; 5862 5863 memset(&cmd, 0, sizeof cmd); 5864 cmd.ucode.once.enable = 0xffffffff; 5865 cmd.ucode.once.start = 0xffffffff; 5866 cmd.ucode.once.send = 0xffffffff; 5867 cmd.ucode.flags = 0xffffffff; 5868 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 5869 __func__); 5870 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 5871 if (error != 0) 5872 return error; 5873 5874 /* Wait at most two seconds for calibration to complete. */ 5875 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 5876 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 5877 return error; 5878} 5879 5880/* 5881 * Send calibration results to the runtime firmware. These results were 5882 * obtained on first boot from the initialization firmware. 5883 */ 5884static int 5885iwn5000_send_calibration(struct iwn_softc *sc) 5886{ 5887 int idx, error; 5888 5889 for (idx = 0; idx < 5; idx++) { 5890 if (sc->calibcmd[idx].buf == NULL) 5891 continue; /* No results available. */ 5892 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5893 "send calibration result idx=%d len=%d\n", idx, 5894 sc->calibcmd[idx].len); 5895 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 5896 sc->calibcmd[idx].len, 0); 5897 if (error != 0) { 5898 device_printf(sc->sc_dev, 5899 "%s: could not send calibration result, error %d\n", 5900 __func__, error); 5901 return error; 5902 } 5903 } 5904 return 0; 5905} 5906 5907static int 5908iwn5000_send_wimax_coex(struct iwn_softc *sc) 5909{ 5910 struct iwn5000_wimax_coex wimax; 5911 5912#ifdef notyet 5913 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 5914 /* Enable WiMAX coexistence for combo adapters. */ 5915 wimax.flags = 5916 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 5917 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 5918 IWN_WIMAX_COEX_STA_TABLE_VALID | 5919 IWN_WIMAX_COEX_ENABLE; 5920 memcpy(wimax.events, iwn6050_wimax_events, 5921 sizeof iwn6050_wimax_events); 5922 } else 5923#endif 5924 { 5925 /* Disable WiMAX coexistence. */ 5926 wimax.flags = 0; 5927 memset(wimax.events, 0, sizeof wimax.events); 5928 } 5929 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 5930 __func__); 5931 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 5932} 5933 5934static int 5935iwn5000_crystal_calib(struct iwn_softc *sc) 5936{ 5937 struct iwn5000_phy_calib_crystal cmd; 5938 5939 memset(&cmd, 0, sizeof cmd); 5940 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 5941 cmd.ngroups = 1; 5942 cmd.isvalid = 1; 5943 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 5944 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 5945 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 5946 cmd.cap_pin[0], cmd.cap_pin[1]); 5947 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5948} 5949 5950static int 5951iwn5000_temp_offset_calib(struct iwn_softc *sc) 5952{ 5953 struct iwn5000_phy_calib_temp_offset cmd; 5954 5955 memset(&cmd, 0, sizeof cmd); 5956 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 5957 cmd.ngroups = 1; 5958 cmd.isvalid = 1; 5959 if (sc->eeprom_temp != 0) 5960 cmd.offset = htole16(sc->eeprom_temp); 5961 else 5962 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 5963 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 5964 le16toh(cmd.offset)); 5965 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 5966} 5967 5968/* 5969 * This function is called after the runtime firmware notifies us of its 5970 * readiness (called in a process context). 5971 */ 5972static int 5973iwn4965_post_alive(struct iwn_softc *sc) 5974{ 5975 int error, qid; 5976 5977 if ((error = iwn_nic_lock(sc)) != 0) 5978 return error; 5979 5980 /* Clear TX scheduler state in SRAM. */ 5981 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 5982 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 5983 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 5984 5985 /* Set physical address of TX scheduler rings (1KB aligned). */ 5986 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 5987 5988 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 5989 5990 /* Disable chain mode for all our 16 queues. */ 5991 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 5992 5993 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 5994 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 5995 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 5996 5997 /* Set scheduler window size. */ 5998 iwn_mem_write(sc, sc->sched_base + 5999 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 6000 /* Set scheduler frame limit. */ 6001 iwn_mem_write(sc, sc->sched_base + 6002 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 6003 IWN_SCHED_LIMIT << 16); 6004 } 6005 6006 /* Enable interrupts for all our 16 queues. */ 6007 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 6008 /* Identify TX FIFO rings (0-7). */ 6009 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 6010 6011 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6012 for (qid = 0; qid < 7; qid++) { 6013 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 6014 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 6015 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 6016 } 6017 iwn_nic_unlock(sc); 6018 return 0; 6019} 6020 6021/* 6022 * This function is called after the initialization or runtime firmware 6023 * notifies us of its readiness (called in a process context). 6024 */ 6025static int 6026iwn5000_post_alive(struct iwn_softc *sc) 6027{ 6028 int error, qid; 6029 6030#ifndef __HAIKU__ 6031 /* Switch to using ICT interrupt mode. */ 6032 iwn5000_ict_reset(sc); 6033#endif 6034 6035 if ((error = iwn_nic_lock(sc)) != 0) 6036 return error; 6037 6038 /* Clear TX scheduler state in SRAM. */ 6039 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 6040 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 6041 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 6042 6043 /* Set physical address of TX scheduler rings (1KB aligned). */ 6044 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 6045 6046 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 6047 6048 /* Enable chain mode for all queues, except command queue. */ 6049 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 6050 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 6051 6052 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 6053 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 6054 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 6055 6056 iwn_mem_write(sc, sc->sched_base + 6057 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 6058 /* Set scheduler window size and frame limit. */ 6059 iwn_mem_write(sc, sc->sched_base + 6060 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 6061 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 6062 } 6063 6064 /* Enable interrupts for all our 20 queues. */ 6065 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 6066 /* Identify TX FIFO rings (0-7). */ 6067 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 6068 6069 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6070 for (qid = 0; qid < 7; qid++) { 6071 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 6072 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6073 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 6074 } 6075 iwn_nic_unlock(sc); 6076 6077 /* Configure WiMAX coexistence for combo adapters. */ 6078 error = iwn5000_send_wimax_coex(sc); 6079 if (error != 0) { 6080 device_printf(sc->sc_dev, 6081 "%s: could not configure WiMAX coexistence, error %d\n", 6082 __func__, error); 6083 return error; 6084 } 6085 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 6086 /* Perform crystal calibration. */ 6087 error = iwn5000_crystal_calib(sc); 6088 if (error != 0) { 6089 device_printf(sc->sc_dev, 6090 "%s: crystal calibration failed, error %d\n", 6091 __func__, error); 6092 return error; 6093 } 6094 } 6095 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 6096 /* Query calibration from the initialization firmware. */ 6097 if ((error = iwn5000_query_calibration(sc)) != 0) { 6098 device_printf(sc->sc_dev, 6099 "%s: could not query calibration, error %d\n", 6100 __func__, error); 6101 return error; 6102 } 6103 /* 6104 * We have the calibration results now, reboot with the 6105 * runtime firmware (call ourselves recursively!) 6106 */ 6107 iwn_hw_stop(sc); 6108 error = iwn_hw_init(sc); 6109 } else { 6110 /* Send calibration results to runtime firmware. */ 6111 error = iwn5000_send_calibration(sc); 6112 } 6113 return error; 6114} 6115 6116/* 6117 * The firmware boot code is small and is intended to be copied directly into 6118 * the NIC internal memory (no DMA transfer). 6119 */ 6120static int 6121iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 6122{ 6123 int error, ntries; 6124 6125 size /= sizeof (uint32_t); 6126 6127 if ((error = iwn_nic_lock(sc)) != 0) 6128 return error; 6129 6130 /* Copy microcode image into NIC memory. */ 6131 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 6132 (const uint32_t *)ucode, size); 6133 6134 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 6135 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 6136 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 6137 6138 /* Start boot load now. */ 6139 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 6140 6141 /* Wait for transfer to complete. */ 6142 for (ntries = 0; ntries < 1000; ntries++) { 6143 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 6144 IWN_BSM_WR_CTRL_START)) 6145 break; 6146 DELAY(10); 6147 } 6148 if (ntries == 1000) { 6149 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 6150 __func__); 6151 iwn_nic_unlock(sc); 6152 return ETIMEDOUT; 6153 } 6154 6155 /* Enable boot after power up. */ 6156 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 6157 6158 iwn_nic_unlock(sc); 6159 return 0; 6160} 6161 6162static int 6163iwn4965_load_firmware(struct iwn_softc *sc) 6164{ 6165 struct iwn_fw_info *fw = &sc->fw; 6166 struct iwn_dma_info *dma = &sc->fw_dma; 6167 int error; 6168 6169 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 6170 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 6171 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6172 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6173 fw->init.text, fw->init.textsz); 6174 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6175 6176 /* Tell adapter where to find initialization sections. */ 6177 if ((error = iwn_nic_lock(sc)) != 0) 6178 return error; 6179 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6180 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 6181 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6182 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6183 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 6184 iwn_nic_unlock(sc); 6185 6186 /* Load firmware boot code. */ 6187 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 6188 if (error != 0) { 6189 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 6190 __func__); 6191 return error; 6192 } 6193 /* Now press "execute". */ 6194 IWN_WRITE(sc, IWN_RESET, 0); 6195 6196 /* Wait at most one second for first alive notification. */ 6197 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 6198 device_printf(sc->sc_dev, 6199 "%s: timeout waiting for adapter to initialize, error %d\n", 6200 __func__, error); 6201 return error; 6202 } 6203 6204 /* Retrieve current temperature for initial TX power calibration. */ 6205 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 6206 sc->temp = iwn4965_get_temperature(sc); 6207 6208 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 6209 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 6210 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6211 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6212 fw->main.text, fw->main.textsz); 6213 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6214 6215 /* Tell adapter where to find runtime sections. */ 6216 if ((error = iwn_nic_lock(sc)) != 0) 6217 return error; 6218 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6219 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 6220 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6221 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6222 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 6223 IWN_FW_UPDATED | fw->main.textsz); 6224 iwn_nic_unlock(sc); 6225 6226 return 0; 6227} 6228 6229static int 6230iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 6231 const uint8_t *section, int size) 6232{ 6233 struct iwn_dma_info *dma = &sc->fw_dma; 6234 int error; 6235 6236 /* Copy firmware section into pre-allocated DMA-safe memory. */ 6237 memcpy(dma->vaddr, section, size); 6238 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 6239 6240 if ((error = iwn_nic_lock(sc)) != 0) 6241 return error; 6242 6243 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6244 IWN_FH_TX_CONFIG_DMA_PAUSE); 6245 6246 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 6247 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 6248 IWN_LOADDR(dma->paddr)); 6249 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 6250 IWN_HIADDR(dma->paddr) << 28 | size); 6251 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 6252 IWN_FH_TXBUF_STATUS_TBNUM(1) | 6253 IWN_FH_TXBUF_STATUS_TBIDX(1) | 6254 IWN_FH_TXBUF_STATUS_TFBD_VALID); 6255 6256 /* Kick Flow Handler to start DMA transfer. */ 6257 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6258 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 6259 6260 iwn_nic_unlock(sc); 6261 6262 /* Wait at most five seconds for FH DMA transfer to complete. */ 6263 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 6264} 6265 6266static int 6267iwn5000_load_firmware(struct iwn_softc *sc) 6268{ 6269 struct iwn_fw_part *fw; 6270 int error; 6271 6272 /* Load the initialization firmware on first boot only. */ 6273 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 6274 &sc->fw.main : &sc->fw.init; 6275 6276 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 6277 fw->text, fw->textsz); 6278 if (error != 0) { 6279 device_printf(sc->sc_dev, 6280 "%s: could not load firmware %s section, error %d\n", 6281 __func__, ".text", error); 6282 return error; 6283 } 6284 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 6285 fw->data, fw->datasz); 6286 if (error != 0) { 6287 device_printf(sc->sc_dev, 6288 "%s: could not load firmware %s section, error %d\n", 6289 __func__, ".data", error); 6290 return error; 6291 } 6292 6293 /* Now press "execute". */ 6294 IWN_WRITE(sc, IWN_RESET, 0); 6295 return 0; 6296} 6297 6298/* 6299 * Extract text and data sections from a legacy firmware image. 6300 */ 6301static int 6302iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 6303{ 6304 const uint32_t *ptr; 6305 size_t hdrlen = 24; 6306 uint32_t rev; 6307 6308 ptr = (const uint32_t *)fw->data; 6309 rev = le32toh(*ptr++); 6310 6311 /* Check firmware API version. */ 6312 if (IWN_FW_API(rev) <= 1) { 6313 device_printf(sc->sc_dev, 6314 "%s: bad firmware, need API version >=2\n", __func__); 6315 return EINVAL; 6316 } 6317 if (IWN_FW_API(rev) >= 3) { 6318 /* Skip build number (version 2 header). */ 6319 hdrlen += 4; 6320 ptr++; 6321 } 6322 if (fw->size < hdrlen) { 6323 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6324 __func__, fw->size); 6325 return EINVAL; 6326 } 6327 fw->main.textsz = le32toh(*ptr++); 6328 fw->main.datasz = le32toh(*ptr++); 6329 fw->init.textsz = le32toh(*ptr++); 6330 fw->init.datasz = le32toh(*ptr++); 6331 fw->boot.textsz = le32toh(*ptr++); 6332 6333 /* Check that all firmware sections fit. */ 6334 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 6335 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 6336 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6337 __func__, fw->size); 6338 return EINVAL; 6339 } 6340 6341 /* Get pointers to firmware sections. */ 6342 fw->main.text = (const uint8_t *)ptr; 6343 fw->main.data = fw->main.text + fw->main.textsz; 6344 fw->init.text = fw->main.data + fw->main.datasz; 6345 fw->init.data = fw->init.text + fw->init.textsz; 6346 fw->boot.text = fw->init.data + fw->init.datasz; 6347 return 0; 6348} 6349 6350/* 6351 * Extract text and data sections from a TLV firmware image. 6352 */ 6353static int 6354iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 6355 uint16_t alt) 6356{ 6357 const struct iwn_fw_tlv_hdr *hdr; 6358 const struct iwn_fw_tlv *tlv; 6359 const uint8_t *ptr, *end; 6360 uint64_t altmask; 6361 uint32_t len, tmp; 6362 6363 if (fw->size < sizeof (*hdr)) { 6364 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6365 __func__, fw->size); 6366 return EINVAL; 6367 } 6368 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 6369 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 6370 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 6371 __func__, le32toh(hdr->signature)); 6372 return EINVAL; 6373 } 6374 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 6375 le32toh(hdr->build)); 6376 6377 /* 6378 * Select the closest supported alternative that is less than 6379 * or equal to the specified one. 6380 */ 6381 altmask = le64toh(hdr->altmask); 6382 while (alt > 0 && !(altmask & (1ULL << alt))) 6383 alt--; /* Downgrade. */ 6384 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 6385 6386 ptr = (const uint8_t *)(hdr + 1); 6387 end = (const uint8_t *)(fw->data + fw->size); 6388 6389 /* Parse type-length-value fields. */ 6390 while (ptr + sizeof (*tlv) <= end) { 6391 tlv = (const struct iwn_fw_tlv *)ptr; 6392 len = le32toh(tlv->len); 6393 6394 ptr += sizeof (*tlv); 6395 if (ptr + len > end) { 6396 device_printf(sc->sc_dev, 6397 "%s: firmware too short: %zu bytes\n", __func__, 6398 fw->size); 6399 return EINVAL; 6400 } 6401 /* Skip other alternatives. */ 6402 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 6403 goto next; 6404 6405 switch (le16toh(tlv->type)) { 6406 case IWN_FW_TLV_MAIN_TEXT: 6407 fw->main.text = ptr; 6408 fw->main.textsz = len; 6409 break; 6410 case IWN_FW_TLV_MAIN_DATA: 6411 fw->main.data = ptr; 6412 fw->main.datasz = len; 6413 break; 6414 case IWN_FW_TLV_INIT_TEXT: 6415 fw->init.text = ptr; 6416 fw->init.textsz = len; 6417 break; 6418 case IWN_FW_TLV_INIT_DATA: 6419 fw->init.data = ptr; 6420 fw->init.datasz = len; 6421 break; 6422 case IWN_FW_TLV_BOOT_TEXT: 6423 fw->boot.text = ptr; 6424 fw->boot.textsz = len; 6425 break; 6426 case IWN_FW_TLV_ENH_SENS: 6427 if (!len) 6428 sc->sc_flags |= IWN_FLAG_ENH_SENS; 6429 break; 6430 case IWN_FW_TLV_PHY_CALIB: 6431 tmp = htole32(*ptr); 6432 if (tmp < 253) { 6433 sc->reset_noise_gain = tmp; 6434 sc->noise_gain = tmp + 1; 6435 } 6436 break; 6437 default: 6438 DPRINTF(sc, IWN_DEBUG_RESET, 6439 "TLV type %d not handled\n", le16toh(tlv->type)); 6440 break; 6441 } 6442 next: /* TLV fields are 32-bit aligned. */ 6443 ptr += (len + 3) & ~3; 6444 } 6445 return 0; 6446} 6447 6448static int 6449iwn_read_firmware(struct iwn_softc *sc) 6450{ 6451 struct iwn_fw_info *fw = &sc->fw; 6452 int error; 6453 6454 IWN_UNLOCK(sc); 6455 6456 memset(fw, 0, sizeof (*fw)); 6457 6458 /* Read firmware image from filesystem. */ 6459 sc->fw_fp = firmware_get(sc->fwname); 6460 if (sc->fw_fp == NULL) { 6461 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 6462 __func__, sc->fwname); 6463 IWN_LOCK(sc); 6464 return EINVAL; 6465 } 6466 IWN_LOCK(sc); 6467 6468 fw->size = sc->fw_fp->datasize; 6469 fw->data = (const uint8_t *)sc->fw_fp->data; 6470 if (fw->size < sizeof (uint32_t)) { 6471 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 6472 __func__, fw->size); 6473 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6474 sc->fw_fp = NULL; 6475 return EINVAL; 6476 } 6477 6478 /* Retrieve text and data sections. */ 6479 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 6480 error = iwn_read_firmware_leg(sc, fw); 6481 else 6482 error = iwn_read_firmware_tlv(sc, fw, 1); 6483 if (error != 0) { 6484 device_printf(sc->sc_dev, 6485 "%s: could not read firmware sections, error %d\n", 6486 __func__, error); 6487 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6488 sc->fw_fp = NULL; 6489 return error; 6490 } 6491 6492 /* Make sure text and data sections fit in hardware memory. */ 6493 if (fw->main.textsz > sc->fw_text_maxsz || 6494 fw->main.datasz > sc->fw_data_maxsz || 6495 fw->init.textsz > sc->fw_text_maxsz || 6496 fw->init.datasz > sc->fw_data_maxsz || 6497 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 6498 (fw->boot.textsz & 3) != 0) { 6499 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 6500 __func__); 6501 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6502 sc->fw_fp = NULL; 6503 return EINVAL; 6504 } 6505 6506 /* We can proceed with loading the firmware. */ 6507 return 0; 6508} 6509 6510static int 6511iwn_clock_wait(struct iwn_softc *sc) 6512{ 6513 int ntries; 6514 6515 /* Set "initialization complete" bit. */ 6516 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6517 6518 /* Wait for clock stabilization. */ 6519 for (ntries = 0; ntries < 2500; ntries++) { 6520 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 6521 return 0; 6522 DELAY(10); 6523 } 6524 device_printf(sc->sc_dev, 6525 "%s: timeout waiting for clock stabilization\n", __func__); 6526 return ETIMEDOUT; 6527} 6528 6529static int 6530iwn_apm_init(struct iwn_softc *sc) 6531{ 6532 uint32_t reg; 6533 int error; 6534 6535 /* Disable L0s exit timer (NMI bug workaround). */ 6536 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6537 /* Don't wait for ICH L0s (ICH bug workaround). */ 6538 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6539 6540 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6541 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6542 6543 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6544 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6545 6546 /* Retrieve PCIe Active State Power Management (ASPM). */ 6547 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 6548 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6549 if (reg & 0x02) /* L1 Entry enabled. */ 6550 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6551 else 6552 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6553 6554 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6555 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6556 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6557 6558 /* Wait for clock stabilization before accessing prph. */ 6559 if ((error = iwn_clock_wait(sc)) != 0) 6560 return error; 6561 6562 if ((error = iwn_nic_lock(sc)) != 0) 6563 return error; 6564 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6565 /* Enable DMA and BSM (Bootstrap State Machine). */ 6566 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6567 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6568 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6569 } else { 6570 /* Enable DMA. */ 6571 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6572 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6573 } 6574 DELAY(20); 6575 /* Disable L1-Active. */ 6576 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6577 iwn_nic_unlock(sc); 6578 6579 return 0; 6580} 6581 6582static void 6583iwn_apm_stop_master(struct iwn_softc *sc) 6584{ 6585 int ntries; 6586 6587 /* Stop busmaster DMA activity. */ 6588 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6589 for (ntries = 0; ntries < 100; ntries++) { 6590 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6591 return; 6592 DELAY(10); 6593 } 6594 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 6595} 6596 6597static void 6598iwn_apm_stop(struct iwn_softc *sc) 6599{ 6600 iwn_apm_stop_master(sc); 6601 6602 /* Reset the entire device. */ 6603 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6604 DELAY(10); 6605 /* Clear "initialization complete" bit. */ 6606 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6607} 6608 6609static int 6610iwn4965_nic_config(struct iwn_softc *sc) 6611{ 6612 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6613 /* 6614 * I don't believe this to be correct but this is what the 6615 * vendor driver is doing. Probably the bits should not be 6616 * shifted in IWN_RFCFG_*. 6617 */ 6618 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6619 IWN_RFCFG_TYPE(sc->rfcfg) | 6620 IWN_RFCFG_STEP(sc->rfcfg) | 6621 IWN_RFCFG_DASH(sc->rfcfg)); 6622 } 6623 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6624 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6625 return 0; 6626} 6627 6628static int 6629iwn5000_nic_config(struct iwn_softc *sc) 6630{ 6631 uint32_t tmp; 6632 int error; 6633 6634 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6635 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6636 IWN_RFCFG_TYPE(sc->rfcfg) | 6637 IWN_RFCFG_STEP(sc->rfcfg) | 6638 IWN_RFCFG_DASH(sc->rfcfg)); 6639 } 6640 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6641 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6642 6643 if ((error = iwn_nic_lock(sc)) != 0) 6644 return error; 6645 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6646 6647 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6648 /* 6649 * Select first Switching Voltage Regulator (1.32V) to 6650 * solve a stability issue related to noisy DC2DC line 6651 * in the silicon of 1000 Series. 6652 */ 6653 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6654 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6655 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6656 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6657 } 6658 iwn_nic_unlock(sc); 6659 6660 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6661 /* Use internal power amplifier only. */ 6662 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6663 } 6664 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6665 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6666 /* Indicate that ROM calibration version is >=6. */ 6667 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6668 } 6669 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6670 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6671 return 0; 6672} 6673 6674/* 6675 * Take NIC ownership over Intel Active Management Technology (AMT). 6676 */ 6677static int 6678iwn_hw_prepare(struct iwn_softc *sc) 6679{ 6680 int ntries; 6681 6682 /* Check if hardware is ready. */ 6683 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6684 for (ntries = 0; ntries < 5; ntries++) { 6685 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6686 IWN_HW_IF_CONFIG_NIC_READY) 6687 return 0; 6688 DELAY(10); 6689 } 6690 6691 /* Hardware not ready, force into ready state. */ 6692 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6693 for (ntries = 0; ntries < 15000; ntries++) { 6694 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6695 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6696 break; 6697 DELAY(10); 6698 } 6699 if (ntries == 15000) 6700 return ETIMEDOUT; 6701 6702 /* Hardware should be ready now. */ 6703 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6704 for (ntries = 0; ntries < 5; ntries++) { 6705 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6706 IWN_HW_IF_CONFIG_NIC_READY) 6707 return 0; 6708 DELAY(10); 6709 } 6710 return ETIMEDOUT; 6711} 6712 6713static int 6714iwn_hw_init(struct iwn_softc *sc) 6715{ 6716 struct iwn_ops *ops = &sc->ops; 6717 int error, chnl, qid; 6718 6719 /* Clear pending interrupts. */ 6720 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6721 6722 if ((error = iwn_apm_init(sc)) != 0) { 6723 device_printf(sc->sc_dev, 6724 "%s: could not power ON adapter, error %d\n", __func__, 6725 error); 6726 return error; 6727 } 6728 6729 /* Select VMAIN power source. */ 6730 if ((error = iwn_nic_lock(sc)) != 0) 6731 return error; 6732 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6733 iwn_nic_unlock(sc); 6734 6735 /* Perform adapter-specific initialization. */ 6736 if ((error = ops->nic_config(sc)) != 0) 6737 return error; 6738 6739 /* Initialize RX ring. */ 6740 if ((error = iwn_nic_lock(sc)) != 0) 6741 return error; 6742 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6743 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6744 /* Set physical address of RX ring (256-byte aligned). */ 6745 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6746 /* Set physical address of RX status (16-byte aligned). */ 6747 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6748 /* Enable RX. */ 6749 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6750 IWN_FH_RX_CONFIG_ENA | 6751 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6752 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6753 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6754 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 6755 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6756 iwn_nic_unlock(sc); 6757 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6758 6759 if ((error = iwn_nic_lock(sc)) != 0) 6760 return error; 6761 6762 /* Initialize TX scheduler. */ 6763 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6764 6765 /* Set physical address of "keep warm" page (16-byte aligned). */ 6766 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6767 6768 /* Initialize TX rings. */ 6769 for (qid = 0; qid < sc->ntxqs; qid++) { 6770 struct iwn_tx_ring *txq = &sc->txq[qid]; 6771 6772 /* Set physical address of TX ring (256-byte aligned). */ 6773 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6774 txq->desc_dma.paddr >> 8); 6775 } 6776 iwn_nic_unlock(sc); 6777 6778 /* Enable DMA channels. */ 6779 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6780 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6781 IWN_FH_TX_CONFIG_DMA_ENA | 6782 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 6783 } 6784 6785 /* Clear "radio off" and "commands blocked" bits. */ 6786 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6787 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 6788 6789 /* Clear pending interrupts. */ 6790 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6791 /* Enable interrupt coalescing. */ 6792 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 6793 /* Enable interrupts. */ 6794 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6795 6796 /* _Really_ make sure "radio off" bit is cleared! */ 6797 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6798 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 6799 6800 /* Enable shadow registers. */ 6801 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 6802 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 6803 6804 if ((error = ops->load_firmware(sc)) != 0) { 6805 device_printf(sc->sc_dev, 6806 "%s: could not load firmware, error %d\n", __func__, 6807 error); 6808 return error; 6809 } 6810 /* Wait at most one second for firmware alive notification. */ 6811 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 6812 device_printf(sc->sc_dev, 6813 "%s: timeout waiting for adapter to initialize, error %d\n", 6814 __func__, error); 6815 return error; 6816 } 6817 /* Do post-firmware initialization. */ 6818 return ops->post_alive(sc); 6819} 6820 6821static void 6822iwn_hw_stop(struct iwn_softc *sc) 6823{ 6824 int chnl, qid, ntries; 6825 6826 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 6827 6828 /* Disable interrupts. */ 6829 IWN_WRITE(sc, IWN_INT_MASK, 0); 6830 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6831 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 6832 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6833 6834 /* Make sure we no longer hold the NIC lock. */ 6835 iwn_nic_unlock(sc); 6836 6837 /* Stop TX scheduler. */ 6838 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6839 6840 /* Stop all DMA channels. */ 6841 if (iwn_nic_lock(sc) == 0) { 6842 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6843 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 6844 for (ntries = 0; ntries < 200; ntries++) { 6845 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 6846 IWN_FH_TX_STATUS_IDLE(chnl)) 6847 break; 6848 DELAY(10); 6849 } 6850 } 6851 iwn_nic_unlock(sc); 6852 } 6853 6854 /* Stop RX ring. */ 6855 iwn_reset_rx_ring(sc, &sc->rxq); 6856 6857 /* Reset all TX rings. */ 6858 for (qid = 0; qid < sc->ntxqs; qid++) 6859 iwn_reset_tx_ring(sc, &sc->txq[qid]); 6860 6861 if (iwn_nic_lock(sc) == 0) { 6862 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 6863 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6864 iwn_nic_unlock(sc); 6865 } 6866 DELAY(5); 6867 /* Power OFF adapter. */ 6868 iwn_apm_stop(sc); 6869} 6870 6871static void 6872iwn_radio_on(void *arg0, int pending) 6873{ 6874 struct iwn_softc *sc = arg0; 6875 struct ifnet *ifp = sc->sc_ifp; 6876 struct ieee80211com *ic = ifp->if_l2com; 6877 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6878 6879 if (vap != NULL) { 6880 iwn_init(sc); 6881 ieee80211_init(vap); 6882 } 6883} 6884 6885static void 6886iwn_radio_off(void *arg0, int pending) 6887{ 6888 struct iwn_softc *sc = arg0; 6889 struct ifnet *ifp = sc->sc_ifp; 6890 struct ieee80211com *ic = ifp->if_l2com; 6891 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6892 6893 iwn_stop(sc); 6894 if (vap != NULL) 6895 ieee80211_stop(vap); 6896 6897 /* Enable interrupts to get RF toggle notification. */ 6898 IWN_LOCK(sc); 6899 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6900 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6901 IWN_UNLOCK(sc); 6902} 6903 6904static void 6905iwn_init_locked(struct iwn_softc *sc) 6906{ 6907 struct ifnet *ifp = sc->sc_ifp; 6908 int error; 6909 6910 IWN_LOCK_ASSERT(sc); 6911 6912 if ((error = iwn_hw_prepare(sc)) != 0) { 6913 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 6914 __func__, error); 6915 goto fail; 6916 } 6917 6918 /* Initialize interrupt mask to default value. */ 6919 sc->int_mask = IWN_INT_MASK_DEF; 6920 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 6921 6922 /* Check that the radio is not disabled by hardware switch. */ 6923 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 6924 device_printf(sc->sc_dev, 6925 "radio is disabled by hardware switch\n"); 6926 /* Enable interrupts to get RF toggle notifications. */ 6927 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6928 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 6929 return; 6930 } 6931 6932 /* Read firmware images from the filesystem. */ 6933 if ((error = iwn_read_firmware(sc)) != 0) { 6934 device_printf(sc->sc_dev, 6935 "%s: could not read firmware, error %d\n", __func__, 6936 error); 6937 goto fail; 6938 } 6939 6940 /* Initialize hardware and upload firmware. */ 6941 error = iwn_hw_init(sc); 6942 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 6943 sc->fw_fp = NULL; 6944 if (error != 0) { 6945 device_printf(sc->sc_dev, 6946 "%s: could not initialize hardware, error %d\n", __func__, 6947 error); 6948 goto fail; 6949 } 6950 6951 /* Configure adapter now that it is ready. */ 6952 if ((error = iwn_config(sc)) != 0) { 6953 device_printf(sc->sc_dev, 6954 "%s: could not configure device, error %d\n", __func__, 6955 error); 6956 goto fail; 6957 } 6958 6959 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6960 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6961 6962 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 6963 return; 6964 6965fail: iwn_stop_locked(sc); 6966} 6967 6968static void 6969iwn_init(void *arg) 6970{ 6971 struct iwn_softc *sc = arg; 6972 struct ifnet *ifp = sc->sc_ifp; 6973 struct ieee80211com *ic = ifp->if_l2com; 6974 6975 IWN_LOCK(sc); 6976 iwn_init_locked(sc); 6977 IWN_UNLOCK(sc); 6978 6979 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6980 ieee80211_start_all(ic); 6981} 6982 6983static void 6984iwn_stop_locked(struct iwn_softc *sc) 6985{ 6986 struct ifnet *ifp = sc->sc_ifp; 6987 6988 IWN_LOCK_ASSERT(sc); 6989 6990 sc->sc_tx_timer = 0; 6991 callout_stop(&sc->watchdog_to); 6992 callout_stop(&sc->calib_to); 6993 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6994 6995 /* Power OFF hardware. */ 6996 iwn_hw_stop(sc); 6997} 6998 6999static void 7000iwn_stop(struct iwn_softc *sc) 7001{ 7002 IWN_LOCK(sc); 7003 iwn_stop_locked(sc); 7004 IWN_UNLOCK(sc); 7005} 7006 7007/* 7008 * Callback from net80211 to start a scan. 7009 */ 7010static void 7011iwn_scan_start(struct ieee80211com *ic) 7012{ 7013 struct ifnet *ifp = ic->ic_ifp; 7014 struct iwn_softc *sc = ifp->if_softc; 7015 7016 IWN_LOCK(sc); 7017 /* make the link LED blink while we're scanning */ 7018 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 7019 IWN_UNLOCK(sc); 7020} 7021 7022/* 7023 * Callback from net80211 to terminate a scan. 7024 */ 7025static void 7026iwn_scan_end(struct ieee80211com *ic) 7027{ 7028 struct ifnet *ifp = ic->ic_ifp; 7029 struct iwn_softc *sc = ifp->if_softc; 7030 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 7031 7032 IWN_LOCK(sc); 7033 if (vap->iv_state == IEEE80211_S_RUN) { 7034 /* Set link LED to ON status if we are associated */ 7035 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 7036 } 7037 IWN_UNLOCK(sc); 7038} 7039 7040/* 7041 * Callback from net80211 to force a channel change. 7042 */ 7043static void 7044iwn_set_channel(struct ieee80211com *ic) 7045{ 7046 const struct ieee80211_channel *c = ic->ic_curchan; 7047 struct ifnet *ifp = ic->ic_ifp; 7048 struct iwn_softc *sc = ifp->if_softc; 7049 int error; 7050 7051 IWN_LOCK(sc); 7052 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 7053 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 7054 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 7055 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 7056 7057 /* 7058 * Only need to set the channel in Monitor mode. AP scanning and auth 7059 * are already taken care of by their respective firmware commands. 7060 */ 7061 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 7062 error = iwn_config(sc); 7063 if (error != 0) 7064 device_printf(sc->sc_dev, 7065 "%s: error %d settting channel\n", __func__, error); 7066 } 7067 IWN_UNLOCK(sc); 7068} 7069 7070/* 7071 * Callback from net80211 to start scanning of the current channel. 7072 */ 7073static void 7074iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 7075{ 7076 struct ieee80211vap *vap = ss->ss_vap; 7077 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 7078 int error; 7079 7080 IWN_LOCK(sc); 7081 error = iwn_scan(sc); 7082 IWN_UNLOCK(sc); 7083 if (error != 0) 7084 ieee80211_cancel_scan(vap); 7085} 7086 7087/* 7088 * Callback from net80211 to handle the minimum dwell time being met. 7089 * The intent is to terminate the scan but we just let the firmware 7090 * notify us when it's finished as we have no safe way to abort it. 7091 */ 7092static void 7093iwn_scan_mindwell(struct ieee80211_scan_state *ss) 7094{ 7095 /* NB: don't try to abort scan; wait for firmware to finish */ 7096} 7097 7098static void 7099iwn_hw_reset(void *arg0, int pending) 7100{ 7101 struct iwn_softc *sc = arg0; 7102 struct ifnet *ifp = sc->sc_ifp; 7103 struct ieee80211com *ic = ifp->if_l2com; 7104 7105 iwn_stop(sc); 7106 iwn_init(sc); 7107 ieee80211_notify_radio(ic, 1); 7108} 7109