1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD$
18 */
19#ifndef _ATH_AH_DECODE_H_
20#define _ATH_AH_DECODE_H_
21/*
22 * Register tracing support.
23 *
24 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
25 * writes to the file /tmp/ath_hal.log.  The file format is a simple
26 * fixed-size array of records.  When done logging set hw.ath.hal.alq=0
27 * and then decode the file with the arcode program (that is part of the
28 * HAL).  If you start+stop tracing the data will be appended to an
29 * existing file.
30 */
31struct athregrec {
32	uint32_t	op	: 8,
33			reg	: 24;
34	uint32_t	val;
35};
36
37enum {
38	OP_READ		= 0,		/* register read */
39	OP_WRITE	= 1,		/* register write */
40	OP_DEVICE	= 2,		/* device identification */
41	OP_MARK		= 3,		/* application marker */
42};
43
44enum {
45	AH_MARK_RESET,			/* ar*Reset entry, bChannelChange */
46	AH_MARK_RESET_LINE,		/* ar*_reset.c, line %d */
47	AH_MARK_RESET_DONE,		/* ar*Reset exit, error code */
48	AH_MARK_CHIPRESET,		/* ar*ChipReset, channel num */
49	AH_MARK_PERCAL,			/* ar*PerCalibration, channel num */
50	AH_MARK_SETCHANNEL,		/* ar*SetChannel, channel num */
51	AH_MARK_ANI_RESET,		/* ar*AniReset, opmode */
52	AH_MARK_ANI_POLL,		/* ar*AniReset, listen time */
53	AH_MARK_ANI_CONTROL,		/* ar*AniReset, cmd */
54	AH_MARK_RX_CTL,			/* RX DMA control */
55};
56
57enum {
58	AH_MARK_RX_CTL_PCU_START,
59	AH_MARK_RX_CTL_PCU_STOP,
60	AH_MARK_RX_CTL_DMA_START,
61	AH_MARK_RX_CTL_DMA_STOP,
62	AH_MARK_RX_CTL_DMA_STOP_ERR,
63};
64
65#endif /* _ATH_AH_DECODE_H_ */
66