1/*
2 *	SiS 190/191 NIC Driver.
3 *	Copyright (c) 2009 S.Zharski <imker@gmx.li>
4 *	Distributed under the terms of the MIT license.
5 *
6 */
7#ifndef _SiS19X_REGISTERS_H_
8#define _SiS19X_REGISTERS_H_
9
10
11// Symbolic offset to registers
12enum SiS19XRegisters {
13	TxControl		= 0x00,	// Tx Host Control / Status
14	TxBase			= 0x04,	// Tx Home Descriptor Base
15	TxReserved		= 0x08,	// Reserved
16	TxStatus		= 0x0c,	// Tx Next Descriptor Control / Status
17	RxControl		= 0x10,	// Rx Host Control / Status
18	RxBase			= 0x14,	// Rx Home Descriptor Base
19	RxReserved		= 0x18,	// Reserved
20	RxStatus		= 0x1c,	// Rx Next Descriptor Control / Status
21	IntSource		= 0x20,	// Interrupt Source
22	IntMask			= 0x24,	// Interrupt Mask
23	IntControl		= 0x28,	// Interrupt Control
24	IntTimer		= 0x2c,	// Interrupt Timer
25	PowControl		= 0x30,	// Power Management Control / Status
26	Reserved0		= 0x34,	// Reserved
27	EEPROMControl	= 0x38,	// EEPROM Control / Status
28	EEPROMInterface	= 0x3c,	// EEPROM Interface
29	StationControl	= 0x40,	// Station Control / Status
30	SMInterface		= 0x44,	// Station Management Interface
31	GIoCR			= 0x48,	// GMAC IO Compensation
32	GIoControl		= 0x4c,	// GMAC IO Control
33	TxMACControl	= 0x50,	// Tx MAC Control
34	TxLimit			= 0x54,	// Tx MAC Timer / TryLimit
35	RGDelay			= 0x58,	// RGMII Tx Internal Delay Control
36	Reserved1		= 0x5c,	// Reserved
37	RxMACControl	= 0x60,	// Rx MAC Control
38	RxMACAddress	= 0x62,	// Rx MAC Unicast Address
39	RxHashTable		= 0x68,	// Rx Multicast Hash Table
40	RxWOLControl	= 0x70,	// Rx WOL Control
41	RxWOLData		= 0x74,	// Rx WOL Data Access
42	RxMPSControl	= 0x78,	// Rx MPS Control
43	Reserved2		= 0x7c	// Reserved
44};
45
46
47// interrupt bits for IMR/ISR registers
48enum SiS19XInterruptBits {
49	INT_SOFT	= 0x40000000U,
50	INT_TIMER	= 0x20000000U,
51	INT_PAUSEF	= 0x00080000U,
52	INT_MAGICP	= 0x00040000U,
53	INT_WAKEF	= 0x00020000U,
54	INT_LINK	= 0x00010000U,
55	INT_RXIDLE	= 0x00000080U,
56	INT_RXDONE	= 0x00000040U,
57	INT_TXIDLE	= 0x00000008U,
58	INT_TXDONE	= 0x00000004U,
59	INT_RXHALT	= 0x00000002U,
60	INT_TXHALT	= 0x00000001U
61};
62
63
64const uint32 knownInterruptsMask = INT_LINK
65								/*| INT_RXIDLE*/ | INT_RXDONE
66								/*| INT_TXIDLE*/ | INT_TXDONE
67								| INT_RXHALT | INT_TXHALT;
68
69
70// bits for RxControl register
71enum SiS19XRxControlBits {
72	RxControlPoll	= 0x00000010U,
73	RxControlEnable	= 0x00000001U
74};
75
76
77// bits for TxControl register
78enum SiS19XTxControlBits {
79	TxControlPoll	= 0x00000010U,
80	TxControlEnable	= 0x00000001U
81};
82
83
84// EEPROM Addresses
85enum SiS19XEEPROMAddress {
86	EEPROMSignature	= 0x00,
87	EEPROMClock		= 0x01,
88	EEPROMInfo		= 0x02,
89	EEPROMAddress	= 0x03
90};
91
92
93// EEPROM Interface Register
94enum SiS19XEEPROMInterface {
95	EIData			= 0xffff0000,
96	EIDataShift		= 16,
97	EIOffset		= 0x0000fc00,
98	EIOffsetShift	= 10,
99	EIOp			= 0x00000300,
100	EIOpShift		= 8,
101	EIOpRead		= (2 << EIOpShift),
102	EIOpWrite		= (1 << EIOpShift),
103	EIReq			= 0x00000080,
104	EI_DO			= 0x00000008,
105	EI_DI			= 0x00000004,
106	EIClock			= 0x00000002,
107	EI_CS			= 0x00000001,
108
109	EIInvalid		= 0xffff	// used as invalid readout from EEPROM
110};
111
112
113// interrupt bits for Station Control registers
114enum SiS19XStationControlBits {
115	SC_Loopback		= 0x80000000U,
116	SC_RGMII		= 0x00008000U,
117	SC_FullDuplex	= 0x00001000U,
118	SC_Speed		= 0x00000c00U,
119	SC_SpeedShift	= 10,
120	SC_Speed1000	= (3U << SC_SpeedShift),
121	SC_Speed100		= (2U << SC_SpeedShift),
122	SC_Speed10		= (1U << SC_SpeedShift)
123};
124
125
126// Station Management Interface Register
127enum SiS19XSMInterface {
128	SMIData			= 0xffff0000,
129	SMIDataShift	= 16,
130	SMIReg			= 0x0000f800,
131	SMIRegShift		= 11,
132	SMIPHY			= 0x000007c0,
133	SMIPHYShift		= 6,
134	SMIOp			= 0x00000020,
135	SMIOpShift		= 5,
136	SMIOpWrite		= (1 << SMIOpShift),
137	SMIOpRead		= (0 << SMIOpShift),
138	SMIReq			= 0x00000010,
139	SMI_MDIO		= 0x00000008,
140	SMI_MDDIR		= 0x00000004,
141	SMI_MDC			= 0x00000002,
142	SMI_MDEN		= 0x00000001
143};
144
145
146// transmit descriptor command bits
147enum TxDescriptorCommandStatus {
148	TDC_TXOWN	= 0x80000000U, // own bit
149	TDC_TXINT	= 0x40000000U,
150	TDC_THOL3	= 0x30000000U,
151	TDC_THOL2	= 0x20000000U,
152	TDC_THOL1	= 0x10000000U,
153	TDC_THOL0	= 0x00000000U,
154	TDC_LSEN	= 0x08000000U,
155	TDC_IPCS	= 0x04000000U,
156	TDC_TCPCS	= 0x02000000U,
157	TDC_UDPCS	= 0x01000000U,
158	TDC_BSTEN	= 0x00800000U,
159	TDC_EXTEN	= 0x00400000U,
160	TDC_DEFEN	= 0x00200000U,
161	TDC_BKFEN	= 0x00100000U,
162	TDC_CRSEN	= 0x00080000U,
163	TDC_COLSEN	= 0x00040000U,
164	TDC_CRCEN	= 0x00020000U,
165	TDC_PADEN	= 0x00010000U,
166	// following bits are set/filled by hardware?
167	TDS_OWC		= 0x00080000U,
168	TDS_ABT		= 0x00040000U,
169	TDS_FIFO	= 0x00020000U,
170	TDS_CRS		= 0x00010000U,
171	TDS_COLLS	= 0x0000ffffU
172};
173
174
175const uint32 txErrorStatusBits = TDS_OWC | TDS_ABT | TDS_FIFO | TDS_CRS;
176const uint32 TxDescriptorEOD = 0x80000000U;
177const uint32 TxDescriptorSize = 0x0000ffffU;
178
179
180struct TxDescriptor {
181	uint32		fPacketSize;
182	uint32		fCommandStatus;
183	uint32		fBufferPointer;
184	uint32		fEOD;
185
186	void		Init(phys_addr_t bufferPointer, bool bEOD) volatile {
187		fPacketSize = 0;
188		fCommandStatus = 0;
189		fBufferPointer = (uint32)bufferPointer;
190		fEOD = bEOD ? TxDescriptorEOD : 0;
191	}
192};
193
194
195// receive descriptor information bits
196enum RxDescriptorInformation {
197	RDI_RXOWN	= 0x80000000U,
198	RDI_RXINT	= 0x40000000U,
199	RDI_IPON	= 0x20000000U,
200	RDI_TCPON	= 0x10000000U,
201	RDI_UDPON	= 0x08000000U,
202	RDI_WAKUP	= 0x00400000U,
203	RDI_MAGIC	= 0x00200000U,
204	RDI_PAUSE	= 0x00100000U,
205	RDI_CAST	= 0x000c0000U,
206		RDI_CAST_SHIFT	= 18,
207	RDI_BCAST	= ( 3U << RDI_CAST_SHIFT ),
208	RDI_MCAST	= ( 2U << RDI_CAST_SHIFT ),
209	RDI_UCAST	= ( 1U << RDI_CAST_SHIFT ),
210	RDI_CRCOFF	= 0x00020000U,
211	RDI_PREADD	= 0x00010000U
212};
213
214
215// receive descriptor status bits
216enum RxDescriptorStatus {
217	RDS_TAGON	= 0x80000000U,
218	RDS_DESCS	= 0x3f000000U,
219		RDS_DESCS_SHIFT	= 24,
220	RDS_ABORT	= 0x00800000U,
221	RDS_SHORT	= 0x00400000U,
222	RDS_LIMIT	= 0x00200000U,
223	RDS_MIIER	= 0x00100000U,
224	RDS_OVRUN	= 0x00080000U,
225	RDS_NIBON	= 0x00040000U,
226	RDS_COLON	= 0x00020000U,
227	RDS_CRCOK	= 0x00010000U,
228	RDS_SIZE	= 0x0000ffffU
229};
230
231
232const uint32 rxErrorStatusBits = RDS_ABORT | RDS_SHORT | RDS_LIMIT
233							| RDS_MIIER | RDS_OVRUN | RDS_NIBON | RDS_COLON;
234const uint32 RxDescriptorEOD = 0x80000000U;
235const uint32 BufferSize = 1536;
236
237struct RxDescriptor {
238	uint32		fStatusSize;
239	uint32		fPacketInfo;
240	uint32		fBufferPointer;
241	uint32		fEOD;
242
243	void Init(phys_addr_t bufferPointer, bool isEOD) volatile {
244		fStatusSize = 0;
245		fPacketInfo = RDI_RXOWN | RDI_RXINT;
246		fBufferPointer =(uint32) bufferPointer;
247		fEOD = isEOD ? RxDescriptorEOD : 0;
248		fEOD |= (BufferSize & 0x0000fff8);
249	}
250};
251
252
253// RxMACControl bits
254enum RxMACControlBits {
255	RXM_Broadcast	= 0x0800U,
256	RXM_Multicast	= 0x0400U,
257	RXM_Physical	= 0x0200U,
258	RXM_AllPhysical	= 0x0100U,
259
260	RXM_Mask		= RXM_Broadcast | RXM_Multicast
261						| RXM_Physical | RXM_AllPhysical
262};
263
264#endif // _SiS19X_REGISTERS_H_
265
266