1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/sysctl.h> 127#include <sys/taskqueue.h> 128 129#include <net/if.h> 130#include <net/if_arp.h> 131#include <net/ethernet.h> 132#include <net/if_dl.h> 133#include <net/if_media.h> 134#include <net/if_types.h> 135#include <net/if_vlan_var.h> 136 137#include <net/bpf.h> 138 139#include <machine/bus.h> 140#include <machine/resource.h> 141#include <sys/bus.h> 142#include <sys/rman.h> 143 144#include <dev/mii/mii.h> 145#include <dev/mii/miivar.h> 146 147#include <dev/pci/pcireg.h> 148#include <dev/pci/pcivar.h> 149 150#include <pci/if_rlreg.h> 151 152MODULE_DEPEND(re, pci, 1, 1, 1); 153MODULE_DEPEND(re, ether, 1, 1, 1); 154MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156/* "device miibus" required. See GENERIC if you get errors here. */ 157#include "miibus_if.h" 158 159/* Tunables. */ 160static int intr_filter = 0; 161TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162static int msi_disable = 0; 163TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164static int msix_disable = 0; 165TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166static int prefer_iomap = 0; 167TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171/* 172 * Various supported device vendors/types and their names. 173 */ 174static const struct rl_type const re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195}; 196 197static const struct rl_hwrev const re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 237 { 0, 0, NULL, 0 } 238}; 239 240static int re_probe (device_t); 241static int re_attach (device_t); 242static int re_detach (device_t); 243 244static int re_encap (struct rl_softc *, struct mbuf **); 245 246static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 247static int re_allocmem (device_t, struct rl_softc *); 248static __inline void re_discard_rxbuf 249 (struct rl_softc *, int); 250static int re_newbuf (struct rl_softc *, int); 251static int re_jumbo_newbuf (struct rl_softc *, int); 252static int re_rx_list_init (struct rl_softc *); 253static int re_jrx_list_init (struct rl_softc *); 254static int re_tx_list_init (struct rl_softc *); 255#ifdef RE_FIXUP_RX 256static __inline void re_fixup_rx 257 (struct mbuf *); 258#endif 259static int re_rxeof (struct rl_softc *, int *); 260static void re_txeof (struct rl_softc *); 261#ifdef DEVICE_POLLING 262static int re_poll (struct ifnet *, enum poll_cmd, int); 263static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 264#endif 265static int re_intr (void *); 266static void re_intr_msi (void *); 267static void re_tick (void *); 268static void re_int_task (void *, int); 269static void re_start (struct ifnet *); 270static void re_start_locked (struct ifnet *); 271static int re_ioctl (struct ifnet *, u_long, caddr_t); 272static void re_init (void *); 273static void re_init_locked (struct rl_softc *); 274static void re_stop (struct rl_softc *); 275static void re_watchdog (struct rl_softc *); 276static int re_suspend (device_t); 277static int re_resume (device_t); 278static int re_shutdown (device_t); 279static int re_ifmedia_upd (struct ifnet *); 280static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 281 282static void re_eeprom_putbyte (struct rl_softc *, int); 283static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 284static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 285static int re_gmii_readreg (device_t, int, int); 286static int re_gmii_writereg (device_t, int, int, int); 287 288static int re_miibus_readreg (device_t, int, int); 289static int re_miibus_writereg (device_t, int, int, int); 290static void re_miibus_statchg (device_t); 291 292static void re_set_jumbo (struct rl_softc *, int); 293static void re_set_rxmode (struct rl_softc *); 294static void re_reset (struct rl_softc *); 295static void re_setwol (struct rl_softc *); 296static void re_clrwol (struct rl_softc *); 297static void re_set_linkspeed (struct rl_softc *); 298 299#ifdef DEV_NETMAP /* see ixgbe.c for details */ 300#include <dev/netmap/if_re_netmap.h> 301#endif /* !DEV_NETMAP */ 302 303#ifdef RE_DIAG 304static int re_diag (struct rl_softc *); 305#endif 306 307static void re_add_sysctls (struct rl_softc *); 308static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 309static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 310static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 311 312static device_method_t re_methods[] = { 313 /* Device interface */ 314 DEVMETHOD(device_probe, re_probe), 315 DEVMETHOD(device_attach, re_attach), 316 DEVMETHOD(device_detach, re_detach), 317 DEVMETHOD(device_suspend, re_suspend), 318 DEVMETHOD(device_resume, re_resume), 319 DEVMETHOD(device_shutdown, re_shutdown), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, re_miibus_readreg), 323 DEVMETHOD(miibus_writereg, re_miibus_writereg), 324 DEVMETHOD(miibus_statchg, re_miibus_statchg), 325 326 DEVMETHOD_END 327}; 328 329static driver_t re_driver = { 330 "re", 331 re_methods, 332 sizeof(struct rl_softc) 333}; 334 335static devclass_t re_devclass; 336 337DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 338DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 339 340#define EE_SET(x) \ 341 CSR_WRITE_1(sc, RL_EECMD, \ 342 CSR_READ_1(sc, RL_EECMD) | x) 343 344#define EE_CLR(x) \ 345 CSR_WRITE_1(sc, RL_EECMD, \ 346 CSR_READ_1(sc, RL_EECMD) & ~x) 347 348/* 349 * Send a read command and address to the EEPROM, check for ACK. 350 */ 351static void 352re_eeprom_putbyte(struct rl_softc *sc, int addr) 353{ 354 int d, i; 355 356 d = addr | (RL_9346_READ << sc->rl_eewidth); 357 358 /* 359 * Feed in each bit and strobe the clock. 360 */ 361 362 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 363 if (d & i) { 364 EE_SET(RL_EE_DATAIN); 365 } else { 366 EE_CLR(RL_EE_DATAIN); 367 } 368 DELAY(100); 369 EE_SET(RL_EE_CLK); 370 DELAY(150); 371 EE_CLR(RL_EE_CLK); 372 DELAY(100); 373 } 374} 375 376/* 377 * Read a word of data stored in the EEPROM at address 'addr.' 378 */ 379static void 380re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 381{ 382 int i; 383 u_int16_t word = 0; 384 385 /* 386 * Send address of word we want to read. 387 */ 388 re_eeprom_putbyte(sc, addr); 389 390 /* 391 * Start reading bits from EEPROM. 392 */ 393 for (i = 0x8000; i; i >>= 1) { 394 EE_SET(RL_EE_CLK); 395 DELAY(100); 396 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 397 word |= i; 398 EE_CLR(RL_EE_CLK); 399 DELAY(100); 400 } 401 402 *dest = word; 403} 404 405/* 406 * Read a sequence of words from the EEPROM. 407 */ 408static void 409re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 410{ 411 int i; 412 u_int16_t word = 0, *ptr; 413 414 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 415 416 DELAY(100); 417 418 for (i = 0; i < cnt; i++) { 419 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 420 re_eeprom_getword(sc, off + i, &word); 421 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 422 ptr = (u_int16_t *)(dest + (i * 2)); 423 *ptr = word; 424 } 425 426 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 427} 428 429static int 430re_gmii_readreg(device_t dev, int phy, int reg) 431{ 432 struct rl_softc *sc; 433 u_int32_t rval; 434 int i; 435 436 sc = device_get_softc(dev); 437 438 /* Let the rgephy driver read the GMEDIASTAT register */ 439 440 if (reg == RL_GMEDIASTAT) { 441 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 442 return (rval); 443 } 444 445 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 446 447 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 448 rval = CSR_READ_4(sc, RL_PHYAR); 449 if (rval & RL_PHYAR_BUSY) 450 break; 451 DELAY(25); 452 } 453 454 if (i == RL_PHY_TIMEOUT) { 455 device_printf(sc->rl_dev, "PHY read failed\n"); 456 return (0); 457 } 458 459 /* 460 * Controller requires a 20us delay to process next MDIO request. 461 */ 462 DELAY(20); 463 464 return (rval & RL_PHYAR_PHYDATA); 465} 466 467static int 468re_gmii_writereg(device_t dev, int phy, int reg, int data) 469{ 470 struct rl_softc *sc; 471 u_int32_t rval; 472 int i; 473 474 sc = device_get_softc(dev); 475 476 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 477 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 478 479 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 480 rval = CSR_READ_4(sc, RL_PHYAR); 481 if (!(rval & RL_PHYAR_BUSY)) 482 break; 483 DELAY(25); 484 } 485 486 if (i == RL_PHY_TIMEOUT) { 487 device_printf(sc->rl_dev, "PHY write failed\n"); 488 return (0); 489 } 490 491 /* 492 * Controller requires a 20us delay to process next MDIO request. 493 */ 494 DELAY(20); 495 496 return (0); 497} 498 499static int 500re_miibus_readreg(device_t dev, int phy, int reg) 501{ 502 struct rl_softc *sc; 503 u_int16_t rval = 0; 504 u_int16_t re8139_reg = 0; 505 506 sc = device_get_softc(dev); 507 508 if (sc->rl_type == RL_8169) { 509 rval = re_gmii_readreg(dev, phy, reg); 510 return (rval); 511 } 512 513 switch (reg) { 514 case MII_BMCR: 515 re8139_reg = RL_BMCR; 516 break; 517 case MII_BMSR: 518 re8139_reg = RL_BMSR; 519 break; 520 case MII_ANAR: 521 re8139_reg = RL_ANAR; 522 break; 523 case MII_ANER: 524 re8139_reg = RL_ANER; 525 break; 526 case MII_ANLPAR: 527 re8139_reg = RL_LPAR; 528 break; 529 case MII_PHYIDR1: 530 case MII_PHYIDR2: 531 return (0); 532 /* 533 * Allow the rlphy driver to read the media status 534 * register. If we have a link partner which does not 535 * support NWAY, this is the register which will tell 536 * us the results of parallel detection. 537 */ 538 case RL_MEDIASTAT: 539 rval = CSR_READ_1(sc, RL_MEDIASTAT); 540 return (rval); 541 default: 542 device_printf(sc->rl_dev, "bad phy register\n"); 543 return (0); 544 } 545 rval = CSR_READ_2(sc, re8139_reg); 546 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 547 /* 8139C+ has different bit layout. */ 548 rval &= ~(BMCR_LOOP | BMCR_ISO); 549 } 550 return (rval); 551} 552 553static int 554re_miibus_writereg(device_t dev, int phy, int reg, int data) 555{ 556 struct rl_softc *sc; 557 u_int16_t re8139_reg = 0; 558 int rval = 0; 559 560 sc = device_get_softc(dev); 561 562 if (sc->rl_type == RL_8169) { 563 rval = re_gmii_writereg(dev, phy, reg, data); 564 return (rval); 565 } 566 567 switch (reg) { 568 case MII_BMCR: 569 re8139_reg = RL_BMCR; 570 if (sc->rl_type == RL_8139CPLUS) { 571 /* 8139C+ has different bit layout. */ 572 data &= ~(BMCR_LOOP | BMCR_ISO); 573 } 574 break; 575 case MII_BMSR: 576 re8139_reg = RL_BMSR; 577 break; 578 case MII_ANAR: 579 re8139_reg = RL_ANAR; 580 break; 581 case MII_ANER: 582 re8139_reg = RL_ANER; 583 break; 584 case MII_ANLPAR: 585 re8139_reg = RL_LPAR; 586 break; 587 case MII_PHYIDR1: 588 case MII_PHYIDR2: 589 return (0); 590 break; 591 default: 592 device_printf(sc->rl_dev, "bad phy register\n"); 593 return (0); 594 } 595 CSR_WRITE_2(sc, re8139_reg, data); 596 return (0); 597} 598 599static void 600re_miibus_statchg(device_t dev) 601{ 602 struct rl_softc *sc; 603 struct ifnet *ifp; 604 struct mii_data *mii; 605 606 sc = device_get_softc(dev); 607 mii = device_get_softc(sc->rl_miibus); 608 ifp = sc->rl_ifp; 609 if (mii == NULL || ifp == NULL || 610 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 611 return; 612 613 sc->rl_flags &= ~RL_FLAG_LINK; 614 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 615 (IFM_ACTIVE | IFM_AVALID)) { 616 switch (IFM_SUBTYPE(mii->mii_media_active)) { 617 case IFM_10_T: 618 case IFM_100_TX: 619 sc->rl_flags |= RL_FLAG_LINK; 620 break; 621 case IFM_1000_T: 622 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 623 break; 624 sc->rl_flags |= RL_FLAG_LINK; 625 break; 626 default: 627 break; 628 } 629 } 630 /* 631 * RealTek controllers does not provide any interface to 632 * Tx/Rx MACs for resolved speed, duplex and flow-control 633 * parameters. 634 */ 635} 636 637/* 638 * Set the RX configuration and 64-bit multicast hash filter. 639 */ 640static void 641re_set_rxmode(struct rl_softc *sc) 642{ 643 struct ifnet *ifp; 644 struct ifmultiaddr *ifma; 645 uint32_t hashes[2] = { 0, 0 }; 646 uint32_t h, rxfilt; 647 648 RL_LOCK_ASSERT(sc); 649 650 ifp = sc->rl_ifp; 651 652 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 653 654 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 655 if (ifp->if_flags & IFF_PROMISC) 656 rxfilt |= RL_RXCFG_RX_ALLPHYS; 657 /* 658 * Unlike other hardwares, we have to explicitly set 659 * RL_RXCFG_RX_MULTI to receive multicast frames in 660 * promiscuous mode. 661 */ 662 rxfilt |= RL_RXCFG_RX_MULTI; 663 hashes[0] = hashes[1] = 0xffffffff; 664 goto done; 665 } 666 667 if_maddr_rlock(ifp); 668 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 669 if (ifma->ifma_addr->sa_family != AF_LINK) 670 continue; 671 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 672 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 673 if (h < 32) 674 hashes[0] |= (1 << h); 675 else 676 hashes[1] |= (1 << (h - 32)); 677 } 678 if_maddr_runlock(ifp); 679 680 if (hashes[0] != 0 || hashes[1] != 0) { 681 /* 682 * For some unfathomable reason, RealTek decided to 683 * reverse the order of the multicast hash registers 684 * in the PCI Express parts. This means we have to 685 * write the hash pattern in reverse order for those 686 * devices. 687 */ 688 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 689 h = bswap32(hashes[0]); 690 hashes[0] = bswap32(hashes[1]); 691 hashes[1] = h; 692 } 693 rxfilt |= RL_RXCFG_RX_MULTI; 694 } 695 696done: 697 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 698 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 699 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 700} 701 702static void 703re_reset(struct rl_softc *sc) 704{ 705 int i; 706 707 RL_LOCK_ASSERT(sc); 708 709 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 710 711 for (i = 0; i < RL_TIMEOUT; i++) { 712 DELAY(10); 713 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 714 break; 715 } 716 if (i == RL_TIMEOUT) 717 device_printf(sc->rl_dev, "reset never completed!\n"); 718 719 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 720 CSR_WRITE_1(sc, 0x82, 1); 721 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 722 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 723} 724 725#ifdef RE_DIAG 726 727/* 728 * The following routine is designed to test for a defect on some 729 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 730 * lines connected to the bus, however for a 32-bit only card, they 731 * should be pulled high. The result of this defect is that the 732 * NIC will not work right if you plug it into a 64-bit slot: DMA 733 * operations will be done with 64-bit transfers, which will fail 734 * because the 64-bit data lines aren't connected. 735 * 736 * There's no way to work around this (short of talking a soldering 737 * iron to the board), however we can detect it. The method we use 738 * here is to put the NIC into digital loopback mode, set the receiver 739 * to promiscuous mode, and then try to send a frame. We then compare 740 * the frame data we sent to what was received. If the data matches, 741 * then the NIC is working correctly, otherwise we know the user has 742 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 743 * slot. In the latter case, there's no way the NIC can work correctly, 744 * so we print out a message on the console and abort the device attach. 745 */ 746 747static int 748re_diag(struct rl_softc *sc) 749{ 750 struct ifnet *ifp = sc->rl_ifp; 751 struct mbuf *m0; 752 struct ether_header *eh; 753 struct rl_desc *cur_rx; 754 u_int16_t status; 755 u_int32_t rxstat; 756 int total_len, i, error = 0, phyaddr; 757 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 758 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 759 760 /* Allocate a single mbuf */ 761 MGETHDR(m0, M_DONTWAIT, MT_DATA); 762 if (m0 == NULL) 763 return (ENOBUFS); 764 765 RL_LOCK(sc); 766 767 /* 768 * Initialize the NIC in test mode. This sets the chip up 769 * so that it can send and receive frames, but performs the 770 * following special functions: 771 * - Puts receiver in promiscuous mode 772 * - Enables digital loopback mode 773 * - Leaves interrupts turned off 774 */ 775 776 ifp->if_flags |= IFF_PROMISC; 777 sc->rl_testmode = 1; 778 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 779 re_init_locked(sc); 780 sc->rl_flags |= RL_FLAG_LINK; 781 if (sc->rl_type == RL_8169) 782 phyaddr = 1; 783 else 784 phyaddr = 0; 785 786 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 787 for (i = 0; i < RL_TIMEOUT; i++) { 788 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 789 if (!(status & BMCR_RESET)) 790 break; 791 } 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 794 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 795 796 DELAY(100000); 797 798 /* Put some data in the mbuf */ 799 800 eh = mtod(m0, struct ether_header *); 801 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 802 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 803 eh->ether_type = htons(ETHERTYPE_IP); 804 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 805 806 /* 807 * Queue the packet, start transmission. 808 * Note: IF_HANDOFF() ultimately calls re_start() for us. 809 */ 810 811 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 812 RL_UNLOCK(sc); 813 /* XXX: re_diag must not be called when in ALTQ mode */ 814 IF_HANDOFF(&ifp->if_snd, m0, ifp); 815 RL_LOCK(sc); 816 m0 = NULL; 817 818 /* Wait for it to propagate through the chip */ 819 820 DELAY(100000); 821 for (i = 0; i < RL_TIMEOUT; i++) { 822 status = CSR_READ_2(sc, RL_ISR); 823 CSR_WRITE_2(sc, RL_ISR, status); 824 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 825 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 826 break; 827 DELAY(10); 828 } 829 830 if (i == RL_TIMEOUT) { 831 device_printf(sc->rl_dev, 832 "diagnostic failed, failed to receive packet in" 833 " loopback mode\n"); 834 error = EIO; 835 goto done; 836 } 837 838 /* 839 * The packet should have been dumped into the first 840 * entry in the RX DMA ring. Grab it from there. 841 */ 842 843 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 844 sc->rl_ldata.rl_rx_list_map, 845 BUS_DMASYNC_POSTREAD); 846 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 847 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 848 BUS_DMASYNC_POSTREAD); 849 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 850 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 851 852 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 853 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 854 eh = mtod(m0, struct ether_header *); 855 856 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 857 total_len = RL_RXBYTES(cur_rx); 858 rxstat = le32toh(cur_rx->rl_cmdstat); 859 860 if (total_len != ETHER_MIN_LEN) { 861 device_printf(sc->rl_dev, 862 "diagnostic failed, received short packet\n"); 863 error = EIO; 864 goto done; 865 } 866 867 /* Test that the received packet data matches what we sent. */ 868 869 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 870 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 871 ntohs(eh->ether_type) != ETHERTYPE_IP) { 872 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 873 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 874 dst, ":", src, ":", ETHERTYPE_IP); 875 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 876 eh->ether_dhost, ":", eh->ether_shost, ":", 877 ntohs(eh->ether_type)); 878 device_printf(sc->rl_dev, "You may have a defective 32-bit " 879 "NIC plugged into a 64-bit PCI slot.\n"); 880 device_printf(sc->rl_dev, "Please re-install the NIC in a " 881 "32-bit slot for proper operation.\n"); 882 device_printf(sc->rl_dev, "Read the re(4) man page for more " 883 "details.\n"); 884 error = EIO; 885 } 886 887done: 888 /* Turn interface off, release resources */ 889 890 sc->rl_testmode = 0; 891 sc->rl_flags &= ~RL_FLAG_LINK; 892 ifp->if_flags &= ~IFF_PROMISC; 893 re_stop(sc); 894 if (m0 != NULL) 895 m_freem(m0); 896 897 RL_UNLOCK(sc); 898 899 return (error); 900} 901 902#endif 903 904/* 905 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 906 * IDs against our list and return a device name if we find a match. 907 */ 908static int 909re_probe(device_t dev) 910{ 911 const struct rl_type *t; 912 uint16_t devid, vendor; 913 uint16_t revid, sdevid; 914 int i; 915 916 vendor = pci_get_vendor(dev); 917 devid = pci_get_device(dev); 918 revid = pci_get_revid(dev); 919 sdevid = pci_get_subdevice(dev); 920 921 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 922 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 923 /* 924 * Only attach to rev. 3 of the Linksys EG1032 adapter. 925 * Rev. 2 is supported by sk(4). 926 */ 927 return (ENXIO); 928 } 929 } 930 931 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 932 if (revid != 0x20) { 933 /* 8139, let rl(4) take care of this device. */ 934 return (ENXIO); 935 } 936 } 937 938 t = re_devs; 939 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 940 if (vendor == t->rl_vid && devid == t->rl_did) { 941 device_set_desc(dev, t->rl_name); 942 return (BUS_PROBE_DEFAULT); 943 } 944 } 945 946 return (ENXIO); 947} 948 949/* 950 * Map a single buffer address. 951 */ 952 953static void 954re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 955{ 956 bus_addr_t *addr; 957 958 if (error) 959 return; 960 961 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 962 addr = arg; 963 *addr = segs->ds_addr; 964} 965 966static int 967re_allocmem(device_t dev, struct rl_softc *sc) 968{ 969 bus_addr_t lowaddr; 970 bus_size_t rx_list_size, tx_list_size; 971 int error; 972 int i; 973 974 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 975 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 976 977 /* 978 * Allocate the parent bus DMA tag appropriate for PCI. 979 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 980 * register should be set. However some RealTek chips are known 981 * to be buggy on DAC handling, therefore disable DAC by limiting 982 * DMA address space to 32bit. PCIe variants of RealTek chips 983 * may not have the limitation. 984 */ 985 lowaddr = BUS_SPACE_MAXADDR; 986 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 987 lowaddr = BUS_SPACE_MAXADDR_32BIT; 988 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 989 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 990 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 991 NULL, NULL, &sc->rl_parent_tag); 992 if (error) { 993 device_printf(dev, "could not allocate parent DMA tag\n"); 994 return (error); 995 } 996 997 /* 998 * Allocate map for TX mbufs. 999 */ 1000 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1001 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1002 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1003 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1004 if (error) { 1005 device_printf(dev, "could not allocate TX DMA tag\n"); 1006 return (error); 1007 } 1008 1009 /* 1010 * Allocate map for RX mbufs. 1011 */ 1012 1013 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1014 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1015 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1016 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1017 &sc->rl_ldata.rl_jrx_mtag); 1018 if (error) { 1019 device_printf(dev, 1020 "could not allocate jumbo RX DMA tag\n"); 1021 return (error); 1022 } 1023 } 1024 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1025 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1026 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1027 if (error) { 1028 device_printf(dev, "could not allocate RX DMA tag\n"); 1029 return (error); 1030 } 1031 1032 /* 1033 * Allocate map for TX descriptor list. 1034 */ 1035 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1036 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1037 NULL, tx_list_size, 1, tx_list_size, 0, 1038 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1039 if (error) { 1040 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1041 return (error); 1042 } 1043 1044 /* Allocate DMA'able memory for the TX ring */ 1045 1046 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1047 (void **)&sc->rl_ldata.rl_tx_list, 1048 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1049 &sc->rl_ldata.rl_tx_list_map); 1050 if (error) { 1051 device_printf(dev, "could not allocate TX DMA ring\n"); 1052 return (error); 1053 } 1054 1055 /* Load the map for the TX ring. */ 1056 1057 sc->rl_ldata.rl_tx_list_addr = 0; 1058 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1059 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1060 tx_list_size, re_dma_map_addr, 1061 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1062 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1063 device_printf(dev, "could not load TX DMA ring\n"); 1064 return (ENOMEM); 1065 } 1066 1067 /* Create DMA maps for TX buffers */ 1068 1069 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1070 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1071 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1072 if (error) { 1073 device_printf(dev, "could not create DMA map for TX\n"); 1074 return (error); 1075 } 1076 } 1077 1078 /* 1079 * Allocate map for RX descriptor list. 1080 */ 1081 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1082 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1083 NULL, rx_list_size, 1, rx_list_size, 0, 1084 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1085 if (error) { 1086 device_printf(dev, "could not create RX DMA ring tag\n"); 1087 return (error); 1088 } 1089 1090 /* Allocate DMA'able memory for the RX ring */ 1091 1092 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1093 (void **)&sc->rl_ldata.rl_rx_list, 1094 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1095 &sc->rl_ldata.rl_rx_list_map); 1096 if (error) { 1097 device_printf(dev, "could not allocate RX DMA ring\n"); 1098 return (error); 1099 } 1100 1101 /* Load the map for the RX ring. */ 1102 1103 sc->rl_ldata.rl_rx_list_addr = 0; 1104 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1105 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1106 rx_list_size, re_dma_map_addr, 1107 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1108 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1109 device_printf(dev, "could not load RX DMA ring\n"); 1110 return (ENOMEM); 1111 } 1112 1113 /* Create DMA maps for RX buffers */ 1114 1115 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1116 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1117 &sc->rl_ldata.rl_jrx_sparemap); 1118 if (error) { 1119 device_printf(dev, 1120 "could not create spare DMA map for jumbo RX\n"); 1121 return (error); 1122 } 1123 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1124 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1125 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1126 if (error) { 1127 device_printf(dev, 1128 "could not create DMA map for jumbo RX\n"); 1129 return (error); 1130 } 1131 } 1132 } 1133 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1134 &sc->rl_ldata.rl_rx_sparemap); 1135 if (error) { 1136 device_printf(dev, "could not create spare DMA map for RX\n"); 1137 return (error); 1138 } 1139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1140 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1141 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1142 if (error) { 1143 device_printf(dev, "could not create DMA map for RX\n"); 1144 return (error); 1145 } 1146 } 1147 1148 /* Create DMA map for statistics. */ 1149 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1150 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1151 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1152 &sc->rl_ldata.rl_stag); 1153 if (error) { 1154 device_printf(dev, "could not create statistics DMA tag\n"); 1155 return (error); 1156 } 1157 /* Allocate DMA'able memory for statistics. */ 1158 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1159 (void **)&sc->rl_ldata.rl_stats, 1160 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1161 &sc->rl_ldata.rl_smap); 1162 if (error) { 1163 device_printf(dev, 1164 "could not allocate statistics DMA memory\n"); 1165 return (error); 1166 } 1167 /* Load the map for statistics. */ 1168 sc->rl_ldata.rl_stats_addr = 0; 1169 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1170 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1171 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1172 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1173 device_printf(dev, "could not load statistics DMA memory\n"); 1174 return (ENOMEM); 1175 } 1176 1177 return (0); 1178} 1179 1180/* 1181 * Attach the interface. Allocate softc structures, do ifmedia 1182 * setup and ethernet/BPF attach. 1183 */ 1184static int 1185re_attach(device_t dev) 1186{ 1187 u_char eaddr[ETHER_ADDR_LEN]; 1188 u_int16_t as[ETHER_ADDR_LEN / 2]; 1189 struct rl_softc *sc; 1190 struct ifnet *ifp; 1191 const struct rl_hwrev *hw_rev; 1192 u_int32_t cap, ctl; 1193 int hwrev; 1194 u_int16_t devid, re_did = 0; 1195 int error = 0, i, phy, rid; 1196 int msic, msixc, reg; 1197 uint8_t cfg; 1198 1199 sc = device_get_softc(dev); 1200 sc->rl_dev = dev; 1201 1202 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1203 MTX_DEF); 1204 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1205 1206 /* 1207 * Map control/status registers. 1208 */ 1209 pci_enable_busmaster(dev); 1210 1211 devid = pci_get_device(dev); 1212 /* 1213 * Prefer memory space register mapping over IO space. 1214 * Because RTL8169SC does not seem to work when memory mapping 1215 * is used always activate io mapping. 1216 */ 1217 if (devid == RT_DEVICEID_8169SC) 1218 prefer_iomap = 1; 1219 if (prefer_iomap == 0) { 1220 sc->rl_res_id = PCIR_BAR(1); 1221 sc->rl_res_type = SYS_RES_MEMORY; 1222 /* RTL8168/8101E seems to use different BARs. */ 1223 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1224 sc->rl_res_id = PCIR_BAR(2); 1225 } else { 1226 sc->rl_res_id = PCIR_BAR(0); 1227 sc->rl_res_type = SYS_RES_IOPORT; 1228 } 1229 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1230 &sc->rl_res_id, RF_ACTIVE); 1231 if (sc->rl_res == NULL && prefer_iomap == 0) { 1232 sc->rl_res_id = PCIR_BAR(0); 1233 sc->rl_res_type = SYS_RES_IOPORT; 1234 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1235 &sc->rl_res_id, RF_ACTIVE); 1236 } 1237 if (sc->rl_res == NULL) { 1238 device_printf(dev, "couldn't map ports/memory\n"); 1239 error = ENXIO; 1240 goto fail; 1241 } 1242 1243 sc->rl_btag = rman_get_bustag(sc->rl_res); 1244 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1245 1246 msic = pci_msi_count(dev); 1247 msixc = pci_msix_count(dev); 1248 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1249 sc->rl_flags |= RL_FLAG_PCIE; 1250 sc->rl_expcap = reg; 1251 } 1252 if (bootverbose) { 1253 device_printf(dev, "MSI count : %d\n", msic); 1254 device_printf(dev, "MSI-X count : %d\n", msixc); 1255 } 1256 if (msix_disable > 0) 1257 msixc = 0; 1258 if (msi_disable > 0) 1259 msic = 0; 1260 /* Prefer MSI-X to MSI. */ 1261 if (msixc > 0) { 1262 msixc = 1; 1263 rid = PCIR_BAR(4); 1264 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1265 &rid, RF_ACTIVE); 1266 if (sc->rl_res_pba == NULL) { 1267 device_printf(sc->rl_dev, 1268 "could not allocate MSI-X PBA resource\n"); 1269 } 1270 if (sc->rl_res_pba != NULL && 1271 pci_alloc_msix(dev, &msixc) == 0) { 1272 if (msixc == 1) { 1273 device_printf(dev, "Using %d MSI-X message\n", 1274 msixc); 1275 sc->rl_flags |= RL_FLAG_MSIX; 1276 } else 1277 pci_release_msi(dev); 1278 } 1279 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1280 if (sc->rl_res_pba != NULL) 1281 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1282 sc->rl_res_pba); 1283 sc->rl_res_pba = NULL; 1284 msixc = 0; 1285 } 1286 } 1287 /* Prefer MSI to INTx. */ 1288 if (msixc == 0 && msic > 0) { 1289 msic = 1; 1290 if (pci_alloc_msi(dev, &msic) == 0) { 1291 if (msic == RL_MSI_MESSAGES) { 1292 device_printf(dev, "Using %d MSI message\n", 1293 msic); 1294 sc->rl_flags |= RL_FLAG_MSI; 1295 /* Explicitly set MSI enable bit. */ 1296 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1297 cfg = CSR_READ_1(sc, RL_CFG2); 1298 cfg |= RL_CFG2_MSI; 1299 CSR_WRITE_1(sc, RL_CFG2, cfg); 1300 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1301 } else 1302 pci_release_msi(dev); 1303 } 1304 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1305 msic = 0; 1306 } 1307 1308 /* Allocate interrupt */ 1309 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1310 rid = 0; 1311 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1312 RF_SHAREABLE | RF_ACTIVE); 1313 if (sc->rl_irq[0] == NULL) { 1314 device_printf(dev, "couldn't allocate IRQ resources\n"); 1315 error = ENXIO; 1316 goto fail; 1317 } 1318 } else { 1319 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1320 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1321 SYS_RES_IRQ, &rid, RF_ACTIVE); 1322 if (sc->rl_irq[i] == NULL) { 1323 device_printf(dev, 1324 "couldn't llocate IRQ resources for " 1325 "message %d\n", rid); 1326 error = ENXIO; 1327 goto fail; 1328 } 1329 } 1330 } 1331 1332 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1333 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1334 cfg = CSR_READ_1(sc, RL_CFG2); 1335 if ((cfg & RL_CFG2_MSI) != 0) { 1336 device_printf(dev, "turning off MSI enable bit.\n"); 1337 cfg &= ~RL_CFG2_MSI; 1338 CSR_WRITE_1(sc, RL_CFG2, cfg); 1339 } 1340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1341 } 1342 1343 /* Disable ASPM L0S/L1. */ 1344 if (sc->rl_expcap != 0) { 1345 cap = pci_read_config(dev, sc->rl_expcap + 1346 PCIR_EXPRESS_LINK_CAP, 2); 1347 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 1348 ctl = pci_read_config(dev, sc->rl_expcap + 1349 PCIR_EXPRESS_LINK_CTL, 2); 1350 if ((ctl & 0x0003) != 0) { 1351 ctl &= ~0x0003; 1352 pci_write_config(dev, sc->rl_expcap + 1353 PCIR_EXPRESS_LINK_CTL, ctl, 2); 1354 device_printf(dev, "ASPM disabled\n"); 1355 } 1356 } else 1357 device_printf(dev, "no ASPM capability\n"); 1358 } 1359 1360 hw_rev = re_hwrevs; 1361 hwrev = CSR_READ_4(sc, RL_TXCFG); 1362 switch (hwrev & 0x70000000) { 1363 case 0x00000000: 1364 case 0x10000000: 1365 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1366 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1367 break; 1368 default: 1369 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1370 hwrev &= RL_TXCFG_HWREV; 1371 break; 1372 } 1373 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1374 while (hw_rev->rl_desc != NULL) { 1375 if (hw_rev->rl_rev == hwrev) { 1376 sc->rl_type = hw_rev->rl_type; 1377 sc->rl_hwrev = hw_rev; 1378 break; 1379 } 1380 hw_rev++; 1381 } 1382 if (hw_rev->rl_desc == NULL) { 1383 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1384 error = ENXIO; 1385 goto fail; 1386 } 1387 1388 switch (hw_rev->rl_rev) { 1389 case RL_HWREV_8139CPLUS: 1390 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1391 break; 1392 case RL_HWREV_8100E: 1393 case RL_HWREV_8101E: 1394 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1395 break; 1396 case RL_HWREV_8102E: 1397 case RL_HWREV_8102EL: 1398 case RL_HWREV_8102EL_SPIN1: 1399 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1400 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1401 RL_FLAG_AUTOPAD; 1402 break; 1403 case RL_HWREV_8103E: 1404 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1405 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1406 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1407 break; 1408 case RL_HWREV_8401E: 1409 case RL_HWREV_8105E: 1410 case RL_HWREV_8105E_SPIN1: 1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1412 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1413 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1414 break; 1415 case RL_HWREV_8402: 1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1417 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1418 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1419 RL_FLAG_CMDSTOP_WAIT_TXQ; 1420 break; 1421 case RL_HWREV_8168B_SPIN1: 1422 case RL_HWREV_8168B_SPIN2: 1423 sc->rl_flags |= RL_FLAG_WOLRXENB; 1424 /* FALLTHROUGH */ 1425 case RL_HWREV_8168B_SPIN3: 1426 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1427 break; 1428 case RL_HWREV_8168C_SPIN2: 1429 sc->rl_flags |= RL_FLAG_MACSLEEP; 1430 /* FALLTHROUGH */ 1431 case RL_HWREV_8168C: 1432 if ((hwrev & 0x00700000) == 0x00200000) 1433 sc->rl_flags |= RL_FLAG_MACSLEEP; 1434 /* FALLTHROUGH */ 1435 case RL_HWREV_8168CP: 1436 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1437 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1438 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1439 break; 1440 case RL_HWREV_8168D: 1441 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1442 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1443 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1444 RL_FLAG_WOL_MANLINK; 1445 break; 1446 case RL_HWREV_8168DP: 1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1448 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1449 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1450 break; 1451 case RL_HWREV_8168E: 1452 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1453 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1454 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1455 RL_FLAG_WOL_MANLINK; 1456 break; 1457 case RL_HWREV_8168E_VL: 1458 case RL_HWREV_8168F: 1459 case RL_HWREV_8411: 1460 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1461 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1462 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1463 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1464 break; 1465 case RL_HWREV_8169_8110SB: 1466 case RL_HWREV_8169_8110SBL: 1467 case RL_HWREV_8169_8110SC: 1468 case RL_HWREV_8169_8110SCE: 1469 sc->rl_flags |= RL_FLAG_PHYWAKE; 1470 /* FALLTHROUGH */ 1471 case RL_HWREV_8169: 1472 case RL_HWREV_8169S: 1473 case RL_HWREV_8110S: 1474 sc->rl_flags |= RL_FLAG_MACRESET; 1475 break; 1476 default: 1477 break; 1478 } 1479 1480 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1481 sc->rl_cfg0 = RL_8139_CFG0; 1482 sc->rl_cfg1 = RL_8139_CFG1; 1483 sc->rl_cfg2 = 0; 1484 sc->rl_cfg3 = RL_8139_CFG3; 1485 sc->rl_cfg4 = RL_8139_CFG4; 1486 sc->rl_cfg5 = RL_8139_CFG5; 1487 } else { 1488 sc->rl_cfg0 = RL_CFG0; 1489 sc->rl_cfg1 = RL_CFG1; 1490 sc->rl_cfg2 = RL_CFG2; 1491 sc->rl_cfg3 = RL_CFG3; 1492 sc->rl_cfg4 = RL_CFG4; 1493 sc->rl_cfg5 = RL_CFG5; 1494 } 1495 1496 /* Reset the adapter. */ 1497 RL_LOCK(sc); 1498 re_reset(sc); 1499 RL_UNLOCK(sc); 1500 1501 /* Enable PME. */ 1502 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1503 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1504 cfg |= RL_CFG1_PME; 1505 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1506 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1507 cfg &= RL_CFG5_PME_STS; 1508 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1509 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1510 1511 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1512 /* 1513 * XXX Should have a better way to extract station 1514 * address from EEPROM. 1515 */ 1516 for (i = 0; i < ETHER_ADDR_LEN; i++) 1517 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1518 } else { 1519 sc->rl_eewidth = RL_9356_ADDR_LEN; 1520 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1521 if (re_did != 0x8129) 1522 sc->rl_eewidth = RL_9346_ADDR_LEN; 1523 1524 /* 1525 * Get station address from the EEPROM. 1526 */ 1527 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1528 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1529 as[i] = le16toh(as[i]); 1530 bcopy(as, eaddr, ETHER_ADDR_LEN); 1531 } 1532 1533 if (sc->rl_type == RL_8169) { 1534 /* Set RX length mask and number of descriptors. */ 1535 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1536 sc->rl_txstart = RL_GTXSTART; 1537 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1538 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1539 } else { 1540 /* Set RX length mask and number of descriptors. */ 1541 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1542 sc->rl_txstart = RL_TXSTART; 1543 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1544 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1545 } 1546 1547 error = re_allocmem(dev, sc); 1548 if (error) 1549 goto fail; 1550 re_add_sysctls(sc); 1551 1552 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1553 if (ifp == NULL) { 1554 device_printf(dev, "can not if_alloc()\n"); 1555 error = ENOSPC; 1556 goto fail; 1557 } 1558 1559 /* Take controller out of deep sleep mode. */ 1560 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1561 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1562 CSR_WRITE_1(sc, RL_GPIO, 1563 CSR_READ_1(sc, RL_GPIO) | 0x01); 1564 else 1565 CSR_WRITE_1(sc, RL_GPIO, 1566 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1567 } 1568 1569 /* Take PHY out of power down mode. */ 1570 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1571 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1572 if (hw_rev->rl_rev == RL_HWREV_8401E) 1573 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1574 } 1575 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1576 re_gmii_writereg(dev, 1, 0x1f, 0); 1577 re_gmii_writereg(dev, 1, 0x0e, 0); 1578 } 1579 1580 ifp->if_softc = sc; 1581 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1582 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1583 ifp->if_ioctl = re_ioctl; 1584 ifp->if_start = re_start; 1585 /* 1586 * RTL8168/8111C generates wrong IP checksummed frame if the 1587 * packet has IP options so disable TX IP checksum offloading. 1588 */ 1589 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1590 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2) 1591 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1592 else 1593 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1594 ifp->if_hwassist |= CSUM_TSO; 1595 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1596 ifp->if_capenable = ifp->if_capabilities; 1597 ifp->if_init = re_init; 1598 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1599 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1600 IFQ_SET_READY(&ifp->if_snd); 1601 1602 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1603 1604#define RE_PHYAD_INTERNAL 0 1605 1606 /* Do MII setup. */ 1607 phy = RE_PHYAD_INTERNAL; 1608 if (sc->rl_type == RL_8169) 1609 phy = 1; 1610 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1611 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1612 if (error != 0) { 1613 device_printf(dev, "attaching PHYs failed\n"); 1614 goto fail; 1615 } 1616 1617 /* 1618 * Call MI attach routine. 1619 */ 1620 ether_ifattach(ifp, eaddr); 1621 1622 /* VLAN capability setup */ 1623 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1624 if (ifp->if_capabilities & IFCAP_HWCSUM) 1625 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1626 /* Enable WOL if PM is supported. */ 1627 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1628 ifp->if_capabilities |= IFCAP_WOL; 1629 ifp->if_capenable = ifp->if_capabilities; 1630 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1631 /* 1632 * Don't enable TSO by default. It is known to generate 1633 * corrupted TCP segments(bad TCP options) under certain 1634 * circumtances. 1635 */ 1636 ifp->if_hwassist &= ~CSUM_TSO; 1637 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1638#ifdef DEVICE_POLLING 1639 ifp->if_capabilities |= IFCAP_POLLING; 1640#endif 1641 /* 1642 * Tell the upper layer(s) we support long frames. 1643 * Must appear after the call to ether_ifattach() because 1644 * ether_ifattach() sets ifi_hdrlen to the default value. 1645 */ 1646 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1647 1648#ifdef DEV_NETMAP 1649 re_netmap_attach(sc); 1650#endif /* DEV_NETMAP */ 1651#ifdef RE_DIAG 1652 /* 1653 * Perform hardware diagnostic on the original RTL8169. 1654 * Some 32-bit cards were incorrectly wired and would 1655 * malfunction if plugged into a 64-bit slot. 1656 */ 1657 1658 if (hwrev == RL_HWREV_8169) { 1659 error = re_diag(sc); 1660 if (error) { 1661 device_printf(dev, 1662 "attach aborted due to hardware diag failure\n"); 1663 ether_ifdetach(ifp); 1664 goto fail; 1665 } 1666 } 1667#endif 1668 1669#ifdef RE_TX_MODERATION 1670 intr_filter = 1; 1671#endif 1672 /* Hook interrupt last to avoid having to lock softc */ 1673 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1674 intr_filter == 0) { 1675 error = bus_setup_intr(dev, sc->rl_irq[0], 1676 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1677 &sc->rl_intrhand[0]); 1678 } else { 1679 error = bus_setup_intr(dev, sc->rl_irq[0], 1680 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1681 &sc->rl_intrhand[0]); 1682 } 1683 if (error) { 1684 device_printf(dev, "couldn't set up irq\n"); 1685 ether_ifdetach(ifp); 1686 } 1687 1688fail: 1689 1690 if (error) 1691 re_detach(dev); 1692 1693 return (error); 1694} 1695 1696/* 1697 * Shutdown hardware and free up resources. This can be called any 1698 * time after the mutex has been initialized. It is called in both 1699 * the error case in attach and the normal detach case so it needs 1700 * to be careful about only freeing resources that have actually been 1701 * allocated. 1702 */ 1703static int 1704re_detach(device_t dev) 1705{ 1706 struct rl_softc *sc; 1707 struct ifnet *ifp; 1708 int i, rid; 1709 1710 sc = device_get_softc(dev); 1711 ifp = sc->rl_ifp; 1712 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1713 1714 /* These should only be active if attach succeeded */ 1715 if (device_is_attached(dev)) { 1716#ifdef DEVICE_POLLING 1717 if (ifp->if_capenable & IFCAP_POLLING) 1718 ether_poll_deregister(ifp); 1719#endif 1720 RL_LOCK(sc); 1721#if 0 1722 sc->suspended = 1; 1723#endif 1724 re_stop(sc); 1725 RL_UNLOCK(sc); 1726 callout_drain(&sc->rl_stat_callout); 1727 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1728 /* 1729 * Force off the IFF_UP flag here, in case someone 1730 * still had a BPF descriptor attached to this 1731 * interface. If they do, ether_ifdetach() will cause 1732 * the BPF code to try and clear the promisc mode 1733 * flag, which will bubble down to re_ioctl(), 1734 * which will try to call re_init() again. This will 1735 * turn the NIC back on and restart the MII ticker, 1736 * which will panic the system when the kernel tries 1737 * to invoke the re_tick() function that isn't there 1738 * anymore. 1739 */ 1740 ifp->if_flags &= ~IFF_UP; 1741 ether_ifdetach(ifp); 1742 } 1743 if (sc->rl_miibus) 1744 device_delete_child(dev, sc->rl_miibus); 1745 bus_generic_detach(dev); 1746 1747 /* 1748 * The rest is resource deallocation, so we should already be 1749 * stopped here. 1750 */ 1751 1752 if (sc->rl_intrhand[0] != NULL) { 1753 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1754 sc->rl_intrhand[0] = NULL; 1755 } 1756 if (ifp != NULL) 1757 if_free(ifp); 1758 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1759 rid = 0; 1760 else 1761 rid = 1; 1762 if (sc->rl_irq[0] != NULL) { 1763 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1764 sc->rl_irq[0] = NULL; 1765 } 1766 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1767 pci_release_msi(dev); 1768 if (sc->rl_res_pba) { 1769 rid = PCIR_BAR(4); 1770 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1771 } 1772 if (sc->rl_res) 1773 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1774 sc->rl_res); 1775 1776 /* Unload and free the RX DMA ring memory and map */ 1777 1778 if (sc->rl_ldata.rl_rx_list_tag) { 1779 if (sc->rl_ldata.rl_rx_list_map) 1780 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1781 sc->rl_ldata.rl_rx_list_map); 1782 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1783 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1784 sc->rl_ldata.rl_rx_list, 1785 sc->rl_ldata.rl_rx_list_map); 1786 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1787 } 1788 1789 /* Unload and free the TX DMA ring memory and map */ 1790 1791 if (sc->rl_ldata.rl_tx_list_tag) { 1792 if (sc->rl_ldata.rl_tx_list_map) 1793 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1794 sc->rl_ldata.rl_tx_list_map); 1795 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1796 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1797 sc->rl_ldata.rl_tx_list, 1798 sc->rl_ldata.rl_tx_list_map); 1799 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1800 } 1801 1802 /* Destroy all the RX and TX buffer maps */ 1803 1804 if (sc->rl_ldata.rl_tx_mtag) { 1805 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1806 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1807 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1808 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1809 } 1810 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1811 } 1812 if (sc->rl_ldata.rl_rx_mtag) { 1813 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1814 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1815 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1816 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1817 } 1818 if (sc->rl_ldata.rl_rx_sparemap) 1819 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1820 sc->rl_ldata.rl_rx_sparemap); 1821 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1822 } 1823 if (sc->rl_ldata.rl_jrx_mtag) { 1824 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1825 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1826 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1827 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1828 } 1829 if (sc->rl_ldata.rl_jrx_sparemap) 1830 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1831 sc->rl_ldata.rl_jrx_sparemap); 1832 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1833 } 1834 /* Unload and free the stats buffer and map */ 1835 1836 if (sc->rl_ldata.rl_stag) { 1837 if (sc->rl_ldata.rl_smap) 1838 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1839 sc->rl_ldata.rl_smap); 1840 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1841 bus_dmamem_free(sc->rl_ldata.rl_stag, 1842 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1843 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1844 } 1845 1846#ifdef DEV_NETMAP 1847 netmap_detach(ifp); 1848#endif /* DEV_NETMAP */ 1849 if (sc->rl_parent_tag) 1850 bus_dma_tag_destroy(sc->rl_parent_tag); 1851 1852 mtx_destroy(&sc->rl_mtx); 1853 1854 return (0); 1855} 1856 1857static __inline void 1858re_discard_rxbuf(struct rl_softc *sc, int idx) 1859{ 1860 struct rl_desc *desc; 1861 struct rl_rxdesc *rxd; 1862 uint32_t cmdstat; 1863 1864 if (sc->rl_ifp->if_mtu > RL_MTU && 1865 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1866 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1867 else 1868 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1869 desc = &sc->rl_ldata.rl_rx_list[idx]; 1870 desc->rl_vlanctl = 0; 1871 cmdstat = rxd->rx_size; 1872 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1873 cmdstat |= RL_RDESC_CMD_EOR; 1874 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1875} 1876 1877static int 1878re_newbuf(struct rl_softc *sc, int idx) 1879{ 1880 struct mbuf *m; 1881 struct rl_rxdesc *rxd; 1882 bus_dma_segment_t segs[1]; 1883 bus_dmamap_t map; 1884 struct rl_desc *desc; 1885 uint32_t cmdstat; 1886 int error, nsegs; 1887 1888 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1889 if (m == NULL) 1890 return (ENOBUFS); 1891 1892 m->m_len = m->m_pkthdr.len = MCLBYTES; 1893#ifdef RE_FIXUP_RX 1894 /* 1895 * This is part of an evil trick to deal with non-x86 platforms. 1896 * The RealTek chip requires RX buffers to be aligned on 64-bit 1897 * boundaries, but that will hose non-x86 machines. To get around 1898 * this, we leave some empty space at the start of each buffer 1899 * and for non-x86 hosts, we copy the buffer back six bytes 1900 * to achieve word alignment. This is slightly more efficient 1901 * than allocating a new buffer, copying the contents, and 1902 * discarding the old buffer. 1903 */ 1904 m_adj(m, RE_ETHER_ALIGN); 1905#endif 1906 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1907 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1908 if (error != 0) { 1909 m_freem(m); 1910 return (ENOBUFS); 1911 } 1912 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1913 1914 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1915 if (rxd->rx_m != NULL) { 1916 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1917 BUS_DMASYNC_POSTREAD); 1918 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1919 } 1920 1921 rxd->rx_m = m; 1922 map = rxd->rx_dmamap; 1923 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1924 rxd->rx_size = segs[0].ds_len; 1925 sc->rl_ldata.rl_rx_sparemap = map; 1926 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1927 BUS_DMASYNC_PREREAD); 1928 1929 desc = &sc->rl_ldata.rl_rx_list[idx]; 1930 desc->rl_vlanctl = 0; 1931 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1932 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1933 cmdstat = segs[0].ds_len; 1934 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1935 cmdstat |= RL_RDESC_CMD_EOR; 1936 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1937 1938 return (0); 1939} 1940 1941static int 1942re_jumbo_newbuf(struct rl_softc *sc, int idx) 1943{ 1944 struct mbuf *m; 1945 struct rl_rxdesc *rxd; 1946 bus_dma_segment_t segs[1]; 1947 bus_dmamap_t map; 1948 struct rl_desc *desc; 1949 uint32_t cmdstat; 1950 int error, nsegs; 1951 1952 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1953 if (m == NULL) 1954 return (ENOBUFS); 1955 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1956#ifdef RE_FIXUP_RX 1957 m_adj(m, RE_ETHER_ALIGN); 1958#endif 1959 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1960 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1961 if (error != 0) { 1962 m_freem(m); 1963 return (ENOBUFS); 1964 } 1965 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1966 1967 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1968 if (rxd->rx_m != NULL) { 1969 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1970 BUS_DMASYNC_POSTREAD); 1971 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1972 } 1973 1974 rxd->rx_m = m; 1975 map = rxd->rx_dmamap; 1976 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1977 rxd->rx_size = segs[0].ds_len; 1978 sc->rl_ldata.rl_jrx_sparemap = map; 1979 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1980 BUS_DMASYNC_PREREAD); 1981 1982 desc = &sc->rl_ldata.rl_rx_list[idx]; 1983 desc->rl_vlanctl = 0; 1984 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1985 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1986 cmdstat = segs[0].ds_len; 1987 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1988 cmdstat |= RL_RDESC_CMD_EOR; 1989 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1990 1991 return (0); 1992} 1993 1994#ifdef RE_FIXUP_RX 1995static __inline void 1996re_fixup_rx(struct mbuf *m) 1997{ 1998 int i; 1999 uint16_t *src, *dst; 2000 2001 src = mtod(m, uint16_t *); 2002 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2003 2004 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2005 *dst++ = *src++; 2006 2007 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2008} 2009#endif 2010 2011static int 2012re_tx_list_init(struct rl_softc *sc) 2013{ 2014 struct rl_desc *desc; 2015 int i; 2016 2017 RL_LOCK_ASSERT(sc); 2018 2019 bzero(sc->rl_ldata.rl_tx_list, 2020 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2021 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2022 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2023#ifdef DEV_NETMAP 2024 re_netmap_tx_init(sc); 2025#endif /* DEV_NETMAP */ 2026 /* Set EOR. */ 2027 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2028 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2029 2030 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2031 sc->rl_ldata.rl_tx_list_map, 2032 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2033 2034 sc->rl_ldata.rl_tx_prodidx = 0; 2035 sc->rl_ldata.rl_tx_considx = 0; 2036 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2037 2038 return (0); 2039} 2040 2041static int 2042re_rx_list_init(struct rl_softc *sc) 2043{ 2044 int error, i; 2045 2046 bzero(sc->rl_ldata.rl_rx_list, 2047 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2048 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2049 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2050 if ((error = re_newbuf(sc, i)) != 0) 2051 return (error); 2052 } 2053#ifdef DEV_NETMAP 2054 re_netmap_rx_init(sc); 2055#endif /* DEV_NETMAP */ 2056 2057 /* Flush the RX descriptors */ 2058 2059 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2060 sc->rl_ldata.rl_rx_list_map, 2061 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2062 2063 sc->rl_ldata.rl_rx_prodidx = 0; 2064 sc->rl_head = sc->rl_tail = NULL; 2065 sc->rl_int_rx_act = 0; 2066 2067 return (0); 2068} 2069 2070static int 2071re_jrx_list_init(struct rl_softc *sc) 2072{ 2073 int error, i; 2074 2075 bzero(sc->rl_ldata.rl_rx_list, 2076 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2077 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2078 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2079 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2080 return (error); 2081 } 2082 2083 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2084 sc->rl_ldata.rl_rx_list_map, 2085 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2086 2087 sc->rl_ldata.rl_rx_prodidx = 0; 2088 sc->rl_head = sc->rl_tail = NULL; 2089 sc->rl_int_rx_act = 0; 2090 2091 return (0); 2092} 2093 2094/* 2095 * RX handler for C+ and 8169. For the gigE chips, we support 2096 * the reception of jumbo frames that have been fragmented 2097 * across multiple 2K mbuf cluster buffers. 2098 */ 2099static int 2100re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2101{ 2102 struct mbuf *m; 2103 struct ifnet *ifp; 2104 int i, rxerr, total_len; 2105 struct rl_desc *cur_rx; 2106 u_int32_t rxstat, rxvlan; 2107 int jumbo, maxpkt = 16, rx_npkts = 0; 2108 2109 RL_LOCK_ASSERT(sc); 2110 2111 ifp = sc->rl_ifp; 2112#ifdef DEV_NETMAP 2113 if (ifp->if_capenable & IFCAP_NETMAP) { 2114 NA(ifp)->rx_rings->nr_kflags |= NKR_PENDINTR; 2115 selwakeuppri(&NA(ifp)->rx_rings->si, PI_NET); 2116 return 0; 2117 } 2118#endif /* DEV_NETMAP */ 2119 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2120 jumbo = 1; 2121 else 2122 jumbo = 0; 2123 2124 /* Invalidate the descriptor memory */ 2125 2126 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2127 sc->rl_ldata.rl_rx_list_map, 2128 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2129 2130 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2131 i = RL_RX_DESC_NXT(sc, i)) { 2132 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2133 break; 2134 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2135 rxstat = le32toh(cur_rx->rl_cmdstat); 2136 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2137 break; 2138 total_len = rxstat & sc->rl_rxlenmask; 2139 rxvlan = le32toh(cur_rx->rl_vlanctl); 2140 if (jumbo != 0) 2141 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2142 else 2143 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2144 2145 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2146 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2147 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2148 /* 2149 * RTL8168C or later controllers do not 2150 * support multi-fragment packet. 2151 */ 2152 re_discard_rxbuf(sc, i); 2153 continue; 2154 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2155 if (re_newbuf(sc, i) != 0) { 2156 /* 2157 * If this is part of a multi-fragment packet, 2158 * discard all the pieces. 2159 */ 2160 if (sc->rl_head != NULL) { 2161 m_freem(sc->rl_head); 2162 sc->rl_head = sc->rl_tail = NULL; 2163 } 2164 re_discard_rxbuf(sc, i); 2165 continue; 2166 } 2167 m->m_len = RE_RX_DESC_BUFLEN; 2168 if (sc->rl_head == NULL) 2169 sc->rl_head = sc->rl_tail = m; 2170 else { 2171 m->m_flags &= ~M_PKTHDR; 2172 sc->rl_tail->m_next = m; 2173 sc->rl_tail = m; 2174 } 2175 continue; 2176 } 2177 2178 /* 2179 * NOTE: for the 8139C+, the frame length field 2180 * is always 12 bits in size, but for the gigE chips, 2181 * it is 13 bits (since the max RX frame length is 16K). 2182 * Unfortunately, all 32 bits in the status word 2183 * were already used, so to make room for the extra 2184 * length bit, RealTek took out the 'frame alignment 2185 * error' bit and shifted the other status bits 2186 * over one slot. The OWN, EOR, FS and LS bits are 2187 * still in the same places. We have already extracted 2188 * the frame length and checked the OWN bit, so rather 2189 * than using an alternate bit mapping, we shift the 2190 * status bits one space to the right so we can evaluate 2191 * them using the 8169 status as though it was in the 2192 * same format as that of the 8139C+. 2193 */ 2194 if (sc->rl_type == RL_8169) 2195 rxstat >>= 1; 2196 2197 /* 2198 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2199 * set, but if CRC is clear, it will still be a valid frame. 2200 */ 2201 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2202 rxerr = 1; 2203 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2204 total_len > 8191 && 2205 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2206 rxerr = 0; 2207 if (rxerr != 0) { 2208 ifp->if_ierrors++; 2209 /* 2210 * If this is part of a multi-fragment packet, 2211 * discard all the pieces. 2212 */ 2213 if (sc->rl_head != NULL) { 2214 m_freem(sc->rl_head); 2215 sc->rl_head = sc->rl_tail = NULL; 2216 } 2217 re_discard_rxbuf(sc, i); 2218 continue; 2219 } 2220 } 2221 2222 /* 2223 * If allocating a replacement mbuf fails, 2224 * reload the current one. 2225 */ 2226 if (jumbo != 0) 2227 rxerr = re_jumbo_newbuf(sc, i); 2228 else 2229 rxerr = re_newbuf(sc, i); 2230 if (rxerr != 0) { 2231 ifp->if_iqdrops++; 2232 if (sc->rl_head != NULL) { 2233 m_freem(sc->rl_head); 2234 sc->rl_head = sc->rl_tail = NULL; 2235 } 2236 re_discard_rxbuf(sc, i); 2237 continue; 2238 } 2239 2240 if (sc->rl_head != NULL) { 2241 if (jumbo != 0) 2242 m->m_len = total_len; 2243 else { 2244 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2245 if (m->m_len == 0) 2246 m->m_len = RE_RX_DESC_BUFLEN; 2247 } 2248 /* 2249 * Special case: if there's 4 bytes or less 2250 * in this buffer, the mbuf can be discarded: 2251 * the last 4 bytes is the CRC, which we don't 2252 * care about anyway. 2253 */ 2254 if (m->m_len <= ETHER_CRC_LEN) { 2255 sc->rl_tail->m_len -= 2256 (ETHER_CRC_LEN - m->m_len); 2257 m_freem(m); 2258 } else { 2259 m->m_len -= ETHER_CRC_LEN; 2260 m->m_flags &= ~M_PKTHDR; 2261 sc->rl_tail->m_next = m; 2262 } 2263 m = sc->rl_head; 2264 sc->rl_head = sc->rl_tail = NULL; 2265 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2266 } else 2267 m->m_pkthdr.len = m->m_len = 2268 (total_len - ETHER_CRC_LEN); 2269 2270#ifdef RE_FIXUP_RX 2271 re_fixup_rx(m); 2272#endif 2273 ifp->if_ipackets++; 2274 m->m_pkthdr.rcvif = ifp; 2275 2276 /* Do RX checksumming if enabled */ 2277 2278 if (ifp->if_capenable & IFCAP_RXCSUM) { 2279 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2280 /* Check IP header checksum */ 2281 if (rxstat & RL_RDESC_STAT_PROTOID) 2282 m->m_pkthdr.csum_flags |= 2283 CSUM_IP_CHECKED; 2284 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2285 m->m_pkthdr.csum_flags |= 2286 CSUM_IP_VALID; 2287 2288 /* Check TCP/UDP checksum */ 2289 if ((RL_TCPPKT(rxstat) && 2290 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2291 (RL_UDPPKT(rxstat) && 2292 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2293 m->m_pkthdr.csum_flags |= 2294 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2295 m->m_pkthdr.csum_data = 0xffff; 2296 } 2297 } else { 2298 /* 2299 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2300 */ 2301 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2302 (rxvlan & RL_RDESC_IPV4)) 2303 m->m_pkthdr.csum_flags |= 2304 CSUM_IP_CHECKED; 2305 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2306 (rxvlan & RL_RDESC_IPV4)) 2307 m->m_pkthdr.csum_flags |= 2308 CSUM_IP_VALID; 2309 if (((rxstat & RL_RDESC_STAT_TCP) && 2310 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2311 ((rxstat & RL_RDESC_STAT_UDP) && 2312 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2313 m->m_pkthdr.csum_flags |= 2314 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2315 m->m_pkthdr.csum_data = 0xffff; 2316 } 2317 } 2318 } 2319 maxpkt--; 2320 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2321 m->m_pkthdr.ether_vtag = 2322 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2323 m->m_flags |= M_VLANTAG; 2324 } 2325 RL_UNLOCK(sc); 2326 (*ifp->if_input)(ifp, m); 2327 RL_LOCK(sc); 2328 rx_npkts++; 2329 } 2330 2331 /* Flush the RX DMA ring */ 2332 2333 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2334 sc->rl_ldata.rl_rx_list_map, 2335 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2336 2337 sc->rl_ldata.rl_rx_prodidx = i; 2338 2339 if (rx_npktsp != NULL) 2340 *rx_npktsp = rx_npkts; 2341 if (maxpkt) 2342 return (EAGAIN); 2343 2344 return (0); 2345} 2346 2347static void 2348re_txeof(struct rl_softc *sc) 2349{ 2350 struct ifnet *ifp; 2351 struct rl_txdesc *txd; 2352 u_int32_t txstat; 2353 int cons; 2354 2355 cons = sc->rl_ldata.rl_tx_considx; 2356 if (cons == sc->rl_ldata.rl_tx_prodidx) 2357 return; 2358 2359 ifp = sc->rl_ifp; 2360#ifdef DEV_NETMAP 2361 if (ifp->if_capenable & IFCAP_NETMAP) { 2362 selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET); 2363 return; 2364 } 2365#endif /* DEV_NETMAP */ 2366 /* Invalidate the TX descriptor list */ 2367 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2368 sc->rl_ldata.rl_tx_list_map, 2369 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2370 2371 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2372 cons = RL_TX_DESC_NXT(sc, cons)) { 2373 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2374 if (txstat & RL_TDESC_STAT_OWN) 2375 break; 2376 /* 2377 * We only stash mbufs in the last descriptor 2378 * in a fragment chain, which also happens to 2379 * be the only place where the TX status bits 2380 * are valid. 2381 */ 2382 if (txstat & RL_TDESC_CMD_EOF) { 2383 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2384 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2385 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2386 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2387 txd->tx_dmamap); 2388 KASSERT(txd->tx_m != NULL, 2389 ("%s: freeing NULL mbufs!", __func__)); 2390 m_freem(txd->tx_m); 2391 txd->tx_m = NULL; 2392 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2393 RL_TDESC_STAT_COLCNT)) 2394 ifp->if_collisions++; 2395 if (txstat & RL_TDESC_STAT_TXERRSUM) 2396 ifp->if_oerrors++; 2397 else 2398 ifp->if_opackets++; 2399 } 2400 sc->rl_ldata.rl_tx_free++; 2401 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2402 } 2403 sc->rl_ldata.rl_tx_considx = cons; 2404 2405 /* No changes made to the TX ring, so no flush needed */ 2406 2407 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2408#ifdef RE_TX_MODERATION 2409 /* 2410 * If not all descriptors have been reaped yet, reload 2411 * the timer so that we will eventually get another 2412 * interrupt that will cause us to re-enter this routine. 2413 * This is done in case the transmitter has gone idle. 2414 */ 2415 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2416#endif 2417 } else 2418 sc->rl_watchdog_timer = 0; 2419} 2420 2421static void 2422re_tick(void *xsc) 2423{ 2424 struct rl_softc *sc; 2425 struct mii_data *mii; 2426 2427 sc = xsc; 2428 2429 RL_LOCK_ASSERT(sc); 2430 2431 mii = device_get_softc(sc->rl_miibus); 2432 mii_tick(mii); 2433 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2434 re_miibus_statchg(sc->rl_dev); 2435 /* 2436 * Reclaim transmitted frames here. Technically it is not 2437 * necessary to do here but it ensures periodic reclamation 2438 * regardless of Tx completion interrupt which seems to be 2439 * lost on PCIe based controllers under certain situations. 2440 */ 2441 re_txeof(sc); 2442 re_watchdog(sc); 2443 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2444} 2445 2446#ifdef DEVICE_POLLING 2447static int 2448re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2449{ 2450 struct rl_softc *sc = ifp->if_softc; 2451 int rx_npkts = 0; 2452 2453 RL_LOCK(sc); 2454 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2455 rx_npkts = re_poll_locked(ifp, cmd, count); 2456 RL_UNLOCK(sc); 2457 return (rx_npkts); 2458} 2459 2460static int 2461re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2462{ 2463 struct rl_softc *sc = ifp->if_softc; 2464 int rx_npkts; 2465 2466 RL_LOCK_ASSERT(sc); 2467 2468 sc->rxcycles = count; 2469 re_rxeof(sc, &rx_npkts); 2470 re_txeof(sc); 2471 2472 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2473 re_start_locked(ifp); 2474 2475 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2476 u_int16_t status; 2477 2478 status = CSR_READ_2(sc, RL_ISR); 2479 if (status == 0xffff) 2480 return (rx_npkts); 2481 if (status) 2482 CSR_WRITE_2(sc, RL_ISR, status); 2483 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2484 (sc->rl_flags & RL_FLAG_PCIE)) 2485 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2486 2487 /* 2488 * XXX check behaviour on receiver stalls. 2489 */ 2490 2491 if (status & RL_ISR_SYSTEM_ERR) { 2492 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2493 re_init_locked(sc); 2494 } 2495 } 2496 return (rx_npkts); 2497} 2498#endif /* DEVICE_POLLING */ 2499 2500static int 2501re_intr(void *arg) 2502{ 2503 struct rl_softc *sc; 2504 uint16_t status; 2505 2506 sc = arg; 2507 2508 status = CSR_READ_2(sc, RL_ISR); 2509 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2510 return (FILTER_STRAY); 2511 CSR_WRITE_2(sc, RL_IMR, 0); 2512 2513 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2514 2515 return (FILTER_HANDLED); 2516} 2517 2518static void 2519re_int_task(void *arg, int npending) 2520{ 2521 struct rl_softc *sc; 2522 struct ifnet *ifp; 2523 u_int16_t status; 2524 int rval = 0; 2525 2526 sc = arg; 2527 ifp = sc->rl_ifp; 2528 2529 RL_LOCK(sc); 2530 2531 status = CSR_READ_2(sc, RL_ISR); 2532 CSR_WRITE_2(sc, RL_ISR, status); 2533 2534 if (sc->suspended || 2535 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2536 RL_UNLOCK(sc); 2537 return; 2538 } 2539 2540#ifdef DEVICE_POLLING 2541 if (ifp->if_capenable & IFCAP_POLLING) { 2542 RL_UNLOCK(sc); 2543 return; 2544 } 2545#endif 2546 2547 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2548 rval = re_rxeof(sc, NULL); 2549 2550 /* 2551 * Some chips will ignore a second TX request issued 2552 * while an existing transmission is in progress. If 2553 * the transmitter goes idle but there are still 2554 * packets waiting to be sent, we need to restart the 2555 * channel here to flush them out. This only seems to 2556 * be required with the PCIe devices. 2557 */ 2558 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2559 (sc->rl_flags & RL_FLAG_PCIE)) 2560 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2561 if (status & ( 2562#ifdef RE_TX_MODERATION 2563 RL_ISR_TIMEOUT_EXPIRED| 2564#else 2565 RL_ISR_TX_OK| 2566#endif 2567 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2568 re_txeof(sc); 2569 2570 if (status & RL_ISR_SYSTEM_ERR) { 2571 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2572 re_init_locked(sc); 2573 } 2574 2575 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2576 re_start_locked(ifp); 2577 2578 RL_UNLOCK(sc); 2579 2580 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2581 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2582 return; 2583 } 2584 2585 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2586} 2587 2588static void 2589re_intr_msi(void *xsc) 2590{ 2591 struct rl_softc *sc; 2592 struct ifnet *ifp; 2593 uint16_t intrs, status; 2594 2595 sc = xsc; 2596 RL_LOCK(sc); 2597 2598 ifp = sc->rl_ifp; 2599#ifdef DEVICE_POLLING 2600 if (ifp->if_capenable & IFCAP_POLLING) { 2601 RL_UNLOCK(sc); 2602 return; 2603 } 2604#endif 2605 /* Disable interrupts. */ 2606 CSR_WRITE_2(sc, RL_IMR, 0); 2607 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2608 RL_UNLOCK(sc); 2609 return; 2610 } 2611 2612 intrs = RL_INTRS_CPLUS; 2613 status = CSR_READ_2(sc, RL_ISR); 2614 CSR_WRITE_2(sc, RL_ISR, status); 2615 if (sc->rl_int_rx_act > 0) { 2616 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2617 RL_ISR_RX_OVERRUN); 2618 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2619 RL_ISR_RX_OVERRUN); 2620 } 2621 2622 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2623 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2624 re_rxeof(sc, NULL); 2625 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2626 if (sc->rl_int_rx_mod != 0 && 2627 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2628 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2629 /* Rearm one-shot timer. */ 2630 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2631 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2632 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2633 sc->rl_int_rx_act = 1; 2634 } else { 2635 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2636 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2637 sc->rl_int_rx_act = 0; 2638 } 2639 } 2640 } 2641 2642 /* 2643 * Some chips will ignore a second TX request issued 2644 * while an existing transmission is in progress. If 2645 * the transmitter goes idle but there are still 2646 * packets waiting to be sent, we need to restart the 2647 * channel here to flush them out. This only seems to 2648 * be required with the PCIe devices. 2649 */ 2650 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2651 (sc->rl_flags & RL_FLAG_PCIE)) 2652 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2653 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2654 re_txeof(sc); 2655 2656 if (status & RL_ISR_SYSTEM_ERR) { 2657 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2658 re_init_locked(sc); 2659 } 2660 2661 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2662 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2663 re_start_locked(ifp); 2664 CSR_WRITE_2(sc, RL_IMR, intrs); 2665 } 2666 RL_UNLOCK(sc); 2667} 2668 2669static int 2670re_encap(struct rl_softc *sc, struct mbuf **m_head) 2671{ 2672 struct rl_txdesc *txd, *txd_last; 2673 bus_dma_segment_t segs[RL_NTXSEGS]; 2674 bus_dmamap_t map; 2675 struct mbuf *m_new; 2676 struct rl_desc *desc; 2677 int nsegs, prod; 2678 int i, error, ei, si; 2679 int padlen; 2680 uint32_t cmdstat, csum_flags, vlanctl; 2681 2682 RL_LOCK_ASSERT(sc); 2683 M_ASSERTPKTHDR((*m_head)); 2684 2685 /* 2686 * With some of the RealTek chips, using the checksum offload 2687 * support in conjunction with the autopadding feature results 2688 * in the transmission of corrupt frames. For example, if we 2689 * need to send a really small IP fragment that's less than 60 2690 * bytes in size, and IP header checksumming is enabled, the 2691 * resulting ethernet frame that appears on the wire will 2692 * have garbled payload. To work around this, if TX IP checksum 2693 * offload is enabled, we always manually pad short frames out 2694 * to the minimum ethernet frame size. 2695 */ 2696 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2697 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2698 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2699 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2700 if (M_WRITABLE(*m_head) == 0) { 2701 /* Get a writable copy. */ 2702 m_new = m_dup(*m_head, M_DONTWAIT); 2703 m_freem(*m_head); 2704 if (m_new == NULL) { 2705 *m_head = NULL; 2706 return (ENOBUFS); 2707 } 2708 *m_head = m_new; 2709 } 2710 if ((*m_head)->m_next != NULL || 2711 M_TRAILINGSPACE(*m_head) < padlen) { 2712 m_new = m_defrag(*m_head, M_DONTWAIT); 2713 if (m_new == NULL) { 2714 m_freem(*m_head); 2715 *m_head = NULL; 2716 return (ENOBUFS); 2717 } 2718 } else 2719 m_new = *m_head; 2720 2721 /* 2722 * Manually pad short frames, and zero the pad space 2723 * to avoid leaking data. 2724 */ 2725 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2726 m_new->m_pkthdr.len += padlen; 2727 m_new->m_len = m_new->m_pkthdr.len; 2728 *m_head = m_new; 2729 } 2730 2731 prod = sc->rl_ldata.rl_tx_prodidx; 2732 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2733 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2734 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2735 if (error == EFBIG) { 2736 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2737 if (m_new == NULL) { 2738 m_freem(*m_head); 2739 *m_head = NULL; 2740 return (ENOBUFS); 2741 } 2742 *m_head = m_new; 2743 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2744 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2745 if (error != 0) { 2746 m_freem(*m_head); 2747 *m_head = NULL; 2748 return (error); 2749 } 2750 } else if (error != 0) 2751 return (error); 2752 if (nsegs == 0) { 2753 m_freem(*m_head); 2754 *m_head = NULL; 2755 return (EIO); 2756 } 2757 2758 /* Check for number of available descriptors. */ 2759 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2760 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2761 return (ENOBUFS); 2762 } 2763 2764 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2765 BUS_DMASYNC_PREWRITE); 2766 2767 /* 2768 * Set up checksum offload. Note: checksum offload bits must 2769 * appear in all descriptors of a multi-descriptor transmit 2770 * attempt. This is according to testing done with an 8169 2771 * chip. This is a requirement. 2772 */ 2773 vlanctl = 0; 2774 csum_flags = 0; 2775 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2776 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2777 csum_flags |= RL_TDESC_CMD_LGSEND; 2778 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2779 RL_TDESC_CMD_MSSVALV2_SHIFT); 2780 } else { 2781 csum_flags |= RL_TDESC_CMD_LGSEND | 2782 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2783 RL_TDESC_CMD_MSSVAL_SHIFT); 2784 } 2785 } else { 2786 /* 2787 * Unconditionally enable IP checksum if TCP or UDP 2788 * checksum is required. Otherwise, TCP/UDP checksum 2789 * does't make effects. 2790 */ 2791 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2792 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2793 csum_flags |= RL_TDESC_CMD_IPCSUM; 2794 if (((*m_head)->m_pkthdr.csum_flags & 2795 CSUM_TCP) != 0) 2796 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2797 if (((*m_head)->m_pkthdr.csum_flags & 2798 CSUM_UDP) != 0) 2799 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2800 } else { 2801 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2802 if (((*m_head)->m_pkthdr.csum_flags & 2803 CSUM_TCP) != 0) 2804 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2805 if (((*m_head)->m_pkthdr.csum_flags & 2806 CSUM_UDP) != 0) 2807 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2808 } 2809 } 2810 } 2811 2812 /* 2813 * Set up hardware VLAN tagging. Note: vlan tag info must 2814 * appear in all descriptors of a multi-descriptor 2815 * transmission attempt. 2816 */ 2817 if ((*m_head)->m_flags & M_VLANTAG) 2818 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2819 RL_TDESC_VLANCTL_TAG; 2820 2821 si = prod; 2822 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2823 desc = &sc->rl_ldata.rl_tx_list[prod]; 2824 desc->rl_vlanctl = htole32(vlanctl); 2825 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2826 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2827 cmdstat = segs[i].ds_len; 2828 if (i != 0) 2829 cmdstat |= RL_TDESC_CMD_OWN; 2830 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2831 cmdstat |= RL_TDESC_CMD_EOR; 2832 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2833 sc->rl_ldata.rl_tx_free--; 2834 } 2835 /* Update producer index. */ 2836 sc->rl_ldata.rl_tx_prodidx = prod; 2837 2838 /* Set EOF on the last descriptor. */ 2839 ei = RL_TX_DESC_PRV(sc, prod); 2840 desc = &sc->rl_ldata.rl_tx_list[ei]; 2841 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2842 2843 desc = &sc->rl_ldata.rl_tx_list[si]; 2844 /* Set SOF and transfer ownership of packet to the chip. */ 2845 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2846 2847 /* 2848 * Insure that the map for this transmission 2849 * is placed at the array index of the last descriptor 2850 * in this chain. (Swap last and first dmamaps.) 2851 */ 2852 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2853 map = txd->tx_dmamap; 2854 txd->tx_dmamap = txd_last->tx_dmamap; 2855 txd_last->tx_dmamap = map; 2856 txd_last->tx_m = *m_head; 2857 2858 return (0); 2859} 2860 2861static void 2862re_start(struct ifnet *ifp) 2863{ 2864 struct rl_softc *sc; 2865 2866 sc = ifp->if_softc; 2867 RL_LOCK(sc); 2868 re_start_locked(ifp); 2869 RL_UNLOCK(sc); 2870} 2871 2872/* 2873 * Main transmit routine for C+ and gigE NICs. 2874 */ 2875static void 2876re_start_locked(struct ifnet *ifp) 2877{ 2878 struct rl_softc *sc; 2879 struct mbuf *m_head; 2880 int queued; 2881 2882 sc = ifp->if_softc; 2883 2884#ifdef DEV_NETMAP 2885 /* XXX is this necessary ? */ 2886 if (ifp->if_capenable & IFCAP_NETMAP) { 2887 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2888 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2889 /* kick the tx unit */ 2890 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2891#ifdef RE_TX_MODERATION 2892 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2893#endif 2894 sc->rl_watchdog_timer = 5; 2895 } 2896 return; 2897 } 2898#endif /* DEV_NETMAP */ 2899 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2900 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2901 return; 2902 2903 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2904 sc->rl_ldata.rl_tx_free > 1;) { 2905 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2906 if (m_head == NULL) 2907 break; 2908 2909 if (re_encap(sc, &m_head) != 0) { 2910 if (m_head == NULL) 2911 break; 2912 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2913 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2914 break; 2915 } 2916 2917 /* 2918 * If there's a BPF listener, bounce a copy of this frame 2919 * to him. 2920 */ 2921 ETHER_BPF_MTAP(ifp, m_head); 2922 2923 queued++; 2924 } 2925 2926 if (queued == 0) { 2927#ifdef RE_TX_MODERATION 2928 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2929 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2930#endif 2931 return; 2932 } 2933 2934 /* Flush the TX descriptors */ 2935 2936 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2937 sc->rl_ldata.rl_tx_list_map, 2938 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2939 2940 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2941 2942#ifdef RE_TX_MODERATION 2943 /* 2944 * Use the countdown timer for interrupt moderation. 2945 * 'TX done' interrupts are disabled. Instead, we reset the 2946 * countdown timer, which will begin counting until it hits 2947 * the value in the TIMERINT register, and then trigger an 2948 * interrupt. Each time we write to the TIMERCNT register, 2949 * the timer count is reset to 0. 2950 */ 2951 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2952#endif 2953 2954 /* 2955 * Set a timeout in case the chip goes out to lunch. 2956 */ 2957 sc->rl_watchdog_timer = 5; 2958} 2959 2960static void 2961re_set_jumbo(struct rl_softc *sc, int jumbo) 2962{ 2963 2964 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2965 pci_set_max_read_req(sc->rl_dev, 4096); 2966 return; 2967 } 2968 2969 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2970 if (jumbo != 0) { 2971 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 2972 RL_CFG3_JUMBO_EN0); 2973 switch (sc->rl_hwrev->rl_rev) { 2974 case RL_HWREV_8168DP: 2975 break; 2976 case RL_HWREV_8168E: 2977 CSR_WRITE_1(sc, sc->rl_cfg4, 2978 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 2979 break; 2980 default: 2981 CSR_WRITE_1(sc, sc->rl_cfg4, 2982 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 2983 } 2984 } else { 2985 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 2986 ~RL_CFG3_JUMBO_EN0); 2987 switch (sc->rl_hwrev->rl_rev) { 2988 case RL_HWREV_8168DP: 2989 break; 2990 case RL_HWREV_8168E: 2991 CSR_WRITE_1(sc, sc->rl_cfg4, 2992 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 2993 break; 2994 default: 2995 CSR_WRITE_1(sc, sc->rl_cfg4, 2996 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 2997 } 2998 } 2999 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3000 3001 switch (sc->rl_hwrev->rl_rev) { 3002 case RL_HWREV_8168DP: 3003 pci_set_max_read_req(sc->rl_dev, 4096); 3004 break; 3005 default: 3006 if (jumbo != 0) 3007 pci_set_max_read_req(sc->rl_dev, 512); 3008 else 3009 pci_set_max_read_req(sc->rl_dev, 4096); 3010 } 3011} 3012 3013static void 3014re_init(void *xsc) 3015{ 3016 struct rl_softc *sc = xsc; 3017 3018 RL_LOCK(sc); 3019 re_init_locked(sc); 3020 RL_UNLOCK(sc); 3021} 3022 3023static void 3024re_init_locked(struct rl_softc *sc) 3025{ 3026 struct ifnet *ifp = sc->rl_ifp; 3027 struct mii_data *mii; 3028 uint32_t reg; 3029 uint16_t cfg; 3030 union { 3031 uint32_t align_dummy; 3032 u_char eaddr[ETHER_ADDR_LEN]; 3033 } eaddr; 3034 3035 RL_LOCK_ASSERT(sc); 3036 3037 mii = device_get_softc(sc->rl_miibus); 3038 3039 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3040 return; 3041 3042 /* 3043 * Cancel pending I/O and free all RX/TX buffers. 3044 */ 3045 re_stop(sc); 3046 3047 /* Put controller into known state. */ 3048 re_reset(sc); 3049 3050 /* 3051 * For C+ mode, initialize the RX descriptors and mbufs. 3052 */ 3053 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3054 if (ifp->if_mtu > RL_MTU) { 3055 if (re_jrx_list_init(sc) != 0) { 3056 device_printf(sc->rl_dev, 3057 "no memory for jumbo RX buffers\n"); 3058 re_stop(sc); 3059 return; 3060 } 3061 /* Disable checksum offloading for jumbo frames. */ 3062 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3063 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3064 } else { 3065 if (re_rx_list_init(sc) != 0) { 3066 device_printf(sc->rl_dev, 3067 "no memory for RX buffers\n"); 3068 re_stop(sc); 3069 return; 3070 } 3071 } 3072 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3073 } else { 3074 if (re_rx_list_init(sc) != 0) { 3075 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3076 re_stop(sc); 3077 return; 3078 } 3079 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3080 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3081 if (ifp->if_mtu > RL_MTU) 3082 pci_set_max_read_req(sc->rl_dev, 512); 3083 else 3084 pci_set_max_read_req(sc->rl_dev, 4096); 3085 } 3086 } 3087 re_tx_list_init(sc); 3088 3089 /* 3090 * Enable C+ RX and TX mode, as well as VLAN stripping and 3091 * RX checksum offload. We must configure the C+ register 3092 * before all others. 3093 */ 3094 cfg = RL_CPLUSCMD_PCI_MRW; 3095 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3096 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3097 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3098 cfg |= RL_CPLUSCMD_VLANSTRIP; 3099 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3100 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3101 /* XXX magic. */ 3102 cfg |= 0x0001; 3103 } else 3104 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3105 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3106 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3107 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3108 reg = 0x000fff00; 3109 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3110 reg |= 0x000000ff; 3111 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3112 reg |= 0x00f00000; 3113 CSR_WRITE_4(sc, 0x7c, reg); 3114 /* Disable interrupt mitigation. */ 3115 CSR_WRITE_2(sc, 0xe2, 0); 3116 } 3117 /* 3118 * Disable TSO if interface MTU size is greater than MSS 3119 * allowed in controller. 3120 */ 3121 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3122 ifp->if_capenable &= ~IFCAP_TSO4; 3123 ifp->if_hwassist &= ~CSUM_TSO; 3124 } 3125 3126 /* 3127 * Init our MAC address. Even though the chipset 3128 * documentation doesn't mention it, we need to enter "Config 3129 * register write enable" mode to modify the ID registers. 3130 */ 3131 /* Copy MAC address on stack to align. */ 3132 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3133 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3134 CSR_WRITE_4(sc, RL_IDR0, 3135 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3136 CSR_WRITE_4(sc, RL_IDR4, 3137 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3138 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3139 3140 /* 3141 * Load the addresses of the RX and TX lists into the chip. 3142 */ 3143 3144 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3145 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3146 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3147 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3148 3149 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3150 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3151 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3152 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3153 3154 /* 3155 * Enable transmit and receive. 3156 */ 3157 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3158 3159 /* 3160 * Set the initial TX configuration. 3161 */ 3162 if (sc->rl_testmode) { 3163 if (sc->rl_type == RL_8169) 3164 CSR_WRITE_4(sc, RL_TXCFG, 3165 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3166 else 3167 CSR_WRITE_4(sc, RL_TXCFG, 3168 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3169 } else 3170 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3171 3172 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3173 3174 /* 3175 * Set the initial RX configuration. 3176 */ 3177 re_set_rxmode(sc); 3178 3179 /* Configure interrupt moderation. */ 3180 if (sc->rl_type == RL_8169) { 3181 /* Magic from vendor. */ 3182 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3183 } 3184 3185#ifdef DEVICE_POLLING 3186 /* 3187 * Disable interrupts if we are polling. 3188 */ 3189 if (ifp->if_capenable & IFCAP_POLLING) 3190 CSR_WRITE_2(sc, RL_IMR, 0); 3191 else /* otherwise ... */ 3192#endif 3193 3194 /* 3195 * Enable interrupts. 3196 */ 3197 if (sc->rl_testmode) 3198 CSR_WRITE_2(sc, RL_IMR, 0); 3199 else 3200 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3201 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3202 3203 /* Set initial TX threshold */ 3204 sc->rl_txthresh = RL_TX_THRESH_INIT; 3205 3206 /* Start RX/TX process. */ 3207 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3208#ifdef notdef 3209 /* Enable receiver and transmitter. */ 3210 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3211#endif 3212 3213 /* 3214 * Initialize the timer interrupt register so that 3215 * a timer interrupt will be generated once the timer 3216 * reaches a certain number of ticks. The timer is 3217 * reloaded on each transmit. 3218 */ 3219#ifdef RE_TX_MODERATION 3220 /* 3221 * Use timer interrupt register to moderate TX interrupt 3222 * moderation, which dramatically improves TX frame rate. 3223 */ 3224 if (sc->rl_type == RL_8169) 3225 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3226 else 3227 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3228#else 3229 /* 3230 * Use timer interrupt register to moderate RX interrupt 3231 * moderation. 3232 */ 3233 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3234 intr_filter == 0) { 3235 if (sc->rl_type == RL_8169) 3236 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3237 RL_USECS(sc->rl_int_rx_mod)); 3238 } else { 3239 if (sc->rl_type == RL_8169) 3240 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3241 } 3242#endif 3243 3244 /* 3245 * For 8169 gigE NICs, set the max allowed RX packet 3246 * size so we can receive jumbo frames. 3247 */ 3248 if (sc->rl_type == RL_8169) { 3249 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3250 /* 3251 * For controllers that use new jumbo frame scheme, 3252 * set maximum size of jumbo frame depedning on 3253 * controller revisions. 3254 */ 3255 if (ifp->if_mtu > RL_MTU) 3256 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3257 sc->rl_hwrev->rl_max_mtu + 3258 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3259 ETHER_CRC_LEN); 3260 else 3261 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3262 RE_RX_DESC_BUFLEN); 3263 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3264 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3265 /* RTL810x has no jumbo frame support. */ 3266 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3267 } else 3268 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3269 } 3270 3271 if (sc->rl_testmode) 3272 return; 3273 3274 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3275 RL_CFG1_DRVLOAD); 3276 3277 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3278 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3279 3280 sc->rl_flags &= ~RL_FLAG_LINK; 3281 mii_mediachg(mii); 3282 3283 sc->rl_watchdog_timer = 0; 3284 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3285} 3286 3287/* 3288 * Set media options. 3289 */ 3290static int 3291re_ifmedia_upd(struct ifnet *ifp) 3292{ 3293 struct rl_softc *sc; 3294 struct mii_data *mii; 3295 int error; 3296 3297 sc = ifp->if_softc; 3298 mii = device_get_softc(sc->rl_miibus); 3299 RL_LOCK(sc); 3300 error = mii_mediachg(mii); 3301 RL_UNLOCK(sc); 3302 3303 return (error); 3304} 3305 3306/* 3307 * Report current media status. 3308 */ 3309static void 3310re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3311{ 3312 struct rl_softc *sc; 3313 struct mii_data *mii; 3314 3315 sc = ifp->if_softc; 3316 mii = device_get_softc(sc->rl_miibus); 3317 3318 RL_LOCK(sc); 3319 mii_pollstat(mii); 3320 ifmr->ifm_active = mii->mii_media_active; 3321 ifmr->ifm_status = mii->mii_media_status; 3322 RL_UNLOCK(sc); 3323} 3324 3325static int 3326re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3327{ 3328 struct rl_softc *sc = ifp->if_softc; 3329 struct ifreq *ifr = (struct ifreq *) data; 3330 struct mii_data *mii; 3331 uint32_t rev; 3332 int error = 0; 3333 3334 switch (command) { 3335 case SIOCSIFMTU: 3336 if (ifr->ifr_mtu < ETHERMIN || 3337 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3338 error = EINVAL; 3339 break; 3340 } 3341 RL_LOCK(sc); 3342 if (ifp->if_mtu != ifr->ifr_mtu) { 3343 ifp->if_mtu = ifr->ifr_mtu; 3344 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3345 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3346 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3347 re_init_locked(sc); 3348 } 3349 if (ifp->if_mtu > RL_TSO_MTU && 3350 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3351 ifp->if_capenable &= ~(IFCAP_TSO4 | 3352 IFCAP_VLAN_HWTSO); 3353 ifp->if_hwassist &= ~CSUM_TSO; 3354 } 3355 VLAN_CAPABILITIES(ifp); 3356 } 3357 RL_UNLOCK(sc); 3358 break; 3359 case SIOCSIFFLAGS: 3360 RL_LOCK(sc); 3361 if ((ifp->if_flags & IFF_UP) != 0) { 3362 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3363 if (((ifp->if_flags ^ sc->rl_if_flags) 3364 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3365 re_set_rxmode(sc); 3366 } else 3367 re_init_locked(sc); 3368 } else { 3369 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3370 re_stop(sc); 3371 } 3372 sc->rl_if_flags = ifp->if_flags; 3373 RL_UNLOCK(sc); 3374 break; 3375 case SIOCADDMULTI: 3376 case SIOCDELMULTI: 3377 RL_LOCK(sc); 3378 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3379 re_set_rxmode(sc); 3380 RL_UNLOCK(sc); 3381 break; 3382 case SIOCGIFMEDIA: 3383 case SIOCSIFMEDIA: 3384 mii = device_get_softc(sc->rl_miibus); 3385 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3386 break; 3387 case SIOCSIFCAP: 3388 { 3389 int mask, reinit; 3390 3391 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3392 reinit = 0; 3393#ifdef DEVICE_POLLING 3394 if (mask & IFCAP_POLLING) { 3395 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3396 error = ether_poll_register(re_poll, ifp); 3397 if (error) 3398 return (error); 3399 RL_LOCK(sc); 3400 /* Disable interrupts */ 3401 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3402 ifp->if_capenable |= IFCAP_POLLING; 3403 RL_UNLOCK(sc); 3404 } else { 3405 error = ether_poll_deregister(ifp); 3406 /* Enable interrupts. */ 3407 RL_LOCK(sc); 3408 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3409 ifp->if_capenable &= ~IFCAP_POLLING; 3410 RL_UNLOCK(sc); 3411 } 3412 } 3413#endif /* DEVICE_POLLING */ 3414 RL_LOCK(sc); 3415 if ((mask & IFCAP_TXCSUM) != 0 && 3416 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3417 ifp->if_capenable ^= IFCAP_TXCSUM; 3418 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3419 rev = sc->rl_hwrev->rl_rev; 3420 if (rev == RL_HWREV_8168C || 3421 rev == RL_HWREV_8168C_SPIN2) 3422 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3423 else 3424 ifp->if_hwassist |= RE_CSUM_FEATURES; 3425 } else 3426 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3427 reinit = 1; 3428 } 3429 if ((mask & IFCAP_RXCSUM) != 0 && 3430 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3431 ifp->if_capenable ^= IFCAP_RXCSUM; 3432 reinit = 1; 3433 } 3434 if ((mask & IFCAP_TSO4) != 0 && 3435 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3436 ifp->if_capenable ^= IFCAP_TSO4; 3437 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3438 ifp->if_hwassist |= CSUM_TSO; 3439 else 3440 ifp->if_hwassist &= ~CSUM_TSO; 3441 if (ifp->if_mtu > RL_TSO_MTU && 3442 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3443 ifp->if_capenable &= ~IFCAP_TSO4; 3444 ifp->if_hwassist &= ~CSUM_TSO; 3445 } 3446 } 3447 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3448 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3449 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3450 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3451 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3452 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3453 /* TSO over VLAN requires VLAN hardware tagging. */ 3454 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3455 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3456 reinit = 1; 3457 } 3458 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3459 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3460 IFCAP_VLAN_HWTSO)) != 0) 3461 reinit = 1; 3462 if ((mask & IFCAP_WOL) != 0 && 3463 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3464 if ((mask & IFCAP_WOL_UCAST) != 0) 3465 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3466 if ((mask & IFCAP_WOL_MCAST) != 0) 3467 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3468 if ((mask & IFCAP_WOL_MAGIC) != 0) 3469 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3470 } 3471 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3472 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3473 re_init_locked(sc); 3474 } 3475 RL_UNLOCK(sc); 3476 VLAN_CAPABILITIES(ifp); 3477 } 3478 break; 3479 default: 3480 error = ether_ioctl(ifp, command, data); 3481 break; 3482 } 3483 3484 return (error); 3485} 3486 3487static void 3488re_watchdog(struct rl_softc *sc) 3489{ 3490 struct ifnet *ifp; 3491 3492 RL_LOCK_ASSERT(sc); 3493 3494 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3495 return; 3496 3497 ifp = sc->rl_ifp; 3498 re_txeof(sc); 3499 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3500 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3501 "-- recovering\n"); 3502 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3503 re_start_locked(ifp); 3504 return; 3505 } 3506 3507 if_printf(ifp, "watchdog timeout\n"); 3508 ifp->if_oerrors++; 3509 3510 re_rxeof(sc, NULL); 3511 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3512 re_init_locked(sc); 3513 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3514 re_start_locked(ifp); 3515} 3516 3517/* 3518 * Stop the adapter and free any mbufs allocated to the 3519 * RX and TX lists. 3520 */ 3521static void 3522re_stop(struct rl_softc *sc) 3523{ 3524 int i; 3525 struct ifnet *ifp; 3526 struct rl_txdesc *txd; 3527 struct rl_rxdesc *rxd; 3528 3529 RL_LOCK_ASSERT(sc); 3530 3531 ifp = sc->rl_ifp; 3532 3533 sc->rl_watchdog_timer = 0; 3534 callout_stop(&sc->rl_stat_callout); 3535 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3536 3537 /* 3538 * Disable accepting frames to put RX MAC into idle state. 3539 * Otherwise it's possible to get frames while stop command 3540 * execution is in progress and controller can DMA the frame 3541 * to already freed RX buffer during that period. 3542 */ 3543 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3544 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3545 RL_RXCFG_RX_BROAD)); 3546 3547 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3548 for (i = RL_TIMEOUT; i > 0; i--) { 3549 if ((CSR_READ_1(sc, sc->rl_txstart) & 3550 RL_TXSTART_START) == 0) 3551 break; 3552 DELAY(20); 3553 } 3554 if (i == 0) 3555 device_printf(sc->rl_dev, 3556 "stopping TX poll timed out!\n"); 3557 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3558 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3559 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3560 RL_CMD_RX_ENB); 3561 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3562 for (i = RL_TIMEOUT; i > 0; i--) { 3563 if ((CSR_READ_4(sc, RL_TXCFG) & 3564 RL_TXCFG_QUEUE_EMPTY) != 0) 3565 break; 3566 DELAY(100); 3567 } 3568 if (i == 0) 3569 device_printf(sc->rl_dev, 3570 "stopping TXQ timed out!\n"); 3571 } 3572 } else 3573 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3574 DELAY(1000); 3575 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3576 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3577 3578 if (sc->rl_head != NULL) { 3579 m_freem(sc->rl_head); 3580 sc->rl_head = sc->rl_tail = NULL; 3581 } 3582 3583 /* Free the TX list buffers. */ 3584 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3585 txd = &sc->rl_ldata.rl_tx_desc[i]; 3586 if (txd->tx_m != NULL) { 3587 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3588 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3589 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3590 txd->tx_dmamap); 3591 m_freem(txd->tx_m); 3592 txd->tx_m = NULL; 3593 } 3594 } 3595 3596 /* Free the RX list buffers. */ 3597 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3598 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3599 if (rxd->rx_m != NULL) { 3600 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3601 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3602 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3603 rxd->rx_dmamap); 3604 m_freem(rxd->rx_m); 3605 rxd->rx_m = NULL; 3606 } 3607 } 3608 3609 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3610 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3611 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3612 if (rxd->rx_m != NULL) { 3613 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3614 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3615 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3616 rxd->rx_dmamap); 3617 m_freem(rxd->rx_m); 3618 rxd->rx_m = NULL; 3619 } 3620 } 3621 } 3622} 3623 3624/* 3625 * Device suspend routine. Stop the interface and save some PCI 3626 * settings in case the BIOS doesn't restore them properly on 3627 * resume. 3628 */ 3629static int 3630re_suspend(device_t dev) 3631{ 3632 struct rl_softc *sc; 3633 3634 sc = device_get_softc(dev); 3635 3636 RL_LOCK(sc); 3637 re_stop(sc); 3638 re_setwol(sc); 3639 sc->suspended = 1; 3640 RL_UNLOCK(sc); 3641 3642 return (0); 3643} 3644 3645/* 3646 * Device resume routine. Restore some PCI settings in case the BIOS 3647 * doesn't, re-enable busmastering, and restart the interface if 3648 * appropriate. 3649 */ 3650static int 3651re_resume(device_t dev) 3652{ 3653 struct rl_softc *sc; 3654 struct ifnet *ifp; 3655 3656 sc = device_get_softc(dev); 3657 3658 RL_LOCK(sc); 3659 3660 ifp = sc->rl_ifp; 3661 /* Take controller out of sleep mode. */ 3662 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3663 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3664 CSR_WRITE_1(sc, RL_GPIO, 3665 CSR_READ_1(sc, RL_GPIO) | 0x01); 3666 } 3667 3668 /* 3669 * Clear WOL matching such that normal Rx filtering 3670 * wouldn't interfere with WOL patterns. 3671 */ 3672 re_clrwol(sc); 3673 3674 /* reinitialize interface if necessary */ 3675 if (ifp->if_flags & IFF_UP) 3676 re_init_locked(sc); 3677 3678 sc->suspended = 0; 3679 RL_UNLOCK(sc); 3680 3681 return (0); 3682} 3683 3684/* 3685 * Stop all chip I/O so that the kernel's probe routines don't 3686 * get confused by errant DMAs when rebooting. 3687 */ 3688static int 3689re_shutdown(device_t dev) 3690{ 3691 struct rl_softc *sc; 3692 3693 sc = device_get_softc(dev); 3694 3695 RL_LOCK(sc); 3696 re_stop(sc); 3697 /* 3698 * Mark interface as down since otherwise we will panic if 3699 * interrupt comes in later on, which can happen in some 3700 * cases. 3701 */ 3702 sc->rl_ifp->if_flags &= ~IFF_UP; 3703 re_setwol(sc); 3704 RL_UNLOCK(sc); 3705 3706 return (0); 3707} 3708 3709static void 3710re_set_linkspeed(struct rl_softc *sc) 3711{ 3712 struct mii_softc *miisc; 3713 struct mii_data *mii; 3714 int aneg, i, phyno; 3715 3716 RL_LOCK_ASSERT(sc); 3717 3718 mii = device_get_softc(sc->rl_miibus); 3719 mii_pollstat(mii); 3720 aneg = 0; 3721 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3722 (IFM_ACTIVE | IFM_AVALID)) { 3723 switch IFM_SUBTYPE(mii->mii_media_active) { 3724 case IFM_10_T: 3725 case IFM_100_TX: 3726 return; 3727 case IFM_1000_T: 3728 aneg++; 3729 break; 3730 default: 3731 break; 3732 } 3733 } 3734 miisc = LIST_FIRST(&mii->mii_phys); 3735 phyno = miisc->mii_phy; 3736 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3737 PHY_RESET(miisc); 3738 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3739 re_miibus_writereg(sc->rl_dev, phyno, 3740 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3741 re_miibus_writereg(sc->rl_dev, phyno, 3742 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3743 DELAY(1000); 3744 if (aneg != 0) { 3745 /* 3746 * Poll link state until re(4) get a 10/100Mbps link. 3747 */ 3748 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3749 mii_pollstat(mii); 3750 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3751 == (IFM_ACTIVE | IFM_AVALID)) { 3752 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3753 case IFM_10_T: 3754 case IFM_100_TX: 3755 return; 3756 default: 3757 break; 3758 } 3759 } 3760 RL_UNLOCK(sc); 3761 pause("relnk", hz); 3762 RL_LOCK(sc); 3763 } 3764 if (i == MII_ANEGTICKS_GIGE) 3765 device_printf(sc->rl_dev, 3766 "establishing a link failed, WOL may not work!"); 3767 } 3768 /* 3769 * No link, force MAC to have 100Mbps, full-duplex link. 3770 * MAC does not require reprogramming on resolved speed/duplex, 3771 * so this is just for completeness. 3772 */ 3773 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3774 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3775} 3776 3777static void 3778re_setwol(struct rl_softc *sc) 3779{ 3780 struct ifnet *ifp; 3781 int pmc; 3782 uint16_t pmstat; 3783 uint8_t v; 3784 3785 RL_LOCK_ASSERT(sc); 3786 3787 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3788 return; 3789 3790 ifp = sc->rl_ifp; 3791 /* Put controller into sleep mode. */ 3792 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3793 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3794 CSR_WRITE_1(sc, RL_GPIO, 3795 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3796 } 3797 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3798 re_set_rxmode(sc); 3799 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3800 re_set_linkspeed(sc); 3801 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3802 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3803 } 3804 /* Enable config register write. */ 3805 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3806 3807 /* Enable PME. */ 3808 v = CSR_READ_1(sc, sc->rl_cfg1); 3809 v &= ~RL_CFG1_PME; 3810 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3811 v |= RL_CFG1_PME; 3812 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3813 3814 v = CSR_READ_1(sc, sc->rl_cfg3); 3815 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3816 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3817 v |= RL_CFG3_WOL_MAGIC; 3818 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3819 3820 v = CSR_READ_1(sc, sc->rl_cfg5); 3821 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3822 RL_CFG5_WOL_LANWAKE); 3823 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3824 v |= RL_CFG5_WOL_UCAST; 3825 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3826 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3827 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3828 v |= RL_CFG5_WOL_LANWAKE; 3829 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3830 3831 /* Config register write done. */ 3832 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3833 3834 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3835 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3836 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3837 /* 3838 * It seems that hardware resets its link speed to 100Mbps in 3839 * power down mode so switching to 100Mbps in driver is not 3840 * needed. 3841 */ 3842 3843 /* Request PME if WOL is requested. */ 3844 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3845 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3846 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3847 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3848 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3849} 3850 3851static void 3852re_clrwol(struct rl_softc *sc) 3853{ 3854 int pmc; 3855 uint8_t v; 3856 3857 RL_LOCK_ASSERT(sc); 3858 3859 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3860 return; 3861 3862 /* Enable config register write. */ 3863 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3864 3865 v = CSR_READ_1(sc, sc->rl_cfg3); 3866 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3867 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3868 3869 /* Config register write done. */ 3870 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3871 3872 v = CSR_READ_1(sc, sc->rl_cfg5); 3873 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3874 v &= ~RL_CFG5_WOL_LANWAKE; 3875 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3876} 3877 3878static void 3879re_add_sysctls(struct rl_softc *sc) 3880{ 3881 struct sysctl_ctx_list *ctx; 3882 struct sysctl_oid_list *children; 3883 int error; 3884 3885 ctx = device_get_sysctl_ctx(sc->rl_dev); 3886 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3887 3888 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3889 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3890 "Statistics Information"); 3891 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3892 return; 3893 3894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3895 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3896 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3897 /* Pull in device tunables. */ 3898 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3899 error = resource_int_value(device_get_name(sc->rl_dev), 3900 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3901 if (error == 0) { 3902 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3903 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3904 device_printf(sc->rl_dev, "int_rx_mod value out of " 3905 "range; using default: %d\n", 3906 RL_TIMER_DEFAULT); 3907 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3908 } 3909 } 3910 3911} 3912 3913static int 3914re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3915{ 3916 struct rl_softc *sc; 3917 struct rl_stats *stats; 3918 int error, i, result; 3919 3920 result = -1; 3921 error = sysctl_handle_int(oidp, &result, 0, req); 3922 if (error || req->newptr == NULL) 3923 return (error); 3924 3925 if (result == 1) { 3926 sc = (struct rl_softc *)arg1; 3927 RL_LOCK(sc); 3928 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3929 RL_UNLOCK(sc); 3930 goto done; 3931 } 3932 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3933 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3934 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3935 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3936 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3937 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3938 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3939 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3940 RL_DUMPSTATS_START)); 3941 for (i = RL_TIMEOUT; i > 0; i--) { 3942 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3943 RL_DUMPSTATS_START) == 0) 3944 break; 3945 DELAY(1000); 3946 } 3947 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3948 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3949 RL_UNLOCK(sc); 3950 if (i == 0) { 3951 device_printf(sc->rl_dev, 3952 "DUMP statistics request timedout\n"); 3953 return (ETIMEDOUT); 3954 } 3955done: 3956 stats = sc->rl_ldata.rl_stats; 3957 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3958 printf("Tx frames : %ju\n", 3959 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3960 printf("Rx frames : %ju\n", 3961 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3962 printf("Tx errors : %ju\n", 3963 (uintmax_t)le64toh(stats->rl_tx_errs)); 3964 printf("Rx errors : %u\n", 3965 le32toh(stats->rl_rx_errs)); 3966 printf("Rx missed frames : %u\n", 3967 (uint32_t)le16toh(stats->rl_missed_pkts)); 3968 printf("Rx frame alignment errs : %u\n", 3969 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3970 printf("Tx single collisions : %u\n", 3971 le32toh(stats->rl_tx_onecoll)); 3972 printf("Tx multiple collisions : %u\n", 3973 le32toh(stats->rl_tx_multicolls)); 3974 printf("Rx unicast frames : %ju\n", 3975 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3976 printf("Rx broadcast frames : %ju\n", 3977 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3978 printf("Rx multicast frames : %u\n", 3979 le32toh(stats->rl_rx_mcasts)); 3980 printf("Tx aborts : %u\n", 3981 (uint32_t)le16toh(stats->rl_tx_aborts)); 3982 printf("Tx underruns : %u\n", 3983 (uint32_t)le16toh(stats->rl_rx_underruns)); 3984 } 3985 3986 return (error); 3987} 3988 3989static int 3990sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3991{ 3992 int error, value; 3993 3994 if (arg1 == NULL) 3995 return (EINVAL); 3996 value = *(int *)arg1; 3997 error = sysctl_handle_int(oidp, &value, 0, req); 3998 if (error || req->newptr == NULL) 3999 return (error); 4000 if (value < low || value > high) 4001 return (EINVAL); 4002 *(int *)arg1 = value; 4003 4004 return (0); 4005} 4006 4007static int 4008sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4009{ 4010 4011 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4012 RL_TIMER_MAX)); 4013} 4014