1/****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41 42/** 43 * e1000_init_mac_ops_generic - Initialize MAC function pointers 44 * @hw: pointer to the HW structure 45 * 46 * Setups up the function pointers to no-op functions 47 **/ 48void e1000_init_mac_ops_generic(struct e1000_hw *hw) 49{ 50 struct e1000_mac_info *mac = &hw->mac; 51 DEBUGFUNC("e1000_init_mac_ops_generic"); 52 53 /* General Setup */ 54 mac->ops.init_params = e1000_null_ops_generic; 55 mac->ops.init_hw = e1000_null_ops_generic; 56 mac->ops.reset_hw = e1000_null_ops_generic; 57 mac->ops.setup_physical_interface = e1000_null_ops_generic; 58 mac->ops.get_bus_info = e1000_null_ops_generic; 59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63 /* LED */ 64 mac->ops.cleanup_led = e1000_null_ops_generic; 65 mac->ops.setup_led = e1000_null_ops_generic; 66 mac->ops.blink_led = e1000_null_ops_generic; 67 mac->ops.led_on = e1000_null_ops_generic; 68 mac->ops.led_off = e1000_null_ops_generic; 69 /* LINK */ 70 mac->ops.setup_link = e1000_null_ops_generic; 71 mac->ops.get_link_up_info = e1000_null_link_info; 72 mac->ops.check_for_link = e1000_null_ops_generic; 73 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 74 /* Management */ 75 mac->ops.check_mng_mode = e1000_null_mng_mode; 76 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 77 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 78 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 79 /* VLAN, MC, etc. */ 80 mac->ops.update_mc_addr_list = e1000_null_update_mc; 81 mac->ops.clear_vfta = e1000_null_mac_generic; 82 mac->ops.write_vfta = e1000_null_write_vfta; 83 mac->ops.rar_set = e1000_rar_set_generic; 84 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 85} 86 87/** 88 * e1000_null_ops_generic - No-op function, returns 0 89 * @hw: pointer to the HW structure 90 **/ 91s32 e1000_null_ops_generic(struct e1000_hw *hw) 92{ 93 DEBUGFUNC("e1000_null_ops_generic"); 94 return E1000_SUCCESS; 95} 96 97/** 98 * e1000_null_mac_generic - No-op function, return void 99 * @hw: pointer to the HW structure 100 **/ 101void e1000_null_mac_generic(struct e1000_hw *hw) 102{ 103 DEBUGFUNC("e1000_null_mac_generic"); 104 return; 105} 106 107/** 108 * e1000_null_link_info - No-op function, return 0 109 * @hw: pointer to the HW structure 110 **/ 111s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 112{ 113 DEBUGFUNC("e1000_null_link_info"); 114 return E1000_SUCCESS; 115} 116 117/** 118 * e1000_null_mng_mode - No-op function, return FALSE 119 * @hw: pointer to the HW structure 120 **/ 121bool e1000_null_mng_mode(struct e1000_hw *hw) 122{ 123 DEBUGFUNC("e1000_null_mng_mode"); 124 return FALSE; 125} 126 127/** 128 * e1000_null_update_mc - No-op function, return void 129 * @hw: pointer to the HW structure 130 **/ 131void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 132{ 133 DEBUGFUNC("e1000_null_update_mc"); 134 return; 135} 136 137/** 138 * e1000_null_write_vfta - No-op function, return void 139 * @hw: pointer to the HW structure 140 **/ 141void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 142{ 143 DEBUGFUNC("e1000_null_write_vfta"); 144 return; 145} 146 147/** 148 * e1000_null_rar_set - No-op function, return void 149 * @hw: pointer to the HW structure 150 **/ 151void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 152{ 153 DEBUGFUNC("e1000_null_rar_set"); 154 return; 155} 156 157/** 158 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 159 * @hw: pointer to the HW structure 160 * 161 * Determines and stores the system bus information for a particular 162 * network interface. The following bus information is determined and stored: 163 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 164 **/ 165s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 166{ 167 struct e1000_mac_info *mac = &hw->mac; 168 struct e1000_bus_info *bus = &hw->bus; 169 u32 status = E1000_READ_REG(hw, E1000_STATUS); 170 s32 ret_val = E1000_SUCCESS; 171 172 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 173 174 /* PCI or PCI-X? */ 175 bus->type = (status & E1000_STATUS_PCIX_MODE) 176 ? e1000_bus_type_pcix 177 : e1000_bus_type_pci; 178 179 /* Bus speed */ 180 if (bus->type == e1000_bus_type_pci) { 181 bus->speed = (status & E1000_STATUS_PCI66) 182 ? e1000_bus_speed_66 183 : e1000_bus_speed_33; 184 } else { 185 switch (status & E1000_STATUS_PCIX_SPEED) { 186 case E1000_STATUS_PCIX_SPEED_66: 187 bus->speed = e1000_bus_speed_66; 188 break; 189 case E1000_STATUS_PCIX_SPEED_100: 190 bus->speed = e1000_bus_speed_100; 191 break; 192 case E1000_STATUS_PCIX_SPEED_133: 193 bus->speed = e1000_bus_speed_133; 194 break; 195 default: 196 bus->speed = e1000_bus_speed_reserved; 197 break; 198 } 199 } 200 201 /* Bus width */ 202 bus->width = (status & E1000_STATUS_BUS64) 203 ? e1000_bus_width_64 204 : e1000_bus_width_32; 205 206 /* Which PCI(-X) function? */ 207 mac->ops.set_lan_id(hw); 208 209 return ret_val; 210} 211 212/** 213 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 214 * @hw: pointer to the HW structure 215 * 216 * Determines and stores the system bus information for a particular 217 * network interface. The following bus information is determined and stored: 218 * bus speed, bus width, type (PCIe), and PCIe function. 219 **/ 220s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 221{ 222 struct e1000_mac_info *mac = &hw->mac; 223 struct e1000_bus_info *bus = &hw->bus; 224 s32 ret_val; 225 u16 pcie_link_status; 226 227 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 228 229 bus->type = e1000_bus_type_pci_express; 230 231 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 232 &pcie_link_status); 233 if (ret_val) { 234 bus->width = e1000_bus_width_unknown; 235 bus->speed = e1000_bus_speed_unknown; 236 } else { 237 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 238 case PCIE_LINK_SPEED_2500: 239 bus->speed = e1000_bus_speed_2500; 240 break; 241 case PCIE_LINK_SPEED_5000: 242 bus->speed = e1000_bus_speed_5000; 243 break; 244 default: 245 bus->speed = e1000_bus_speed_unknown; 246 break; 247 } 248 249 bus->width = (enum e1000_bus_width)((pcie_link_status & 250 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 251 } 252 253 mac->ops.set_lan_id(hw); 254 255 return E1000_SUCCESS; 256} 257 258/** 259 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 260 * 261 * @hw: pointer to the HW structure 262 * 263 * Determines the LAN function id by reading memory-mapped registers 264 * and swaps the port value if requested. 265 **/ 266static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 267{ 268 struct e1000_bus_info *bus = &hw->bus; 269 u32 reg; 270 271 /* 272 * The status register reports the correct function number 273 * for the device regardless of function swap state. 274 */ 275 reg = E1000_READ_REG(hw, E1000_STATUS); 276 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 277} 278 279/** 280 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 281 * @hw: pointer to the HW structure 282 * 283 * Determines the LAN function id by reading PCI config space. 284 **/ 285void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 286{ 287 struct e1000_bus_info *bus = &hw->bus; 288 u16 pci_header_type; 289 u32 status; 290 291 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 292 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 293 status = E1000_READ_REG(hw, E1000_STATUS); 294 bus->func = (status & E1000_STATUS_FUNC_MASK) 295 >> E1000_STATUS_FUNC_SHIFT; 296 } else { 297 bus->func = 0; 298 } 299} 300 301/** 302 * e1000_set_lan_id_single_port - Set LAN id for a single port device 303 * @hw: pointer to the HW structure 304 * 305 * Sets the LAN function id to zero for a single port device. 306 **/ 307void e1000_set_lan_id_single_port(struct e1000_hw *hw) 308{ 309 struct e1000_bus_info *bus = &hw->bus; 310 311 bus->func = 0; 312} 313 314/** 315 * e1000_clear_vfta_generic - Clear VLAN filter table 316 * @hw: pointer to the HW structure 317 * 318 * Clears the register array which contains the VLAN filter table by 319 * setting all the values to 0. 320 **/ 321void e1000_clear_vfta_generic(struct e1000_hw *hw) 322{ 323 u32 offset; 324 325 DEBUGFUNC("e1000_clear_vfta_generic"); 326 327 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 328 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 329 E1000_WRITE_FLUSH(hw); 330 } 331} 332 333/** 334 * e1000_write_vfta_generic - Write value to VLAN filter table 335 * @hw: pointer to the HW structure 336 * @offset: register offset in VLAN filter table 337 * @value: register value written to VLAN filter table 338 * 339 * Writes value at the given offset in the register array which stores 340 * the VLAN filter table. 341 **/ 342void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 343{ 344 DEBUGFUNC("e1000_write_vfta_generic"); 345 346 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 347 E1000_WRITE_FLUSH(hw); 348} 349 350/** 351 * e1000_init_rx_addrs_generic - Initialize receive address's 352 * @hw: pointer to the HW structure 353 * @rar_count: receive address registers 354 * 355 * Setup the receive address registers by setting the base receive address 356 * register to the devices MAC address and clearing all the other receive 357 * address registers to 0. 358 **/ 359void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 360{ 361 u32 i; 362 u8 mac_addr[ETH_ADDR_LEN] = {0}; 363 364 DEBUGFUNC("e1000_init_rx_addrs_generic"); 365 366 /* Setup the receive address */ 367 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 368 369 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 370 371 /* Zero out the other (rar_entry_count - 1) receive addresses */ 372 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 373 for (i = 1; i < rar_count; i++) 374 hw->mac.ops.rar_set(hw, mac_addr, i); 375} 376 377/** 378 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 379 * @hw: pointer to the HW structure 380 * 381 * Checks the nvm for an alternate MAC address. An alternate MAC address 382 * can be setup by pre-boot software and must be treated like a permanent 383 * address and must override the actual permanent MAC address. If an 384 * alternate MAC address is found it is programmed into RAR0, replacing 385 * the permanent address that was installed into RAR0 by the Si on reset. 386 * This function will return SUCCESS unless it encounters an error while 387 * reading the EEPROM. 388 **/ 389s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 390{ 391 u32 i; 392 s32 ret_val = E1000_SUCCESS; 393 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 394 u8 alt_mac_addr[ETH_ADDR_LEN]; 395 396 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 397 398 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 399 if (ret_val) 400 return ret_val; 401 402 /* not supported on older hardware or 82573 */ 403 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 404 return E1000_SUCCESS; 405 406 /* 407 * Alternate MAC address is handled by the option ROM for 82580 408 * and newer. SW support not required. 409 */ 410 if (hw->mac.type >= e1000_82580) 411 return E1000_SUCCESS; 412 413 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 414 &nvm_alt_mac_addr_offset); 415 if (ret_val) { 416 DEBUGOUT("NVM Read Error\n"); 417 return ret_val; 418 } 419 420 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 421 (nvm_alt_mac_addr_offset == 0x0000)) 422 /* There is no Alternate MAC Address */ 423 return E1000_SUCCESS; 424 425 if (hw->bus.func == E1000_FUNC_1) 426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 427 if (hw->bus.func == E1000_FUNC_2) 428 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 429 430 if (hw->bus.func == E1000_FUNC_3) 431 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 432 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 433 offset = nvm_alt_mac_addr_offset + (i >> 1); 434 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 435 if (ret_val) { 436 DEBUGOUT("NVM Read Error\n"); 437 return ret_val; 438 } 439 440 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 441 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 442 } 443 444 /* if multicast bit is set, the alternate address will not be used */ 445 if (alt_mac_addr[0] & 0x01) { 446 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 447 return E1000_SUCCESS; 448 } 449 450 /* 451 * We have a valid alternate MAC address, and we want to treat it the 452 * same as the normal permanent MAC address stored by the HW into the 453 * RAR. Do this by mapping this address into RAR0. 454 */ 455 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 456 457 return E1000_SUCCESS; 458} 459 460/** 461 * e1000_rar_set_generic - Set receive address register 462 * @hw: pointer to the HW structure 463 * @addr: pointer to the receive address 464 * @index: receive address array register 465 * 466 * Sets the receive address array register at index to the address passed 467 * in by addr. 468 **/ 469static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 470{ 471 u32 rar_low, rar_high; 472 473 DEBUGFUNC("e1000_rar_set_generic"); 474 475 /* 476 * HW expects these in little endian so we reverse the byte order 477 * from network order (big endian) to little endian 478 */ 479 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 480 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 481 482 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 483 484 /* If MAC address zero, no need to set the AV bit */ 485 if (rar_low || rar_high) 486 rar_high |= E1000_RAH_AV; 487 488 /* 489 * Some bridges will combine consecutive 32-bit writes into 490 * a single burst write, which will malfunction on some parts. 491 * The flushes avoid this. 492 */ 493 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 494 E1000_WRITE_FLUSH(hw); 495 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 496 E1000_WRITE_FLUSH(hw); 497} 498 499/** 500 * e1000_hash_mc_addr_generic - Generate a multicast hash value 501 * @hw: pointer to the HW structure 502 * @mc_addr: pointer to a multicast address 503 * 504 * Generates a multicast address hash value which is used to determine 505 * the multicast filter table array address and new table value. 506 **/ 507u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 508{ 509 u32 hash_value, hash_mask; 510 u8 bit_shift = 0; 511 512 DEBUGFUNC("e1000_hash_mc_addr_generic"); 513 514 /* Register count multiplied by bits per register */ 515 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 516 517 /* 518 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 519 * where 0xFF would still fall within the hash mask. 520 */ 521 while (hash_mask >> bit_shift != 0xFF) 522 bit_shift++; 523 524 /* 525 * The portion of the address that is used for the hash table 526 * is determined by the mc_filter_type setting. 527 * The algorithm is such that there is a total of 8 bits of shifting. 528 * The bit_shift for a mc_filter_type of 0 represents the number of 529 * left-shifts where the MSB of mc_addr[5] would still fall within 530 * the hash_mask. Case 0 does this exactly. Since there are a total 531 * of 8 bits of shifting, then mc_addr[4] will shift right the 532 * remaining number of bits. Thus 8 - bit_shift. The rest of the 533 * cases are a variation of this algorithm...essentially raising the 534 * number of bits to shift mc_addr[5] left, while still keeping the 535 * 8-bit shifting total. 536 * 537 * For example, given the following Destination MAC Address and an 538 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 539 * we can see that the bit_shift for case 0 is 4. These are the hash 540 * values resulting from each mc_filter_type... 541 * [0] [1] [2] [3] [4] [5] 542 * 01 AA 00 12 34 56 543 * LSB MSB 544 * 545 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 546 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 547 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 548 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 549 */ 550 switch (hw->mac.mc_filter_type) { 551 default: 552 case 0: 553 break; 554 case 1: 555 bit_shift += 1; 556 break; 557 case 2: 558 bit_shift += 2; 559 break; 560 case 3: 561 bit_shift += 4; 562 break; 563 } 564 565 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 566 (((u16) mc_addr[5]) << bit_shift))); 567 568 return hash_value; 569} 570 571/** 572 * e1000_update_mc_addr_list_generic - Update Multicast addresses 573 * @hw: pointer to the HW structure 574 * @mc_addr_list: array of multicast addresses to program 575 * @mc_addr_count: number of multicast addresses to program 576 * 577 * Updates entire Multicast Table Array. 578 * The caller must have a packed mc_addr_list of multicast addresses. 579 **/ 580void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 581 u8 *mc_addr_list, u32 mc_addr_count) 582{ 583 u32 hash_value, hash_bit, hash_reg; 584 int i; 585 586 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 587 588 /* clear mta_shadow */ 589 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 590 591 /* update mta_shadow from mc_addr_list */ 592 for (i = 0; (u32) i < mc_addr_count; i++) { 593 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 594 595 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 596 hash_bit = hash_value & 0x1F; 597 598 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 599 mc_addr_list += (ETH_ADDR_LEN); 600 } 601 602 /* replace the entire MTA table */ 603 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 604 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 605 E1000_WRITE_FLUSH(hw); 606} 607 608/** 609 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 610 * @hw: pointer to the HW structure 611 * 612 * In certain situations, a system BIOS may report that the PCIx maximum 613 * memory read byte count (MMRBC) value is higher than than the actual 614 * value. We check the PCIx command register with the current PCIx status 615 * register. 616 **/ 617void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 618{ 619 u16 cmd_mmrbc; 620 u16 pcix_cmd; 621 u16 pcix_stat_hi_word; 622 u16 stat_mmrbc; 623 624 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 625 626 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 627 if (hw->bus.type != e1000_bus_type_pcix) 628 return; 629 630 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 631 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 632 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 633 PCIX_COMMAND_MMRBC_SHIFT; 634 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 635 PCIX_STATUS_HI_MMRBC_SHIFT; 636 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 637 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 638 if (cmd_mmrbc > stat_mmrbc) { 639 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 640 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 641 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 642 } 643} 644 645/** 646 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 647 * @hw: pointer to the HW structure 648 * 649 * Clears the base hardware counters by reading the counter registers. 650 **/ 651void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 652{ 653 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 654 655 E1000_READ_REG(hw, E1000_CRCERRS); 656 E1000_READ_REG(hw, E1000_SYMERRS); 657 E1000_READ_REG(hw, E1000_MPC); 658 E1000_READ_REG(hw, E1000_SCC); 659 E1000_READ_REG(hw, E1000_ECOL); 660 E1000_READ_REG(hw, E1000_MCC); 661 E1000_READ_REG(hw, E1000_LATECOL); 662 E1000_READ_REG(hw, E1000_COLC); 663 E1000_READ_REG(hw, E1000_DC); 664 E1000_READ_REG(hw, E1000_SEC); 665 E1000_READ_REG(hw, E1000_RLEC); 666 E1000_READ_REG(hw, E1000_XONRXC); 667 E1000_READ_REG(hw, E1000_XONTXC); 668 E1000_READ_REG(hw, E1000_XOFFRXC); 669 E1000_READ_REG(hw, E1000_XOFFTXC); 670 E1000_READ_REG(hw, E1000_FCRUC); 671 E1000_READ_REG(hw, E1000_GPRC); 672 E1000_READ_REG(hw, E1000_BPRC); 673 E1000_READ_REG(hw, E1000_MPRC); 674 E1000_READ_REG(hw, E1000_GPTC); 675 E1000_READ_REG(hw, E1000_GORCL); 676 E1000_READ_REG(hw, E1000_GORCH); 677 E1000_READ_REG(hw, E1000_GOTCL); 678 E1000_READ_REG(hw, E1000_GOTCH); 679 E1000_READ_REG(hw, E1000_RNBC); 680 E1000_READ_REG(hw, E1000_RUC); 681 E1000_READ_REG(hw, E1000_RFC); 682 E1000_READ_REG(hw, E1000_ROC); 683 E1000_READ_REG(hw, E1000_RJC); 684 E1000_READ_REG(hw, E1000_TORL); 685 E1000_READ_REG(hw, E1000_TORH); 686 E1000_READ_REG(hw, E1000_TOTL); 687 E1000_READ_REG(hw, E1000_TOTH); 688 E1000_READ_REG(hw, E1000_TPR); 689 E1000_READ_REG(hw, E1000_TPT); 690 E1000_READ_REG(hw, E1000_MPTC); 691 E1000_READ_REG(hw, E1000_BPTC); 692} 693 694/** 695 * e1000_check_for_copper_link_generic - Check for link (Copper) 696 * @hw: pointer to the HW structure 697 * 698 * Checks to see of the link status of the hardware has changed. If a 699 * change in link status has been detected, then we read the PHY registers 700 * to get the current speed/duplex if link exists. 701 **/ 702s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 703{ 704 struct e1000_mac_info *mac = &hw->mac; 705 s32 ret_val; 706 bool link; 707 708 DEBUGFUNC("e1000_check_for_copper_link"); 709 710 /* 711 * We only want to go out to the PHY registers to see if Auto-Neg 712 * has completed and/or if our link status has changed. The 713 * get_link_status flag is set upon receiving a Link Status 714 * Change or Rx Sequence Error interrupt. 715 */ 716 if (!mac->get_link_status) 717 return E1000_SUCCESS; 718 719 /* 720 * First we want to see if the MII Status Register reports 721 * link. If so, then we want to get the current speed/duplex 722 * of the PHY. 723 */ 724 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 725 if (ret_val) 726 return ret_val; 727 728 if (!link) 729 return E1000_SUCCESS; /* No link detected */ 730 731 mac->get_link_status = FALSE; 732 733 /* 734 * Check if there was DownShift, must be checked 735 * immediately after link-up 736 */ 737 e1000_check_downshift_generic(hw); 738 739 /* 740 * If we are forcing speed/duplex, then we simply return since 741 * we have already determined whether we have link or not. 742 */ 743 if (!mac->autoneg) 744 return -E1000_ERR_CONFIG; 745 746 /* 747 * Auto-Neg is enabled. Auto Speed Detection takes care 748 * of MAC speed/duplex configuration. So we only need to 749 * configure Collision Distance in the MAC. 750 */ 751 mac->ops.config_collision_dist(hw); 752 753 /* 754 * Configure Flow Control now that Auto-Neg has completed. 755 * First, we need to restore the desired flow control 756 * settings because we may have had to re-autoneg with a 757 * different link partner. 758 */ 759 ret_val = e1000_config_fc_after_link_up_generic(hw); 760 if (ret_val) 761 DEBUGOUT("Error configuring flow control\n"); 762 763 return ret_val; 764} 765 766/** 767 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 768 * @hw: pointer to the HW structure 769 * 770 * Checks for link up on the hardware. If link is not up and we have 771 * a signal, then we need to force link up. 772 **/ 773s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 774{ 775 struct e1000_mac_info *mac = &hw->mac; 776 u32 rxcw; 777 u32 ctrl; 778 u32 status; 779 s32 ret_val; 780 781 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 782 783 ctrl = E1000_READ_REG(hw, E1000_CTRL); 784 status = E1000_READ_REG(hw, E1000_STATUS); 785 rxcw = E1000_READ_REG(hw, E1000_RXCW); 786 787 /* 788 * If we don't have link (auto-negotiation failed or link partner 789 * cannot auto-negotiate), the cable is plugged in (we have signal), 790 * and our link partner is not trying to auto-negotiate with us (we 791 * are receiving idles or data), we need to force link up. We also 792 * need to give auto-negotiation time to complete, in case the cable 793 * was just plugged in. The autoneg_failed flag does this. 794 */ 795 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 796 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 797 !(rxcw & E1000_RXCW_C)) { 798 if (!mac->autoneg_failed) { 799 mac->autoneg_failed = TRUE; 800 return E1000_SUCCESS; 801 } 802 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 803 804 /* Disable auto-negotiation in the TXCW register */ 805 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 806 807 /* Force link-up and also force full-duplex. */ 808 ctrl = E1000_READ_REG(hw, E1000_CTRL); 809 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 810 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 811 812 /* Configure Flow Control after forcing link up. */ 813 ret_val = e1000_config_fc_after_link_up_generic(hw); 814 if (ret_val) { 815 DEBUGOUT("Error configuring flow control\n"); 816 return ret_val; 817 } 818 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 819 /* 820 * If we are forcing link and we are receiving /C/ ordered 821 * sets, re-enable auto-negotiation in the TXCW register 822 * and disable forced link in the Device Control register 823 * in an attempt to auto-negotiate with our link partner. 824 */ 825 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 826 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 827 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 828 829 mac->serdes_has_link = TRUE; 830 } 831 832 return E1000_SUCCESS; 833} 834 835/** 836 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 837 * @hw: pointer to the HW structure 838 * 839 * Checks for link up on the hardware. If link is not up and we have 840 * a signal, then we need to force link up. 841 **/ 842s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 843{ 844 struct e1000_mac_info *mac = &hw->mac; 845 u32 rxcw; 846 u32 ctrl; 847 u32 status; 848 s32 ret_val; 849 850 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 851 852 ctrl = E1000_READ_REG(hw, E1000_CTRL); 853 status = E1000_READ_REG(hw, E1000_STATUS); 854 rxcw = E1000_READ_REG(hw, E1000_RXCW); 855 856 /* 857 * If we don't have link (auto-negotiation failed or link partner 858 * cannot auto-negotiate), and our link partner is not trying to 859 * auto-negotiate with us (we are receiving idles or data), 860 * we need to force link up. We also need to give auto-negotiation 861 * time to complete. 862 */ 863 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 864 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 865 if (!mac->autoneg_failed) { 866 mac->autoneg_failed = TRUE; 867 return E1000_SUCCESS; 868 } 869 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 870 871 /* Disable auto-negotiation in the TXCW register */ 872 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 873 874 /* Force link-up and also force full-duplex. */ 875 ctrl = E1000_READ_REG(hw, E1000_CTRL); 876 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 877 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 878 879 /* Configure Flow Control after forcing link up. */ 880 ret_val = e1000_config_fc_after_link_up_generic(hw); 881 if (ret_val) { 882 DEBUGOUT("Error configuring flow control\n"); 883 return ret_val; 884 } 885 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 886 /* 887 * If we are forcing link and we are receiving /C/ ordered 888 * sets, re-enable auto-negotiation in the TXCW register 889 * and disable forced link in the Device Control register 890 * in an attempt to auto-negotiate with our link partner. 891 */ 892 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 893 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 894 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 895 896 mac->serdes_has_link = TRUE; 897 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 898 /* 899 * If we force link for non-auto-negotiation switch, check 900 * link status based on MAC synchronization for internal 901 * serdes media type. 902 */ 903 /* SYNCH bit and IV bit are sticky. */ 904 usec_delay(10); 905 rxcw = E1000_READ_REG(hw, E1000_RXCW); 906 if (rxcw & E1000_RXCW_SYNCH) { 907 if (!(rxcw & E1000_RXCW_IV)) { 908 mac->serdes_has_link = TRUE; 909 DEBUGOUT("SERDES: Link up - forced.\n"); 910 } 911 } else { 912 mac->serdes_has_link = FALSE; 913 DEBUGOUT("SERDES: Link down - force failed.\n"); 914 } 915 } 916 917 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 918 status = E1000_READ_REG(hw, E1000_STATUS); 919 if (status & E1000_STATUS_LU) { 920 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 921 usec_delay(10); 922 rxcw = E1000_READ_REG(hw, E1000_RXCW); 923 if (rxcw & E1000_RXCW_SYNCH) { 924 if (!(rxcw & E1000_RXCW_IV)) { 925 mac->serdes_has_link = TRUE; 926 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 927 } else { 928 mac->serdes_has_link = FALSE; 929 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 930 } 931 } else { 932 mac->serdes_has_link = FALSE; 933 DEBUGOUT("SERDES: Link down - no sync.\n"); 934 } 935 } else { 936 mac->serdes_has_link = FALSE; 937 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 938 } 939 } 940 941 return E1000_SUCCESS; 942} 943 944/** 945 * e1000_set_default_fc_generic - Set flow control default values 946 * @hw: pointer to the HW structure 947 * 948 * Read the EEPROM for the default values for flow control and store the 949 * values. 950 **/ 951s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 952{ 953 s32 ret_val; 954 u16 nvm_data; 955 956 DEBUGFUNC("e1000_set_default_fc_generic"); 957 958 /* 959 * Read and store word 0x0F of the EEPROM. This word contains bits 960 * that determine the hardware's default PAUSE (flow control) mode, 961 * a bit that determines whether the HW defaults to enabling or 962 * disabling auto-negotiation, and the direction of the 963 * SW defined pins. If there is no SW over-ride of the flow 964 * control setting, then the variable hw->fc will 965 * be initialized based on a value in the EEPROM. 966 */ 967 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 968 969 if (ret_val) { 970 DEBUGOUT("NVM Read Error\n"); 971 return ret_val; 972 } 973 974 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 975 hw->fc.requested_mode = e1000_fc_none; 976 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 977 NVM_WORD0F_ASM_DIR) 978 hw->fc.requested_mode = e1000_fc_tx_pause; 979 else 980 hw->fc.requested_mode = e1000_fc_full; 981 982 return E1000_SUCCESS; 983} 984 985/** 986 * e1000_setup_link_generic - Setup flow control and link settings 987 * @hw: pointer to the HW structure 988 * 989 * Determines which flow control settings to use, then configures flow 990 * control. Calls the appropriate media-specific link configuration 991 * function. Assuming the adapter has a valid link partner, a valid link 992 * should be established. Assumes the hardware has previously been reset 993 * and the transmitter and receiver are not enabled. 994 **/ 995s32 e1000_setup_link_generic(struct e1000_hw *hw) 996{ 997 s32 ret_val; 998 999 DEBUGFUNC("e1000_setup_link_generic"); 1000 1001 /* 1002 * In the case of the phy reset being blocked, we already have a link. 1003 * We do not need to set it up again. 1004 */ 1005 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1006 return E1000_SUCCESS; 1007 1008 /* 1009 * If requested flow control is set to default, set flow control 1010 * based on the EEPROM flow control settings. 1011 */ 1012 if (hw->fc.requested_mode == e1000_fc_default) { 1013 ret_val = e1000_set_default_fc_generic(hw); 1014 if (ret_val) 1015 return ret_val; 1016 } 1017 1018 /* 1019 * Save off the requested flow control mode for use later. Depending 1020 * on the link partner's capabilities, we may or may not use this mode. 1021 */ 1022 hw->fc.current_mode = hw->fc.requested_mode; 1023 1024 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1025 hw->fc.current_mode); 1026 1027 /* Call the necessary media_type subroutine to configure the link. */ 1028 ret_val = hw->mac.ops.setup_physical_interface(hw); 1029 if (ret_val) 1030 return ret_val; 1031 1032 /* 1033 * Initialize the flow control address, type, and PAUSE timer 1034 * registers to their default values. This is done even if flow 1035 * control is disabled, because it does not hurt anything to 1036 * initialize these registers. 1037 */ 1038 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1039 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1040 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1041 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1042 1043 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1044 1045 return e1000_set_fc_watermarks_generic(hw); 1046} 1047 1048/** 1049 * e1000_commit_fc_settings_generic - Configure flow control 1050 * @hw: pointer to the HW structure 1051 * 1052 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1053 * base on the flow control settings in e1000_mac_info. 1054 **/ 1055s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1056{ 1057 struct e1000_mac_info *mac = &hw->mac; 1058 u32 txcw; 1059 1060 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1061 1062 /* 1063 * Check for a software override of the flow control settings, and 1064 * setup the device accordingly. If auto-negotiation is enabled, then 1065 * software will have to set the "PAUSE" bits to the correct value in 1066 * the Transmit Config Word Register (TXCW) and re-start auto- 1067 * negotiation. However, if auto-negotiation is disabled, then 1068 * software will have to manually configure the two flow control enable 1069 * bits in the CTRL register. 1070 * 1071 * The possible values of the "fc" parameter are: 1072 * 0: Flow control is completely disabled 1073 * 1: Rx flow control is enabled (we can receive pause frames, 1074 * but not send pause frames). 1075 * 2: Tx flow control is enabled (we can send pause frames but we 1076 * do not support receiving pause frames). 1077 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1078 */ 1079 switch (hw->fc.current_mode) { 1080 case e1000_fc_none: 1081 /* Flow control completely disabled by a software over-ride. */ 1082 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1083 break; 1084 case e1000_fc_rx_pause: 1085 /* 1086 * Rx Flow control is enabled and Tx Flow control is disabled 1087 * by a software over-ride. Since there really isn't a way to 1088 * advertise that we are capable of Rx Pause ONLY, we will 1089 * advertise that we support both symmetric and asymmetric Rx 1090 * PAUSE. Later, we will disable the adapter's ability to send 1091 * PAUSE frames. 1092 */ 1093 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1094 break; 1095 case e1000_fc_tx_pause: 1096 /* 1097 * Tx Flow control is enabled, and Rx Flow control is disabled, 1098 * by a software over-ride. 1099 */ 1100 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1101 break; 1102 case e1000_fc_full: 1103 /* 1104 * Flow control (both Rx and Tx) is enabled by a software 1105 * over-ride. 1106 */ 1107 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1108 break; 1109 default: 1110 DEBUGOUT("Flow control param set incorrectly\n"); 1111 return -E1000_ERR_CONFIG; 1112 break; 1113 } 1114 1115 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1116 mac->txcw = txcw; 1117 1118 return E1000_SUCCESS; 1119} 1120 1121/** 1122 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1123 * @hw: pointer to the HW structure 1124 * 1125 * Polls for link up by reading the status register, if link fails to come 1126 * up with auto-negotiation, then the link is forced if a signal is detected. 1127 **/ 1128s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1129{ 1130 struct e1000_mac_info *mac = &hw->mac; 1131 u32 i, status; 1132 s32 ret_val; 1133 1134 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1135 1136 /* 1137 * If we have a signal (the cable is plugged in, or assumed TRUE for 1138 * serdes media) then poll for a "Link-Up" indication in the Device 1139 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1140 * seconds (Auto-negotiation should complete in less than 500 1141 * milliseconds even if the other end is doing it in SW). 1142 */ 1143 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1144 msec_delay(10); 1145 status = E1000_READ_REG(hw, E1000_STATUS); 1146 if (status & E1000_STATUS_LU) 1147 break; 1148 } 1149 if (i == FIBER_LINK_UP_LIMIT) { 1150 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1151 mac->autoneg_failed = TRUE; 1152 /* 1153 * AutoNeg failed to achieve a link, so we'll call 1154 * mac->check_for_link. This routine will force the 1155 * link up if we detect a signal. This will allow us to 1156 * communicate with non-autonegotiating link partners. 1157 */ 1158 ret_val = mac->ops.check_for_link(hw); 1159 if (ret_val) { 1160 DEBUGOUT("Error while checking for link\n"); 1161 return ret_val; 1162 } 1163 mac->autoneg_failed = FALSE; 1164 } else { 1165 mac->autoneg_failed = FALSE; 1166 DEBUGOUT("Valid Link Found\n"); 1167 } 1168 1169 return E1000_SUCCESS; 1170} 1171 1172/** 1173 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1174 * @hw: pointer to the HW structure 1175 * 1176 * Configures collision distance and flow control for fiber and serdes 1177 * links. Upon successful setup, poll for link. 1178 **/ 1179s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1180{ 1181 u32 ctrl; 1182 s32 ret_val; 1183 1184 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1185 1186 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1187 1188 /* Take the link out of reset */ 1189 ctrl &= ~E1000_CTRL_LRST; 1190 1191 hw->mac.ops.config_collision_dist(hw); 1192 1193 ret_val = e1000_commit_fc_settings_generic(hw); 1194 if (ret_val) 1195 return ret_val; 1196 1197 /* 1198 * Since auto-negotiation is enabled, take the link out of reset (the 1199 * link will be in reset, because we previously reset the chip). This 1200 * will restart auto-negotiation. If auto-negotiation is successful 1201 * then the link-up status bit will be set and the flow control enable 1202 * bits (RFCE and TFCE) will be set according to their negotiated value. 1203 */ 1204 DEBUGOUT("Auto-negotiation enabled\n"); 1205 1206 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1207 E1000_WRITE_FLUSH(hw); 1208 msec_delay(1); 1209 1210 /* 1211 * For these adapters, the SW definable pin 1 is set when the optics 1212 * detect a signal. If we have a signal, then poll for a "Link-Up" 1213 * indication. 1214 */ 1215 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1216 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1217 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1218 } else { 1219 DEBUGOUT("No signal detected\n"); 1220 } 1221 1222 return ret_val; 1223} 1224 1225/** 1226 * e1000_config_collision_dist_generic - Configure collision distance 1227 * @hw: pointer to the HW structure 1228 * 1229 * Configures the collision distance to the default value and is used 1230 * during link setup. 1231 **/ 1232static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1233{ 1234 u32 tctl; 1235 1236 DEBUGFUNC("e1000_config_collision_dist_generic"); 1237 1238 tctl = E1000_READ_REG(hw, E1000_TCTL); 1239 1240 tctl &= ~E1000_TCTL_COLD; 1241 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1242 1243 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1244 E1000_WRITE_FLUSH(hw); 1245} 1246 1247/** 1248 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1249 * @hw: pointer to the HW structure 1250 * 1251 * Sets the flow control high/low threshold (watermark) registers. If 1252 * flow control XON frame transmission is enabled, then set XON frame 1253 * transmission as well. 1254 **/ 1255s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1256{ 1257 u32 fcrtl = 0, fcrth = 0; 1258 1259 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1260 1261 /* 1262 * Set the flow control receive threshold registers. Normally, 1263 * these registers will be set to a default threshold that may be 1264 * adjusted later by the driver's runtime code. However, if the 1265 * ability to transmit pause frames is not enabled, then these 1266 * registers will be set to 0. 1267 */ 1268 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1269 /* 1270 * We need to set up the Receive Threshold high and low water 1271 * marks as well as (optionally) enabling the transmission of 1272 * XON frames. 1273 */ 1274 fcrtl = hw->fc.low_water; 1275 if (hw->fc.send_xon) 1276 fcrtl |= E1000_FCRTL_XONE; 1277 1278 fcrth = hw->fc.high_water; 1279 } 1280 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1281 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1282 1283 return E1000_SUCCESS; 1284} 1285 1286/** 1287 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1288 * @hw: pointer to the HW structure 1289 * 1290 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1291 * device control register to reflect the adapter settings. TFCE and RFCE 1292 * need to be explicitly set by software when a copper PHY is used because 1293 * autonegotiation is managed by the PHY rather than the MAC. Software must 1294 * also configure these bits when link is forced on a fiber connection. 1295 **/ 1296s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1297{ 1298 u32 ctrl; 1299 1300 DEBUGFUNC("e1000_force_mac_fc_generic"); 1301 1302 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1303 1304 /* 1305 * Because we didn't get link via the internal auto-negotiation 1306 * mechanism (we either forced link or we got link via PHY 1307 * auto-neg), we have to manually enable/disable transmit an 1308 * receive flow control. 1309 * 1310 * The "Case" statement below enables/disable flow control 1311 * according to the "hw->fc.current_mode" parameter. 1312 * 1313 * The possible values of the "fc" parameter are: 1314 * 0: Flow control is completely disabled 1315 * 1: Rx flow control is enabled (we can receive pause 1316 * frames but not send pause frames). 1317 * 2: Tx flow control is enabled (we can send pause frames 1318 * frames but we do not receive pause frames). 1319 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1320 * other: No other values should be possible at this point. 1321 */ 1322 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1323 1324 switch (hw->fc.current_mode) { 1325 case e1000_fc_none: 1326 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1327 break; 1328 case e1000_fc_rx_pause: 1329 ctrl &= (~E1000_CTRL_TFCE); 1330 ctrl |= E1000_CTRL_RFCE; 1331 break; 1332 case e1000_fc_tx_pause: 1333 ctrl &= (~E1000_CTRL_RFCE); 1334 ctrl |= E1000_CTRL_TFCE; 1335 break; 1336 case e1000_fc_full: 1337 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1338 break; 1339 default: 1340 DEBUGOUT("Flow control param set incorrectly\n"); 1341 return -E1000_ERR_CONFIG; 1342 } 1343 1344 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1345 1346 return E1000_SUCCESS; 1347} 1348 1349/** 1350 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1351 * @hw: pointer to the HW structure 1352 * 1353 * Checks the status of auto-negotiation after link up to ensure that the 1354 * speed and duplex were not forced. If the link needed to be forced, then 1355 * flow control needs to be forced also. If auto-negotiation is enabled 1356 * and did not fail, then we configure flow control based on our link 1357 * partner. 1358 **/ 1359s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1360{ 1361 struct e1000_mac_info *mac = &hw->mac; 1362 s32 ret_val = E1000_SUCCESS; 1363 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1364 u16 speed, duplex; 1365 1366 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1367 1368 /* 1369 * Check for the case where we have fiber media and auto-neg failed 1370 * so we had to force link. In this case, we need to force the 1371 * configuration of the MAC to match the "fc" parameter. 1372 */ 1373 if (mac->autoneg_failed) { 1374 if (hw->phy.media_type == e1000_media_type_fiber || 1375 hw->phy.media_type == e1000_media_type_internal_serdes) 1376 ret_val = e1000_force_mac_fc_generic(hw); 1377 } else { 1378 if (hw->phy.media_type == e1000_media_type_copper) 1379 ret_val = e1000_force_mac_fc_generic(hw); 1380 } 1381 1382 if (ret_val) { 1383 DEBUGOUT("Error forcing flow control settings\n"); 1384 return ret_val; 1385 } 1386 1387 /* 1388 * Check for the case where we have copper media and auto-neg is 1389 * enabled. In this case, we need to check and see if Auto-Neg 1390 * has completed, and if so, how the PHY and link partner has 1391 * flow control configured. 1392 */ 1393 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1394 /* 1395 * Read the MII Status Register and check to see if AutoNeg 1396 * has completed. We read this twice because this reg has 1397 * some "sticky" (latched) bits. 1398 */ 1399 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1400 if (ret_val) 1401 return ret_val; 1402 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1403 if (ret_val) 1404 return ret_val; 1405 1406 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1407 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1408 return ret_val; 1409 } 1410 1411 /* 1412 * The AutoNeg process has completed, so we now need to 1413 * read both the Auto Negotiation Advertisement 1414 * Register (Address 4) and the Auto_Negotiation Base 1415 * Page Ability Register (Address 5) to determine how 1416 * flow control was negotiated. 1417 */ 1418 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1419 &mii_nway_adv_reg); 1420 if (ret_val) 1421 return ret_val; 1422 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1423 &mii_nway_lp_ability_reg); 1424 if (ret_val) 1425 return ret_val; 1426 1427 /* 1428 * Two bits in the Auto Negotiation Advertisement Register 1429 * (Address 4) and two bits in the Auto Negotiation Base 1430 * Page Ability Register (Address 5) determine flow control 1431 * for both the PHY and the link partner. The following 1432 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1433 * 1999, describes these PAUSE resolution bits and how flow 1434 * control is determined based upon these settings. 1435 * NOTE: DC = Don't Care 1436 * 1437 * LOCAL DEVICE | LINK PARTNER 1438 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1439 *-------|---------|-------|---------|-------------------- 1440 * 0 | 0 | DC | DC | e1000_fc_none 1441 * 0 | 1 | 0 | DC | e1000_fc_none 1442 * 0 | 1 | 1 | 0 | e1000_fc_none 1443 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1444 * 1 | 0 | 0 | DC | e1000_fc_none 1445 * 1 | DC | 1 | DC | e1000_fc_full 1446 * 1 | 1 | 0 | 0 | e1000_fc_none 1447 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1448 * 1449 * Are both PAUSE bits set to 1? If so, this implies 1450 * Symmetric Flow Control is enabled at both ends. The 1451 * ASM_DIR bits are irrelevant per the spec. 1452 * 1453 * For Symmetric Flow Control: 1454 * 1455 * LOCAL DEVICE | LINK PARTNER 1456 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1457 *-------|---------|-------|---------|-------------------- 1458 * 1 | DC | 1 | DC | E1000_fc_full 1459 * 1460 */ 1461 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1462 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1463 /* 1464 * Now we need to check if the user selected Rx ONLY 1465 * of pause frames. In this case, we had to advertise 1466 * FULL flow control because we could not advertise Rx 1467 * ONLY. Hence, we must now check to see if we need to 1468 * turn OFF the TRANSMISSION of PAUSE frames. 1469 */ 1470 if (hw->fc.requested_mode == e1000_fc_full) { 1471 hw->fc.current_mode = e1000_fc_full; 1472 DEBUGOUT("Flow Control = FULL.\n"); 1473 } else { 1474 hw->fc.current_mode = e1000_fc_rx_pause; 1475 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1476 } 1477 } 1478 /* 1479 * For receiving PAUSE frames ONLY. 1480 * 1481 * LOCAL DEVICE | LINK PARTNER 1482 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1483 *-------|---------|-------|---------|-------------------- 1484 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1485 */ 1486 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1487 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1488 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1489 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1490 hw->fc.current_mode = e1000_fc_tx_pause; 1491 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1492 } 1493 /* 1494 * For transmitting PAUSE frames ONLY. 1495 * 1496 * LOCAL DEVICE | LINK PARTNER 1497 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1498 *-------|---------|-------|---------|-------------------- 1499 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1500 */ 1501 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1502 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1503 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1504 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1505 hw->fc.current_mode = e1000_fc_rx_pause; 1506 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1507 } else { 1508 /* 1509 * Per the IEEE spec, at this point flow control 1510 * should be disabled. 1511 */ 1512 hw->fc.current_mode = e1000_fc_none; 1513 DEBUGOUT("Flow Control = NONE.\n"); 1514 } 1515 1516 /* 1517 * Now we need to do one last check... If we auto- 1518 * negotiated to HALF DUPLEX, flow control should not be 1519 * enabled per IEEE 802.3 spec. 1520 */ 1521 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1522 if (ret_val) { 1523 DEBUGOUT("Error getting link speed and duplex\n"); 1524 return ret_val; 1525 } 1526 1527 if (duplex == HALF_DUPLEX) 1528 hw->fc.current_mode = e1000_fc_none; 1529 1530 /* 1531 * Now we call a subroutine to actually force the MAC 1532 * controller to use the correct flow control settings. 1533 */ 1534 ret_val = e1000_force_mac_fc_generic(hw); 1535 if (ret_val) { 1536 DEBUGOUT("Error forcing flow control settings\n"); 1537 return ret_val; 1538 } 1539 } 1540 1541 return E1000_SUCCESS; 1542} 1543 1544/** 1545 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1546 * @hw: pointer to the HW structure 1547 * @speed: stores the current speed 1548 * @duplex: stores the current duplex 1549 * 1550 * Read the status register for the current speed/duplex and store the current 1551 * speed and duplex for copper connections. 1552 **/ 1553s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1554 u16 *duplex) 1555{ 1556 u32 status; 1557 1558 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1559 1560 status = E1000_READ_REG(hw, E1000_STATUS); 1561 if (status & E1000_STATUS_SPEED_1000) { 1562 *speed = SPEED_1000; 1563 DEBUGOUT("1000 Mbs, "); 1564 } else if (status & E1000_STATUS_SPEED_100) { 1565 *speed = SPEED_100; 1566 DEBUGOUT("100 Mbs, "); 1567 } else { 1568 *speed = SPEED_10; 1569 DEBUGOUT("10 Mbs, "); 1570 } 1571 1572 if (status & E1000_STATUS_FD) { 1573 *duplex = FULL_DUPLEX; 1574 DEBUGOUT("Full Duplex\n"); 1575 } else { 1576 *duplex = HALF_DUPLEX; 1577 DEBUGOUT("Half Duplex\n"); 1578 } 1579 1580 return E1000_SUCCESS; 1581} 1582 1583/** 1584 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1585 * @hw: pointer to the HW structure 1586 * @speed: stores the current speed 1587 * @duplex: stores the current duplex 1588 * 1589 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1590 * for fiber/serdes links. 1591 **/ 1592s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1593 u16 *speed, u16 *duplex) 1594{ 1595 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1596 1597 *speed = SPEED_1000; 1598 *duplex = FULL_DUPLEX; 1599 1600 return E1000_SUCCESS; 1601} 1602 1603/** 1604 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1605 * @hw: pointer to the HW structure 1606 * 1607 * Acquire the HW semaphore to access the PHY or NVM 1608 **/ 1609s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1610{ 1611 u32 swsm; 1612 s32 timeout = hw->nvm.word_size + 1; 1613 s32 i = 0; 1614 1615 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1616 1617 /* Get the SW semaphore */ 1618 while (i < timeout) { 1619 swsm = E1000_READ_REG(hw, E1000_SWSM); 1620 if (!(swsm & E1000_SWSM_SMBI)) 1621 break; 1622 1623 usec_delay(50); 1624 i++; 1625 } 1626 1627 if (i == timeout) { 1628 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1629 return -E1000_ERR_NVM; 1630 } 1631 1632 /* Get the FW semaphore. */ 1633 for (i = 0; i < timeout; i++) { 1634 swsm = E1000_READ_REG(hw, E1000_SWSM); 1635 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1636 1637 /* Semaphore acquired if bit latched */ 1638 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1639 break; 1640 1641 usec_delay(50); 1642 } 1643 1644 if (i == timeout) { 1645 /* Release semaphores */ 1646 e1000_put_hw_semaphore_generic(hw); 1647 DEBUGOUT("Driver can't access the NVM\n"); 1648 return -E1000_ERR_NVM; 1649 } 1650 1651 return E1000_SUCCESS; 1652} 1653 1654/** 1655 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1656 * @hw: pointer to the HW structure 1657 * 1658 * Release hardware semaphore used to access the PHY or NVM 1659 **/ 1660void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1661{ 1662 u32 swsm; 1663 1664 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1665 1666 swsm = E1000_READ_REG(hw, E1000_SWSM); 1667 1668 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1669 1670 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1671} 1672 1673/** 1674 * e1000_get_auto_rd_done_generic - Check for auto read completion 1675 * @hw: pointer to the HW structure 1676 * 1677 * Check EEPROM for Auto Read done bit. 1678 **/ 1679s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1680{ 1681 s32 i = 0; 1682 1683 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1684 1685 while (i < AUTO_READ_DONE_TIMEOUT) { 1686 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1687 break; 1688 msec_delay(1); 1689 i++; 1690 } 1691 1692 if (i == AUTO_READ_DONE_TIMEOUT) { 1693 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1694 return -E1000_ERR_RESET; 1695 } 1696 1697 return E1000_SUCCESS; 1698} 1699 1700/** 1701 * e1000_valid_led_default_generic - Verify a valid default LED config 1702 * @hw: pointer to the HW structure 1703 * @data: pointer to the NVM (EEPROM) 1704 * 1705 * Read the EEPROM for the current default LED configuration. If the 1706 * LED configuration is not valid, set to a valid LED configuration. 1707 **/ 1708s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1709{ 1710 s32 ret_val; 1711 1712 DEBUGFUNC("e1000_valid_led_default_generic"); 1713 1714 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1715 if (ret_val) { 1716 DEBUGOUT("NVM Read Error\n"); 1717 return ret_val; 1718 } 1719 1720 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1721 *data = ID_LED_DEFAULT; 1722 1723 return E1000_SUCCESS; 1724} 1725 1726/** 1727 * e1000_id_led_init_generic - 1728 * @hw: pointer to the HW structure 1729 * 1730 **/ 1731s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1732{ 1733 struct e1000_mac_info *mac = &hw->mac; 1734 s32 ret_val; 1735 const u32 ledctl_mask = 0x000000FF; 1736 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1737 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1738 u16 data, i, temp; 1739 const u16 led_mask = 0x0F; 1740 1741 DEBUGFUNC("e1000_id_led_init_generic"); 1742 1743 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1744 if (ret_val) 1745 return ret_val; 1746 1747 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1748 mac->ledctl_mode1 = mac->ledctl_default; 1749 mac->ledctl_mode2 = mac->ledctl_default; 1750 1751 for (i = 0; i < 4; i++) { 1752 temp = (data >> (i << 2)) & led_mask; 1753 switch (temp) { 1754 case ID_LED_ON1_DEF2: 1755 case ID_LED_ON1_ON2: 1756 case ID_LED_ON1_OFF2: 1757 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1758 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1759 break; 1760 case ID_LED_OFF1_DEF2: 1761 case ID_LED_OFF1_ON2: 1762 case ID_LED_OFF1_OFF2: 1763 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1764 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1765 break; 1766 default: 1767 /* Do nothing */ 1768 break; 1769 } 1770 switch (temp) { 1771 case ID_LED_DEF1_ON2: 1772 case ID_LED_ON1_ON2: 1773 case ID_LED_OFF1_ON2: 1774 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1775 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1776 break; 1777 case ID_LED_DEF1_OFF2: 1778 case ID_LED_ON1_OFF2: 1779 case ID_LED_OFF1_OFF2: 1780 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1781 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1782 break; 1783 default: 1784 /* Do nothing */ 1785 break; 1786 } 1787 } 1788 1789 return E1000_SUCCESS; 1790} 1791 1792/** 1793 * e1000_setup_led_generic - Configures SW controllable LED 1794 * @hw: pointer to the HW structure 1795 * 1796 * This prepares the SW controllable LED for use and saves the current state 1797 * of the LED so it can be later restored. 1798 **/ 1799s32 e1000_setup_led_generic(struct e1000_hw *hw) 1800{ 1801 u32 ledctl; 1802 1803 DEBUGFUNC("e1000_setup_led_generic"); 1804 1805 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1806 return -E1000_ERR_CONFIG; 1807 1808 if (hw->phy.media_type == e1000_media_type_fiber) { 1809 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1810 hw->mac.ledctl_default = ledctl; 1811 /* Turn off LED0 */ 1812 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1813 E1000_LEDCTL_LED0_MODE_MASK); 1814 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1815 E1000_LEDCTL_LED0_MODE_SHIFT); 1816 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1817 } else if (hw->phy.media_type == e1000_media_type_copper) { 1818 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1819 } 1820 1821 return E1000_SUCCESS; 1822} 1823 1824/** 1825 * e1000_cleanup_led_generic - Set LED config to default operation 1826 * @hw: pointer to the HW structure 1827 * 1828 * Remove the current LED configuration and set the LED configuration 1829 * to the default value, saved from the EEPROM. 1830 **/ 1831s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1832{ 1833 DEBUGFUNC("e1000_cleanup_led_generic"); 1834 1835 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1836 return E1000_SUCCESS; 1837} 1838 1839/** 1840 * e1000_blink_led_generic - Blink LED 1841 * @hw: pointer to the HW structure 1842 * 1843 * Blink the LEDs which are set to be on. 1844 **/ 1845s32 e1000_blink_led_generic(struct e1000_hw *hw) 1846{ 1847 u32 ledctl_blink = 0; 1848 u32 i; 1849 1850 DEBUGFUNC("e1000_blink_led_generic"); 1851 1852 if (hw->phy.media_type == e1000_media_type_fiber) { 1853 /* always blink LED0 for PCI-E fiber */ 1854 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1855 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1856 } else { 1857 /* 1858 * set the blink bit for each LED that's "on" (0x0E) 1859 * in ledctl_mode2 1860 */ 1861 ledctl_blink = hw->mac.ledctl_mode2; 1862 for (i = 0; i < 4; i++) 1863 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1864 E1000_LEDCTL_MODE_LED_ON) 1865 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1866 (i * 8)); 1867 } 1868 1869 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1870 1871 return E1000_SUCCESS; 1872} 1873 1874/** 1875 * e1000_led_on_generic - Turn LED on 1876 * @hw: pointer to the HW structure 1877 * 1878 * Turn LED on. 1879 **/ 1880s32 e1000_led_on_generic(struct e1000_hw *hw) 1881{ 1882 u32 ctrl; 1883 1884 DEBUGFUNC("e1000_led_on_generic"); 1885 1886 switch (hw->phy.media_type) { 1887 case e1000_media_type_fiber: 1888 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1889 ctrl &= ~E1000_CTRL_SWDPIN0; 1890 ctrl |= E1000_CTRL_SWDPIO0; 1891 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1892 break; 1893 case e1000_media_type_copper: 1894 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1895 break; 1896 default: 1897 break; 1898 } 1899 1900 return E1000_SUCCESS; 1901} 1902 1903/** 1904 * e1000_led_off_generic - Turn LED off 1905 * @hw: pointer to the HW structure 1906 * 1907 * Turn LED off. 1908 **/ 1909s32 e1000_led_off_generic(struct e1000_hw *hw) 1910{ 1911 u32 ctrl; 1912 1913 DEBUGFUNC("e1000_led_off_generic"); 1914 1915 switch (hw->phy.media_type) { 1916 case e1000_media_type_fiber: 1917 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1918 ctrl |= E1000_CTRL_SWDPIN0; 1919 ctrl |= E1000_CTRL_SWDPIO0; 1920 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1921 break; 1922 case e1000_media_type_copper: 1923 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1924 break; 1925 default: 1926 break; 1927 } 1928 1929 return E1000_SUCCESS; 1930} 1931 1932/** 1933 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1934 * @hw: pointer to the HW structure 1935 * @no_snoop: bitmap of snoop events 1936 * 1937 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1938 **/ 1939void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1940{ 1941 u32 gcr; 1942 1943 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1944 1945 if (hw->bus.type != e1000_bus_type_pci_express) 1946 return; 1947 1948 if (no_snoop) { 1949 gcr = E1000_READ_REG(hw, E1000_GCR); 1950 gcr &= ~(PCIE_NO_SNOOP_ALL); 1951 gcr |= no_snoop; 1952 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1953 } 1954} 1955 1956/** 1957 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1958 * @hw: pointer to the HW structure 1959 * 1960 * Returns E1000_SUCCESS if successful, else returns -10 1961 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1962 * the master requests to be disabled. 1963 * 1964 * Disables PCI-Express master access and verifies there are no pending 1965 * requests. 1966 **/ 1967s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1968{ 1969 u32 ctrl; 1970 s32 timeout = MASTER_DISABLE_TIMEOUT; 1971 1972 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1973 1974 if (hw->bus.type != e1000_bus_type_pci_express) 1975 return E1000_SUCCESS; 1976 1977 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1978 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1979 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1980 1981 while (timeout) { 1982 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1983 E1000_STATUS_GIO_MASTER_ENABLE)) 1984 break; 1985 usec_delay(100); 1986 timeout--; 1987 } 1988 1989 if (!timeout) { 1990 DEBUGOUT("Master requests are pending.\n"); 1991 return -E1000_ERR_MASTER_REQUESTS_PENDING; 1992 } 1993 1994 return E1000_SUCCESS; 1995} 1996 1997/** 1998 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 1999 * @hw: pointer to the HW structure 2000 * 2001 * Reset the Adaptive Interframe Spacing throttle to default values. 2002 **/ 2003void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2004{ 2005 struct e1000_mac_info *mac = &hw->mac; 2006 2007 DEBUGFUNC("e1000_reset_adaptive_generic"); 2008 2009 if (!mac->adaptive_ifs) { 2010 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2011 return; 2012 } 2013 2014 mac->current_ifs_val = 0; 2015 mac->ifs_min_val = IFS_MIN; 2016 mac->ifs_max_val = IFS_MAX; 2017 mac->ifs_step_size = IFS_STEP; 2018 mac->ifs_ratio = IFS_RATIO; 2019 2020 mac->in_ifs_mode = FALSE; 2021 E1000_WRITE_REG(hw, E1000_AIT, 0); 2022} 2023 2024/** 2025 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2026 * @hw: pointer to the HW structure 2027 * 2028 * Update the Adaptive Interframe Spacing Throttle value based on the 2029 * time between transmitted packets and time between collisions. 2030 **/ 2031void e1000_update_adaptive_generic(struct e1000_hw *hw) 2032{ 2033 struct e1000_mac_info *mac = &hw->mac; 2034 2035 DEBUGFUNC("e1000_update_adaptive_generic"); 2036 2037 if (!mac->adaptive_ifs) { 2038 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2039 return; 2040 } 2041 2042 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2043 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2044 mac->in_ifs_mode = TRUE; 2045 if (mac->current_ifs_val < mac->ifs_max_val) { 2046 if (!mac->current_ifs_val) 2047 mac->current_ifs_val = mac->ifs_min_val; 2048 else 2049 mac->current_ifs_val += 2050 mac->ifs_step_size; 2051 E1000_WRITE_REG(hw, E1000_AIT, 2052 mac->current_ifs_val); 2053 } 2054 } 2055 } else { 2056 if (mac->in_ifs_mode && 2057 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2058 mac->current_ifs_val = 0; 2059 mac->in_ifs_mode = FALSE; 2060 E1000_WRITE_REG(hw, E1000_AIT, 0); 2061 } 2062 } 2063} 2064 2065/** 2066 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2067 * @hw: pointer to the HW structure 2068 * 2069 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2070 * set, which is forced to MDI mode only. 2071 **/ 2072static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2073{ 2074 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2075 2076 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2077 DEBUGOUT("Invalid MDI setting detected\n"); 2078 hw->phy.mdix = 1; 2079 return -E1000_ERR_CONFIG; 2080 } 2081 2082 return E1000_SUCCESS; 2083} 2084 2085/** 2086 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2087 * @hw: pointer to the HW structure 2088 * @reg: 32bit register offset such as E1000_SCTL 2089 * @offset: register offset to write to 2090 * @data: data to write at register offset 2091 * 2092 * Writes an address/data control type register. There are several of these 2093 * and they all have the format address << 8 | data and bit 31 is polled for 2094 * completion. 2095 **/ 2096s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2097 u32 offset, u8 data) 2098{ 2099 u32 i, regvalue = 0; 2100 2101 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2102 2103 /* Set up the address and data */ 2104 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2105 E1000_WRITE_REG(hw, reg, regvalue); 2106 2107 /* Poll the ready bit to see if the MDI read completed */ 2108 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2109 usec_delay(5); 2110 regvalue = E1000_READ_REG(hw, reg); 2111 if (regvalue & E1000_GEN_CTL_READY) 2112 break; 2113 } 2114 if (!(regvalue & E1000_GEN_CTL_READY)) { 2115 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2116 return -E1000_ERR_PHY; 2117 } 2118 2119 return E1000_SUCCESS; 2120} 2121